CN109478534B - 纳米尺度的半导体器件的气隙间隔物构造 - Google Patents
纳米尺度的半导体器件的气隙间隔物构造 Download PDFInfo
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- CN109478534B CN109478534B CN201780041377.3A CN201780041377A CN109478534B CN 109478534 B CN109478534 B CN 109478534B CN 201780041377 A CN201780041377 A CN 201780041377A CN 109478534 B CN109478534 B CN 109478534B
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Classifications
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Abstract
提供了具有形成为半导体器件的BEOL或MOL层的一部分的气隙隔离物的半导体器件,以及制造这种气隙隔离物的方法。例如,一种方法包括在基板上形成第一金属结构和第二金属结构,其中第一和第二金属结构彼此相邻设置,在第一和第二金属结构之间设置绝缘材料。蚀刻绝缘材料以在第一和第二金属结构之间形成空间。使用夹断沉积工艺在第一和第二金属结构上沉积一层介电材料,以在第一和第二金属结构之间的空间中形成气隙,其中气隙的一部分在第一金属结构和第二金属结构中的至少一个的上表面上方延伸。
Description
技术领域
本领域一般涉及半导体制造,并且特别涉及用于制造半导体器件的气隙间隔物的技术。
背景技术
随着半导体制造技术继续朝着更小的设计规则和更高的集成密度发展,集成电路中的相邻结构之间的间隔变得越来越小。因此,在集成电路的相邻结构之间可能发生不希望的电容耦合,例如BEOL(线路后端)互连结构中的相邻金属线,FEOL(线路前端)器件的相邻触点(例如,MOL(线路中间)器件触点)等。这些与寄生电容相关的结构会导致半导体器件的性能下降。例如,晶体管触点之间的电容耦合会导致栅极-源极或栅极-漏极寄生电容增加,这会对晶体管的工作速度产生不利影响,增加集成电路的能耗等。此外,BEOL结构的相邻金属线之间的不需要的电容耦合可导致互连堆栈中增加的电阻-电容延迟(或等待时间)、串扰、增加的动态功耗等。
为了减少相邻导电结构之间的寄生耦合,半导体工业已采用低介电常数(低k)电介质和超低k(ULK)电介质(代替传统的SiO2(k=4.0))作为超大规模集成电路(ULSI)的MOL和BEOL层的绝缘材料。然而,低k电介质的出现以及激进的缩放已经导致这种低k材料的长期可靠性的关键挑战。例如,低k TDDB(时间相关的介电击穿)通常被认为是一个关键问题,因为低k材料通常具有比传统SiO2电介质更弱的固有击穿强度。通常,TDDB指的是当电介质经受随时间的变化的电压/电流偏置和温度应力时,电介质的绝缘特性的损失。TDDB导致漏电流增加,从而降低纳米级集成电路的性能。
发明内容
本发明的实施例包括具有形成为半导体器件的BEOL或MOL层的一部分的气隙间隔物的半导体器件,以及用于制造作为半导体器件的BEOL和MOL层的一部分的气隙间隔物的方法。
例如,一种制造半导体器件的方法包括在衬底上形成第一金属结构和第二金属结构,其中第一和第二金属结构彼此相邻设置,在第一和第二金属结构之间设置绝缘材料。蚀刻绝缘材料以在第一和第二金属结构之间形成空间。在第一和第二金属结构上沉积一层介电材料,以在第一和第二金属结构之间的空间中形成气隙,其中气隙的一部分在第一金属结构和第二金属结构中的至少一个的上表面上方延伸。
在一个实施例中,第一金属结构包括形成在BEOL互连结构的层间介电层中的第一金属线,第二金属结构包括形成在BEOL互连结构的ILD层中的第二金属线。
在另一实施例中,第一金属结构包括器件触点,第二金属结构包括晶体管的栅极结构。在一个实施例中,器件触点高于栅极结构,并且气隙的一部分在栅极结构上方延伸并且在器件触点的上表面下方延伸。
将在以下实施例的详细描述中描述其他实施例,其将结合附图来阅读。
附图说明
图1A和1B是根据本发明实施例的半导体器件的示意图,该半导体器件包括整体形成在半导体器件的BEOL结构内的气隙间隔物;
图2A和2B示意性地示出了与使用传统方法形成的气隙结构相比,使用根据本发明实施例的夹断沉积方法形成的气隙结构实现的BEOL结构的金属线之间的TDDB可靠性和减小的电容耦合的改进;
图3是根据本发明另一实施例的半导体器件的横截面示意侧视图,该半导体器件包括整体形成在半导体器件的BEOL结构内的气隙隔离物;
图4至10示意性地示出了根据本发明的实施例的用于制造图1A的半导体器件的方法,其中:
图4是处于制造的中间阶段的半导体器件的横截面示意侧视图,其中在ILD(层间电介质)层中形成开口图案;
图5是图4的半导体器件在沉积保形衬里材料层并沉积一层金属材料以填充ILD层中的开口之后的横截面示意性侧视图;
图6是图5的半导体器件将半导体结构的表面平坦化到ILD层以形成金属布线层之后的横截面示意性侧视图;
图7是图6的半导体器件在金属布线层的金属线上形成保护帽之后的横截面示意性侧视图;
图8是图7的半导体器件在蚀刻ILD层以在金属布线层的金属线之间形成空间之后的横截面示意性侧视图;
图9是图8的半导体器件在沉积绝缘材料的保形层以形成覆盖金属布线层的暴露表面的绝缘衬垫和ILD层之后的横截面示意性侧视图;以及
图10是图9的半导体器件的横截面示意性侧视图,其描述了使用非保形沉积工艺沉积介电材料以使夹断区域在金属布线层的金属线之间的空间上方的沉积的介电材料中开始形成的过程;
图11是根据本发明的另一个实施例的半导体器件的横截面示意侧视图,该半导体器件包括整体形成在半导体器件的FEOL/MOL结构内的气隙间隔物;
图12至19示意性地示出了根据本发明的实施例的用于制造图11的半导体器件的方法,其中:
图12是处于制造的中间阶段的半导体器件的横截面示意图,其中在半导体衬底上形成垂直晶体管结构;
图13是图12的半导体器件在图案化预金属电介质层以在垂直晶体管结构的栅极结构之间形成接触开口之后的横截面示意性侧视图;
图14是图13的半导体器件在半导体器件的表面上形成保形衬垫层以在衬垫材料上给接触开口使用衬里材料安衬里之后的横截面示意性侧视图;
图15是图14的半导体器件在沉积一层金属材料以用金属材料填充接触开口并平坦化半导体器件的表面以形成MOL器件触点之后的横截面示意性侧视图;
图16是图15的半导体器件在凹陷栅极覆盖层和垂直晶体管结构的栅极结构的侧壁间隔物之后的横截面侧视图;
图17是图16的半导体器件在沉积绝缘材料的保形层以给栅极结构的暴露表面上和MOL器件触点安衬里形成绝缘衬垫之后的横截面示意性侧视图;
图18是图17的半导体器件在使用非保形沉积工艺沉积介电材料,以在栅极结构和MOL器件触点之间的空间中形成气隙得到夹断区域之后的横截面示意性侧视图;以及
图19是图18的半导体器件在将半导体器件的表面平面化到MOL器件触点并沉积作为BEOL结构的第一互连层的一部分的ILD层之后的横截面示意性侧视图。
具体实施方式
现在将进一步详细描述关于具有形成为BEOL和/或MOL层的一部分的气隙间隔物的半导体集成电路器件,以及用于制造半导体集成电路器件的作为BEOL和/或MOL层的一部分的气隙间隔物的方法的实施例。特别地,如下面进一步详细说明的,本发明的实施例包括使用“夹断”沉积技术制造气隙隔离物的方法,该技术利用某些介电材料和沉积技术来控制气隙隔离物的尺寸和形状。由此形成并优化用于目标应用的气隙间隔物的形成。这里讨论的用于形成气隙间隔物的示例性夹断沉积方法提供了半导体集成电路器件的BEOL和MOL层中的改进的TDDB可靠性以及优化的电容减少。
应理解,附图中所示的各种层、结构和区域是未按比例绘制的示意图。另外,为了便于解释,通常用于形成半导体器件或结构的一种或多种层、结构和区域可能未在给定附图中明确示出。这并不意味着从实际的半导体结构中省略了未明确示出的任何层、结构和区域。
此外,应理解,本文所讨论的实施方案不限于本文所示的特定材料、特征和处理步骤。特别地,关于半导体处理步骤,要强调的是,这里提供的描述并不旨在包含形成功能半导体集成电路器件可能需要的所有处理步骤。相反,为了描述的经济性,有目的地没有描述在形成半导体器件中常用的某些处理步骤,例如湿法清洗和退火步骤。
此外,在整个附图中使用相同或相似的附图标记来表示相同或相似的特征、元件或结构,因此,对于每个附图,将不再重复相同或相似的特征、元件或结构的详细说明。应理解,本文所用的关于厚度、宽度、百分比、范围等的术语“约”或“基本上”旨在表示接近或接近但不精确。例如,如本文所用的术语“约”或“基本上”意味着存在小的误差范围,例如1%或小于所述量。
图1A和1B是根据本发明实施例的半导体器件100的示意图,该半导体器件100包括整体形成在半导体器件的BEOL结构内的气隙间隔物。图1A是图1B中沿着线1A-1A截取的半导体器件100的横截面示意图。图1B是沿着包括图1A中所示的线1B-1B的平面的半导体器件100的示意性平面图。更具体地,如图1A和图1B所示的各个XYZ笛卡尔坐标所示,图1A是半导体器件100在X-Z平面中的示意性横截面图。图1B是示出X-Y平面内的各种元件的布局的平面图。应当理解,这里使用的术语“垂直”或“垂直方向”表示图中所示的笛卡尔坐标的Z方向,并且这里使用的术语“水平”或“水平方向”表示X-图中所示的笛卡尔坐标的X方向和/或Y方向。
特别地,图1A示意性地示出了包括衬底110、FEOL/MOL结构120和BEOL结构130的半导体器件100。在一个实施例中,衬底110包括由例如硅或其他类型的半导体衬底形成的块状半导体衬底,其他类型的半导体衬底是通常用于块状半导体制造工艺的材料,例如锗、硅锗合金、碳化硅、硅-锗碳化物合金或化合物半导体材料(例如III-V和II-VI)。化合物半导体材料的非限制性实例包括砷化镓、砷化铟和磷化铟。基础衬底100的厚度将根据应用而变化。在另一实施例中,衬底110包括SOI(绝缘体上硅)衬底,其包括设置在基础半导体衬底(例如,硅衬底)与有源半导体层(例如,有源硅)之间的绝缘层(例如,氧化物层),有源半导体层中有源电路元件(例如,场效应晶体管)形成为FEOL层的一部分。
具体地,FEOL/MOL结构120包括形成在衬底110上的FEOL层。FEOL层包括形成在半导体衬底110的有源表面中或之上的各种半导体器件和组件,以提供用于的目标应用的集成电路。例如,FEOL层包括FET器件(例如FinFET器件,平面MOSFET器件等)、双极晶体管、二极管、电容器、电感器、电阻器、隔离器件等,它们形成在半导体衬底110的有源表面之中或之上。通常,FEOL工艺通常包括制备衬底110(或晶片)、形成隔离结构(例如,浅沟槽隔离)、形成器件阱、图案化栅极结构、形成间隔物、形成源极/漏极区域(例如,通孔注入)、在源极/漏极区域上形成硅化物接触、形成应力衬垫等。
FEOL/MOL结构120还包括在FEOL层上形成的MOL层。通常,MOL层包括PMD(预金属电介质层)和在PMD层中形成的导电触点(例如,通孔触点)。PMD层在FEOL层的组件和器件上形成。在PMD层中形成开口图案,并且使用诸如钨的导电材料填充开口,以形成与FEOL层的集成电路的器件端子(例如,源极/漏极区域、栅极触点等)电接触的导电通孔触点。MOL层的导电通孔触点提供FEOL层的集成电路与BEOL结构130的第一金属化层之间的电连接。
在FEOL/MOL结构120上形成BEOL结构130,以连接FEOL层的各种集成电路部件。如本领域中已知的,BEOL结构包括多层介电材料和嵌入到介电材料中的金属化层次。BEOL金属化包括水平布线、互连、焊盘等,以及以导电通孔形式的垂直布线,该导电通孔形成BEOL结构的不同互连级别之间的连接。BEOL制造工艺涉及多层电介质和金属材料的连续沉积和图案化,以在FEOL器件之间形成电连接网络,并提供与外部元件的I/O连接。
在图1A的示例实施例中,BEOL结构130包括第一互连级别140和第二互连级别150。第一互连级140被一般地描绘,并且可以包括一个或多个低k层间电介质(ILD)层和金属通孔和布线级别(例如,铜镶嵌结构)。在第一互连级别140和第二互连级别150之间形成覆盖层148。覆盖层148用于使第一互连级别140的金属化与ILD层151的介电材料绝缘。例如,覆盖层148用于改善互连可靠性并防止铜金属化扩散到第二互连级别150的ILD层151中。覆盖层148可包括任何合适的绝缘或介电材料,包括但不限于氮化硅(SiN)、碳化硅(SiC)、碳氮化硅(SiCN)、氢化碳化硅(SiCH)、包括相同或不同类型的介电材料的多层叠层等。可以使用标准沉积技术(例如,化学蒸汽沉积)沉积覆盖层148。覆盖层148可以形成为具有约2nm至约60nm的厚度。
第二互连级别150包括ILD层151和形成在ILD层151中的金属布线层152。ILD层151可以使用任何合适的介电材料形成,包括但不限于氧化硅(例如SiO2)),SiN(例如,(Si3N4)、氢化硅碳氧化物(SiCOH)、硅基低k电介质、多孔电介质或其他已知的ULK(超低k)电介质材料。ILD层151可以使用已知的沉积技术,例如ALD(原子层沉积)、CVD(化学气相沉积)、PECVD(等离子体增强CVD)或PVD(物理气相沉积)沉积。ILD层151的厚度将根据应用不同而变化,例如,可以具有约30nm至约200nm的厚度。
金属布线层152包括多个紧密间隔的金属线152-1、152-2、152-3、152-4、152-5和152-6,它们形成在沟槽/开口内,沟槽/开口在ILD层151中图案化并填充金属材料以形成金属线。沟槽/开口衬有保形衬垫层153,其用作阻挡扩散层以防止金属材料(例如,Cu)迁移到ILD层151中,以及用作粘附层以提供对金属材料(例如,用于填充ILD层151中的沟槽/开口并形成金属线152-1、...、152-6的Cu)的良好粘附性。
如图1A中进一步描绘的那样,第二互连层150还包括选择性地形成在金属线152-1、152-2、152-3、152-4、152-5和152-6的上表面上的保护帽154、保形地覆盖金属布线层152的保形绝缘衬垫155、以及使用夹断沉积技术沉积,以在金属线152-1、152-2、152-3、152-4、152-5和152-6之间形成气隙隔离物158的电介质覆盖层156。保护帽154和保形绝缘衬垫155用于保护金属布线152免受可能由后续处理步骤和环境条件引起的潜在结构损坏或污染。用于形成保护帽154和保形绝缘衬垫155的示例材料和方法将在下面参考图7-9进一步详细讨论。
作为减小金属布线层152的相邻金属线之间的寄生电容耦合的手段,气隙隔离物158形成在金属布线层152的金属线152-1、152-2、152-3、152-4、152-5和152-6之间的空间中。如下面进一步详细说明的,作为BEOL制造工艺的一部分执行电介质气隙集成工艺,其中蚀刻ILD层151的部分电介质材料以在布线层152的金属线金属线152-1、152-2、152-3、152-4、152-5和152-6之间形成空间。使用非保形沉积介电盖层156(例如,化学气相沉积)的沉积工艺以沉积介电材料,该介电材料在布线层152的金属线之间的空隙的上部上方形成“夹断”区域156-1,从而形成气隙隔离物158。如图1A所示,在本发明的一个实施例中,夹断区域156-1形成在金属布线层152的金属线152-1、...、152-6的上表面上方,如虚线1B-1B所示。在这方面,形成在金属线152-1、...、152-6之间的气隙隔离物158垂直地延伸到金属线152-1、...、152-6上方的介电覆盖层156中。
此外,在本发明的一个实施例中,如图1B所示,形成在金属线152-1、...、152-6之间的气隙隔离物158水平地延伸(例如,沿Y方向)经过相邻金属线的端部。特别地,图1B示出了金属布线层152的示例交叉梳状布局图案,其中金属线152-1、152-3和152-5的一端共同连接到细长金属线152-7,并且其中金属线152-2、152-4和152-6的一端连接到细长的金属线152-8。如图1B所示,气隙隔离物158水平地延伸超过金属线152-1、...、152-6的开口(未连接)端。与传统的气隙结构相比,图1A和1B中所示的气隙隔离物158的尺寸和形状提供了改进的TDDB可靠性,以及减的小金属线之间的电容耦合,其原因现在将参考图2A和2B进一步详细讨论。
图2A和2B示意性地示出了根据本发明实施例的与使用传统方法形成的气隙结构相比,使用夹断沉积方法形成的气隙结构实现的BEDB结构的金属线之间的TDDB可靠性和减小的电容耦合的改进。特别地,图2A示意性地示出了图1A的金属布线层152的一部分,其包括金属线152-1和152-2,以及通过使用根据本发明实施例的夹断沉积工艺形成介电盖层156而在金属线之间形成的气隙158。如图2A所示,金属线152-1和152-2以及相关的衬垫153形成为具有宽度W,并且间隔距离S。图2B示意性地示出了包括气隙168的半导体结构,气隙168沉积在具有与图2中相同的宽度W和间隔S的相同的两条金属线152-1和152-2之间。但是,其中通过使用传统的夹断沉积工艺形成介电盖层166来形成气隙168。
如图2A所示,“夹断”区域156-1形成在电介质盖层156中,使得气隙158在金属线152-1和152-2的上表面上方延伸。相反,如图2B所示,传统的夹断沉积工艺导致在金属线152-1和152-2的上表面下方的介电盖层166中形成夹断区域166-1,使得产生的气隙168不延伸到金属线152-1和152-2之上。此外,如图2A和2B所示,使用传统的夹断沉积工艺如图2B所示沉积在金属线152-1和152-2之间的空间中的侧壁和底表面上的介电材料的量明显大于使用根据本发明实施例的夹断沉积工艺如图2A所示沉积在金属线152-1和152-2之间的空间中的侧壁和底表面上的电介质材料的量。结果,图2A得到的气隙158的体积V1明显大于图2中所示的所得气隙168的体积V2。
与图2B所示的传统结构相比,与图2A中的结构相关的具有各种优点。例如,气隙158的较大体积V1(具有设置在金属线之间的空间中的较少介电材料)导致金属线152-1和金属线152-2之间的较小寄生电容(与如图2B的结构相比)。实际上,与图2B相比,在图2A中的金属线152-1和152-2之间的空间中具有降低的有效介电常数,因为在图2A的金属线152-1和152-2之间的空间中存在较少的介电材料和大的空气体积V1(k=1)。
另外,与图2B的结构相比,图2A的结构提供了改进的TDDB可靠性。特别地,如图2A所示,由于气隙158在金属线152-1和152-2上方延伸,所以在金属线152-1和152-2的关键界面之间存在长的扩散/传导路径P1(关键界面是介电盖层156与金属线152-1和152-2的上表面之间的界面)。这与图2B所示结构中金属线152-1和152-2的关键界面之间的介电盖层166中较短的扩散/导电路径P2形成对比。图2A或2B结构中的TDDB失效机制将由电介质材料的击穿以及由于电子隧穿电流而在金属线152-1和152-2的上表面之间形成穿过电介质材料的导电路径引起。与图2B所示的结构相比,图2A中所示结构中的扩散路径P1越长,图2A中结合可选地使用具有优异介电击穿强度的致密电介质垫片155材料,将提供改进的TDDB结构的可靠性。
此外,如图1B所示,气隙间隔件158通过金属线的端部水平延伸将进一步提高TDDB的可靠性并减少电容耦合,原因与参考图2A讨论的相同。特别地,如图1B所示,气隙158延伸经过金属线152-1的端部,例如,将在金属线152-1和相邻的金属线152-2的开口端处的关键界面之间提供长的扩散/传导路径。在图1B的替换实施例中,可以在细长金属线152-8与金属线152-1、152-2和152-5的相邻开口端之间形成气隙隔离物,并且可以在细长金属线152-7和金属线152-2,152-4和152-6的相邻开口端之间形成气隙隔离物,从而进一步优化TDDB可靠性并减少交叉梳状结构之间的电容耦合。
图3是根据本发明另一实施例的半导体器件的横截面示意侧视图,该半导体器件包括整体形成在半导体器件的BEOL结构内的气隙隔离物。特别地,图3示意性地示出了半导体器件100',其结构类似于图1A/1B中所示的半导体器件100,除了图3中所示的气隙隔离物158不会延伸超过金属布线层152的金属线的底面。利用这种结构,ILD层151将向下凹陷到金属线的底部水平(与凹陷在金属线底部下方相比,如图8所示,以形成图1A中所示的延伸气隙隔离物。)在本发明的其他实施例中,图1A和图3示出了具有第一和第二互连级别140和150的BEOL结构130,BEOL结构130可以具有在第二互连级别150上形成的一个或多个附加互连级。这样的附加互连级可以使用利用本文讨论的技术和材料的气隙间隔器形成。
制造图1A(和图3)的半导体器件100的方法参考图4至10更详细地讨论图,图4至10示意性地示出了处于各个制造阶段的半导体器件100。例如,图4是根据本发明的一个实施例的处于制造的中间阶段的半导体器件100的横截面示意图,其中在ILD层151中形成开口151-1的图案(例如,包括沟槽的镶嵌开口和通孔开口)。特别地,图4示意性地示出了在依次在衬底110的顶部上形成FEOL/MOL结构120、第一互连级别140、覆盖层148和ILD层151之后,在图案化ILD层151以形成ILD层151中的开口之后,在制造的中间阶段的图1A的半导体器件100。在沉积ILD层151之后,可以执行标准光刻和蚀刻工艺以蚀刻ILD层151中的开口151-1,其随后用金属材料填充以形成图1A的金属布线层152。应注意,虽然在ILD层151中未示出垂直通孔,但应理解,垂直通孔将存在于第二互连级别150中以提供到底层互连级别140中的金属化的垂直连接。
在图4中,开口151-1示出为具有宽度W并且间隔开距离S。在本发明的一个实施例中,在紧密间隔的金属线之间使用夹断沉积方法形成气隙间隔物的情况下,开口的宽度W(其中形成金属线)可以在约2nm至约25nm的范围内,优选的范围为约6nm至约10nm。此外,在一个实施例中,金属线之间的间距S可以在约2nm至约25nm的范围内,优选的范围为约6nm至约10nm。
示例性制造工艺中的下一个工艺模块包括使用如图5和6中示意性示出的工艺流程来形成图1A中所示的金属布线层152。特别地,图5是图4的半导体器件在沉积衬垫材料153A的保形层并在衬垫材料153A的保形层上沉积金属材料层152A以填充ILD层151中的开口151-1之后的横截面示意图。此外,图6是图5的半导体器件将半导体结构的表面平坦化到ILD层151以形成金属布线层152之后的横截面示意图。金属布线层152可以使用已知材料和已知技术形成。
例如,衬垫材料153A的保形层优选地被沉积以使用薄衬垫层给在ILD层151中的开口151-1的侧壁和底表面上安衬里。薄衬垫层可以通过保形地沉积一个或多个薄层材料,例如氮化钽(TaN)、钴(Co)、或钌(Ru)、或锰(Mn)或氮化锰(MnN))或适用于给定应用的其他衬里材料(或衬里材料的组合,例如Ta/TaN、TiN、CoWP、NiMoP、NiMoB)形成。薄衬垫层用于多种目的。例如,薄衬垫层用作阻挡扩散层,以防止金属材料(例如,Cu)迁移/扩散到ILD层151中。此外,薄衬垫层用作粘附层以对用于填充ILD层151中的开口151-1的金属材料层152A(例如,Cu)提供良好的粘附性。
在一个实施例中,金属材料层152A包括金属材料,例如铜(Cu)、铝(Al)、钨(W)、钴(Co)或钌(Ru),其中使用已知技术,例如电镀、化学镀、CVD,PVD或方法的组合进行沉积。在用导电材料填充ILD层151中的开口151-1之前,可以使用合适的沉积技术,例如ALD、CVD或PVD,可选地沉积(在保形衬垫层153A上)薄种子层(例如,Cu种子层)。种子层可以由增强在底层材料上的金属材料的粘附性的材料,并且在随后的电镀过程中用作催化材料形成。例如,可以使用PVD在衬底的表面上沉积薄的保形Cu籽晶层,然后电镀Cu以填充在ILD层151中形成的开口151-1(例如,沟槽和通孔),并且因此形成Cu金属化层152。然后,通过执行化学机械抛光工艺(CMP)来去除覆盖层衬垫、种子和金属化材料,以将半导体结构的表面平坦化到ILD层151,从而形成如图6所示的中间结构。
在本发明的一个实施例中,在执行CMP工艺之后,可以在金属线152-1、...、152-6的暴露表面上形成保护层,以保护金属化免受作为后续处理条件和环境的结果的潜在的损坏。例如,图7是根据本发明的一个实施例,在金属线152-1、...、152-6上形成保护帽154之后,图6的半导体器件的横截面示意图。在一个实施例中,对于铜金属化,可以使用选择性Co沉积工艺形成保护帽154,以选择性地在金属线152-1、...、152-6的暴露表面上沉积Co的薄覆盖层。在本发明的其他实施例中,保护帽154可以由其他材料形成,例如钽(Ta)或钌(Ru)。金属线152-1、...、152-6上的保护帽154是可选的特征,如果需要,当使用下文讨论的技术形成气隙隔离物和其他结构时,可选的特征可以允许更积极的蚀刻条件等。
制造工艺中的下一步骤包括使用如图8、9和10中示意性描绘的工艺流程在第二互连级别150中形成气隙间隔物。特别地,图8是根据本发明的一个实施例,在蚀刻ILD层151的暴露部分以在金属线152-1,...,152-6之间形成空间151-2之后,图7的半导体器件的横截面示意图。在一个实施例中,可以使用任何合适的掩模(例如,光致抗蚀剂掩模)和蚀刻技术(例如,RIE(反应离子蚀刻))来凹陷ILD层151的部分并形成空间151-2,如图8所示。例如,在一个实施例中,可使用基于氟的蚀刻剂的干蚀刻技术蚀刻掉ILD层151的介电材料以形成空间151-2。在一个实施例中,形成空间151-2使得ILD层151的凹陷表面在金属线152-1,...,152-6的底表面下方,如图8所示。在另一个实施例中,可以执行蚀刻工艺,使得空间151-2向下凹陷到金属布线152的底表面的水平(参见图3)。在金属布线152的金属线相隔较远的区域中,不去除ILD层151,因为假设宽间隔金属线之间的线间电容可以忽略不计。
该工艺的下一步骤包括在图8的半导体结构上沉积保形绝缘材料层,以形成保形绝缘衬垫155,如图9所示。保形绝缘衬垫155是可选的保护特征,其可以在夹断沉积工艺之前形成,以对ILD层151和金属布线层152的暴露表面提供额外的保护。例如,在图9所示的示例性实施例中,当保形衬垫层153为金属线152-1,...,152-6的侧壁提供一些保护时,保形绝缘衬垫155可以提供额外的保护以防止当金属线由铜形成并且衬垫层153不足以防止氧气从随后形成的气隙隔离物158扩散到金属线中时金属线152-1,......,152的氧化。实际上,当气隙隔离物158随后形成为具有近真空环境时,气隙隔离物158中仍存在一定水平的氧气,当衬里层153允许气隙隔离物158中的氧气残留以通过衬垫层153扩散到金属线时,这会导致铜金属线的氧化。
此外,保形绝缘衬垫155可以形成有一个或多个坚固的超薄介电材料层,其具有所需的电气和机械特性,例如低泄漏、高电击穿、疏水等,并且可以承受来自后续的半导体处理步骤的低损伤。例如,保形绝缘衬垫155可以由介电材料,例如SiN、SiCN、SiNO、SiCNO、SiBN、SiCBN、SiC、或具有如上所述的所需电气/机械特性的其他介电材料形成。在一个实施例中,形成保形绝缘衬垫155,其厚度在约0.5nm至约5nm的范围内。保形绝缘衬垫155可以由相同或不同电介质材料的多个保形层形成,其使用循环沉积工艺沉积。例如,在一个实施例中,保形绝缘衬垫155可以由多个SiN的薄保形层(例如,0.1nm-0.2nm厚的SiN层)形成,其顺序地沉积以形成具有总期望厚度的SiN衬垫层。
如图9所示,在形成保形绝缘衬垫155之后,金属布线层152的金属线之间的空间151-2显示为具有初始体积Vi。特别地,在形成保形绝缘衬垫155的一个实施例中,体积Vi由保形绝缘衬垫155的侧壁和底表面以及虚线L限定,虚线L表示在金属布线层152之上的保形绝缘衬垫155的上表面。在本发明的另一个实施例中,当没有形成保形绝缘衬垫155时,初始体积Vi将由衬垫层153的暴露表面,ILD层151的凹陷表面和金属布线层152的金属线的上表面限定。如下所述,根据本发明的一个实施例,在使用夹断的沉积方法形成气隙隔离物158之后,初始体积Vi的重要部分保留在金属线之间的空间151-2中。
制造工艺中的下一步骤包括在图9的半导体结构上使用夹断沉积工艺沉积介电材料以在金属布线层152的金属线之间的间隔物151-2中形成气隙隔离物158。图10根据本发明的实施例示意性地示出了使用非保形沉积工艺(例如,PECVD或PVD)沉积介电材料层156A,以使得夹断区域在金属布线层152的金属线之间的空间151-2之上开始形成沉积的介电材料156A的过程。图1A示出了在夹断沉积工艺完成时的半导体器件100,其中介电盖层156在介电盖层中使用夹断区156-1形成,并且气隙隔离物158在在金属布线层152的金属线之间的空间151-2中形成。
根据本发明的实施例,可以控制通过夹断沉积形成的气隙隔离物的结构特征(例如,尺寸、形状、体积等),例如,基于(i)用于形成介电覆盖层156的介电材料的类型,和/或(ii)用于执行夹断沉积的沉积工艺和相关的沉积参数(例如,气体流速、RF功率、压力、沉积速率等)。例如,在本发明的一个实施例中,通过低k电介质材料(例如,k在约2.0至约5.0的范围内)的PECVD沉积形成覆盖层158。这种低k介电材料包括但不限于SiCOH、多孔p-SiCOH、SiCN、富碳SiCNH、p-SiCNH、SiN、SiC等。SiCOH介电材料具有介电常数k=2.7,多孔SiCOH材料的介电常数约为2.3-2.4。在本发明的一个示例实施例中,通过使用具有以下沉积参数的工业平行板单晶片300mm CVD反应器的等离子体CVD沉积工艺沉积SiCN电介质膜来实施夹断沉积工艺:气体[三甲基硅烷(200-500标准立方厘米每分钟(sccm))和氨(300-800sccm)];射频功率[300-600瓦];压力[2-6托];沉积速率[0.5-5nm/sec]。
此外,可以控制PECVD沉积的电介质材料的保形水平,以实现在相邻金属线的表面上方或相邻金属线的表面下方的电介质覆盖层的“夹断”。在纵横比R为2(其中R=沟槽深度/沟槽开口)的沟槽上沉积的绝缘/电介质膜的术语“保形水平”在本文中定义为沉积在沟槽位置中间的侧壁上的绝缘/电介质膜的厚度除以沟槽位置顶部的绝缘/介电膜的厚度的比率。例如,在沟槽结构上沉积厚度为3nm的绝缘/介电膜的33%水平的保形性,其具有12nm的开口和24nm的深度(纵横比2)应该在沟槽中间的侧壁上厚度应为约1nm以及沟槽顶部3nm(保形水平=1nm/3nm~33%)。
例如,对于约40%或更小的保形水平,如图1A中所示的“夹断”区域156-1可以在金属布线层152的金属线上方的电介质盖层156中形成。这导致在金属布线层152的金属线上方延伸的气隙隔离物158的形成。另一方面,如果保形性水平大于约40%,则“夹断”区域将在金属布线层152的金属线的上表面下方的介电盖层中形成。这将导致不延伸到金属布线层152的金属线之上的气隙经间隔物的形成。
根据给定的应用和气隙/空气隔离物结构的尺寸,可以通过调节沉积工艺参数来实现PECVD沉积的介电材料的目标保形性水平。例如,对于PECVD介电材料,例如SiN、SiCN、SiCOH、多孔p-SiCOH和其他ULK介电材料,通过增加RF功率、增加压力和/或增加沉积速率(例如,增加前体材料的流速)可以获得较低水平的保形性。例如,如图1A和3所示,随着保形性水平降低,在金属线上方形成“夹断”区域,在空间151-2内的暴露侧壁和底表面上的具有最少的电介质材料沉积,导致形成大的、并且大容量的在金属布线层152的金属线上方延伸的空气间隙隔离物158。
应注意,已经制造了如图1A和3中所示的实验性BEOL测试结构,其中使用本文讨论的“夹断”沉积方法形成包含ULK材料(例如,SiCOH,多孔p-SiCOH)的非保形覆盖层(保形性小于40%)以获得在紧密间隔的间线之间的大的,大容量的气隙间隔物,其中如图1A和3所示,气隙间隔物在金属线上方延伸。此外,实验结果表明,这种非保形覆盖层的夹断沉积导致在金属线之间的空气隙的侧壁和底表面上非常少地介电材料沉积。特别地,假设金属线之间的空间151-2在形成覆盖层之前具有初始体积Vi(如图9所示),已经制造出实验性的BEOL测试结构,其中在使用如本文所述的非保形夹断沉积工艺形成气隙隔离物之后,产生的体积已经实现了约为nVi(其中n在约0.70至接近1.0的范围内)。
空气的介电常数约为1,这远小于用于形成保形绝缘衬垫155和介电覆盖层156的介电材料的介电常数。在这方面,使用本文所述的技术,严格控制的能力并且最小化沉积在金属布线层152的相邻金属线之间的空间151-2内的介电材料的量,使得能够通过降低有效介电常数(并且因此寄生电容)来优化BEOL结构的电性能。此外,使用ULK电介质材料执行夹断沉积以形成低k电介质盖层156和大体积气隙隔离物158的能力导致整体降低BEOL结构的有效介电常数(从而降低寄生电容)。
虽然上面讨论的本发明的示例性实施例示出了作为BEOL结构的一部分气隙间隔物的形成,但是可以应用类似的技术来形成作为FEOL/MOL结构的一部分以减少相邻FEOL/MOL结构之间的寄生耦合的气隙间隔物。例如,可以使用如现在将参考图11-19进一步详细讨论的技术在FEOL/MOL结构中的MOL器件触点和垂直晶体管器件的金属栅极结构之间形成气隙间隔物。
图11是根据本发明的另一个实施例的半导体器件的侧视横截面示意图,该半导体器件包括在半导体器件的FEOL/MOL结构内整体形成的气隙间隔物。特别地,图11示意性地示出了半导体器件200,其包括衬底210/215以及形成在基板210/215上的多个垂直晶体管结构M1、M2、M3(参见图12),衬底210/215包括体衬底层210和绝缘层215(例如,SOI衬底的掩埋氧化物层),垂直晶体管结构M1、M2、M3具有标准结构框架,包括半导体鳍片220(在X方向沿衬底延伸)、外延生长的源极(S)/漏极(D)区域225、以及相应的金属栅极结构230-1、230-2和230-3。半导体鳍片220用作由相应的金属栅极结构230-1、230-2、230-3围绕的半导体鳍片220的区域中的垂直晶体管结构M1、M2、M3的垂直沟道。半导体鳍片220可以通过蚀刻/图案化形成在绝缘层215顶部的有源硅层(例如,SOI衬底的SOI层)来形成。半导体鳍片220未在图11中具体示出,但是半导体鳍片220的上表面在图11中用虚线表示(即,半导体鳍片220的沟道部分被栅极结构230-1、230-2和230-3覆盖,并且从栅极结构延伸的半导体鳍片220的部分被封装在生长在半导体鳍片220的暴露表面之上的外延材料中)。
在一个实施例中,金属栅极结构230-1、230-2和230-3各自包括形成在半导体鳍片220的垂直侧壁和上表面上的保形高k金属栅极堆叠结构,以及形成在高k金属栅堆叠结构上方的栅电极。每个保形高k金属栅极堆叠结构包括形成在半导体鳍片220的侧壁和上表面上的栅极电介质材料的保形层(例如,诸如HfO2、Al2O3等的高k电介质材料),以及形成在栅极介电材料的保形层上的金属功函数金属材料的保形层(例如,Zr、W、Ta、Hf、Ti、Al、Ru、Pa、TaN、TiN等)。形成在高k金属栅极堆叠结构上的栅电极材料包括低电阻导电材料,包括但不限于钨、铝或通常用于形成栅电极结构的任何金属或导电材料。
外延源极(S)/漏极(D)区域225包括外延生长在从金属栅极结构230-1、230-2、230-3延伸出的半导体鳍状结构220的暴露部分上的外延半导体材料(例如,SiGe,III-V化合物半导体材料等)。作为半导体器件200的MOL层的一部分形成多个MOL器件触点240/245,以提供到源/漏区225的垂直接触。每个MOL器件触点240/245包括衬垫/阻挡层240和导电通路245。
如图11中进一步所示,金属栅极结构230-1、230-2、230-3通过绝缘材料层234、250、260和气隙隔离物262与MOL触点240/245和其他周围结构电绝缘。绝缘材料层包括下侧壁间隔物234、保形绝缘衬垫250和介电覆盖层260。下侧壁间隔物234使金属栅极结构230-1、230-2、230-3与相邻的源极/漏极区域223电绝缘。保形绝缘衬垫250(其组成和功能与BEOL结构的保形绝缘衬垫155相似,图1A)保形地覆盖MOL器件触点240/245和金属栅极结构230-1,230-2、230-3的侧壁表面。保形绝缘衬垫250是可选的特征,其可以形成为保护MOL器件触点240/245和金属栅极结构230-1、230-2、230-3免受可能由后续处理步骤和环境条件引起的结构损坏或污染。
根据本发明的实施例,通过使用夹断沉积工艺沉积低k电介质材料来形成电介质覆盖层260,以使用低k电介质材料封装金属栅极结构230-1、230-2、230-3的上部区域,并且在金属栅极结构和MOL器件触点之间形成气隙隔离物262。用于制造气隙隔离物262的工艺流程将在下面进一步详细讨论。如图11所示,气隙隔离物262相对较大且体积较大,并且在金属栅极结构230-1、230-2、230-3上方垂直延伸。出于与上面所讨论的关于如图2A所示的BEOL气隙隔离物158类似的原因,图11所示的FEOL/MOL气隙隔离物262的尺寸和形状提供了改进的TDDB可靠性,以及MOL器件触点和金属栅极结构之间的电容耦合减小。
例如,大体积气隙隔离物262减小了金属栅极结构230-1、230-2、230-3与MOL器件触点240/245之间的空间中的有效介电常数。另外,如图11所示,由于气隙隔离物262在金属栅极结构230-1、230-2、230-3上方延伸,在金属栅极结构230-1、230-2、230-3的关键界面(关键界面是介电覆盖层260与金属栅极结构230-1、230-2、230-3的上表面之间的界面)和相邻的MOL器件触点240/245之间存在相对长的扩散/传导路径P。这样,图11中的气隙隔离物262用于增加FEOL/MOL半导体结构的TDDB可靠性。
图11还示出了在FEOL/MOL层上形成的BEOL结构的第一互连级别,其中第一互连级别包括ILD层270,以及形成在ILD层270中的、与相应的MOL器件触点240/245电接触的多个金属线272/274。通过蚀刻ILD层270中的开口(例如,沟槽或通孔),用阻挡衬垫层272衬里开口并使用已知技术用诸如铜的金属材料274填充开口,形成金属线272/274。
用于制造图11的半导体器件200的工艺流程,现在将参考图12和19更详细地讨论,图12至19示意性地示出了处于各个制造阶段的半导体器件200。首先,图12是处于制造的中间阶段的半导体器件200的横截面示意图,其中在半导体衬底210/215上形成垂直晶体管结构M1、M2和M3。在一个实施例中,衬底210/215包括SOI(绝缘体上硅)衬底,其中基础衬底210由硅或其他类型的半导体衬底材料形成,这些材料通常用于诸如锗、硅-锗合金、碳化硅、硅-锗碳化物合金或化合物半导体材料(例如III-V和II-VI)的体半导体制造工艺中。化合物半导体材料的非限制性实例包括砷化镓、砷化铟和磷化铟。绝缘层215(例如,氧化物层)设置在基础半导体基板210和有源半导体层(例如,有源硅层)之间,其中使用已知方法将有源半导体层图案化以制造半导体鳍状结构220。而且,可以使用已知方法在半导体鳍形结构220的暴露部分上外延生长外延源/漏区225。
如图12中进一步所示,金属栅极结构230-1、230-2和230-3被封装在包括绝缘覆盖层232和侧壁隔离物234的绝缘/介电材料结构中。.覆盖层232和侧壁隔离物234使用已知技术和绝缘材料(例如,SiN)制造。金属栅极结构230-1、230-2和230-3可以例如通过RMG(替代金属栅极)工艺形成,其中在形成外延源/漏区225之后,但在形成MOL器件触点之前,最初形成伪栅极结构,然后用金属栅极结构230-1、230-2,230-3代替。在图12的实施例中,假设已经完成RMG工艺,导致金属栅极结构230-1、230-2,230-3的形成,并且已经沉积并平坦化PMD(金属前电介质)层236,得到图12所示的结构。
通过在半导体器件的表面上沉积一层介电材料,然后将介电材料平面化到覆盖层232的上表面来形成PMD层236。可以用任何合适的绝缘/介电材料,例如氧化硅、氮化硅、氢化硅碳氧化物、硅基低k电介质、多孔电介质、或包括多孔有机电介质的有机电介质等形成PMD层236。PMD层236可以使用已知的沉积技术,例如ALD、CVD、PECVD、旋涂沉积或PVD,然后是标准平坦化工艺(例如,CMP)。
下一个处理模块包括使用如图13、14和15中示意性示出的处理流程来形成MOL设备触点。特别地,图13是图12的半导体器件在图案化PMD层236以在垂直晶体管结构M1、M2、M3的栅极结构230-1、230-2、230-3之间直到源极/漏极区域225形成接触开口236-1之后的横截面示意性侧视图。可以使用已知的蚀刻技术和蚀刻化学物质来形成开口236-1,以选择性地对覆盖层232和侧壁间隔物234的绝缘材料蚀刻PMD层236的材料。
接下来,图14是图13的半导体器件在半导体器件的表面上沉积保形衬垫层240A之后的横截面示意性侧视图。保形衬垫层240A可以包括诸如TaN等的材料,其用作用于填充开口236-1并形成MOL器件触点的金属材料的阻挡扩散层和/或粘合层。接下来,图15是图14的半导体器件在沉积一层金属材料以用导电材料245填充金属栅极结构230-1、230-2、230-3之间的接触开口236-1并将半导体器件的表面平坦化到栅极覆盖层232以去除覆盖层衬垫和导电材料,从而形成MOL器件触点240/245的横截面示意性侧视图。导电材料245可以包括铜、钨、钴、铝或其他适合用于形成到源/漏区和栅电极的垂直MOL器件触点的导电材料。
尽管未在图15中具体示出,MOL栅极触点可以在穿过PMD层236和覆盖层232向下到达金属栅极结构230-1、230-2和230-3的上表面的形成的开口中形成。应当理解,金属栅极结构230-1、230-2、230-3在Y-Y方向上延伸(如图11中所示的基于笛卡尔坐标系,在图纸平面内外),因此,如本领域普通技术人员所理解的,MOL栅极触点可以形成在PMD层236中,与金属栅极结构230-1、230-2、230-3的延伸端部对齐。
在形成MOL器件触点之后,下一个处理模块包括使用如图16-19中示意性示出的工艺流程在金属栅极结构和MOL器件触点之间形成气隙间隔物。该工艺的初始步骤包括蚀刻栅极覆盖层232和侧壁隔离物234。特别是,图16是图15的半导体器件在蚀刻掉栅极覆盖层232并使侧壁间隔物234向下凹陷到半导体鳍状结构220的上表面之后,从而在金属栅极结构230-1、230-2、230-3的侧壁和相邻的MOL设备触点240/245之间形成窄空间S的横截面侧视图。而图16的示例实施例示出了栅极覆盖层232被完全蚀刻掉,在替代实施例中,可以实施蚀刻工艺,使得蚀刻的栅极覆盖层232的薄层保留在金属栅极结构230-1、230-2、230-3的顶表面上。
接下来,图17是图16的半导体器件在沉积绝缘材料250A的保形层以在金属栅极结构230-1、230-2、230-3的暴露表面上和MOL器件触点240/245形成绝缘衬垫之后的横截面示意性侧视图。保形绝缘衬垫层250A是可选的保护特征,其出于与上述相同或相似的原因,可以在夹断沉积工艺之前形成,从而为金属栅极结构230-1、230-2、230-3的暴露表面和MOL设备触点240/245提供额外的保护。
此外,保形绝缘衬垫层250A可以由一个或多个坚固的超薄介电材料层形成,该介电材料具有所需的电气和机械特性,例如低泄漏、高电击穿、疏水等,并且可以承受后续半导体加工步骤造成的损坏。例如,保形绝缘衬垫层250A可以由例如SiN,SiCN,SiNO,SiCNO,SiC或其他具有如上所述的所需电气/机械特性的介电材料之类的介电材料形成。在一个实施例中,当间隔S(图16)在约4nm至约15nm的范围内时,形成的保形绝缘衬垫层250A的厚度在约1.0nm至约2nm的范围内,从而借助于相邻结构的侧壁上的衬垫层250A,将间隔S减小约2nm,至约4nm。
与上面讨论的BEOL实施例类似,保形绝缘衬垫层250A可以由使用循环沉积工艺沉积的相同或不同介电材料的多个保形层形成。例如,在一个实施例中,保形绝缘衬垫层250A可以由多个SiN的薄保形层形成,其顺序地沉积以形成具有总期望厚度的SiN衬垫层(例如,使用等离子体CVD或CVD工艺,硅烷和NH3循环沉积0.1nm-0.2nm厚的SiN层)。
制造工艺中的下一步骤包括在图17的半导体结构上使用夹断沉积工艺沉积介电材料以在金属栅极结构和MOL器件触点之间形成气隙隔离物。例如,图18是图17的半导体器件在使用非保形沉积工艺沉积一层介电材料260A以使得在金属栅极结构230-1、230-2、230-3和相邻的MOL设备触点240/245之间的狭窄空间中形成气隙隔离物262的夹紧区域形成之后的横截面示意性侧视图。如上所述,根据本发明的实施例,可以控制通过夹断沉积形成的气隙隔离物262的结构特征(例如,尺寸、形状、体积等),例如,基于(i)用于形成介电层260A的介电材料的类型,和/或(ii)用于执行夹断沉积的沉积工艺和相关的沉积参数(例如,气体流速、RF功率、压力、沉积速率等)。
例如,在本发明的一个实施例中,介电材料层260A通过低k电介质材料(例如,k在约2.0至约5.0的范围内)的PECVD沉积形成。这种低k介电材料包括但不限于SiCOH、多孔p-SiCOH、SiCN、SiNO、富碳SiCNH、p-SiCNH、SiN、SiC等。SiCOH介电材料具有介电常数k=2.7,多孔SiCOH材料的介电常数约为2.3-2.4。在本发明的一个示例实施例中,通过使用具有以下沉积参数的工业平行板单晶片300mm CVD反应器的等离子体CVD沉积工艺沉积SiN电介质膜来实现夹断沉积工艺:气体[硅烷(100-500sccm)和氨(200-1000sccm)];射频功率[200-600瓦];压力[1-8托];和沉积速率[0.5-8nm/sec]。
图19是图18的半导体器件在将半导体器件的表面平面化到MOL器件触点并沉积作为BEOL结构的第一互连级别的一部分的ILD层270之后的横截面示意性侧视图。图18的半导体结构可以使用标准CMP工艺平坦化,其中执行CMP工艺以去除覆盖层电介质材料260A和设置在MOL器件触点顶部上的绝缘衬垫层250A的部分,从而得到图19所示的结构。如图19所示,夹断沉积的电介质材料260A的剩余部分在金属栅极结构230-1、230-2、230-3和单独的绝缘衬垫250上形成单独的电介质覆盖结构260。尽管图11和19没有特别示出,在形成ILD层270之前,可以在平坦化的FEOL/MOL表面上形成另外的覆盖层,以使MOL器件触点的导电材料245与ILD层270的介电材料绝缘。
已经基于图11中示意性示出的半导体结构制造了实验测试结构,其中保形绝缘衬垫250由厚度为1nm、1.5nm、2nm和3nm的环状SiN膜形成,并且其中使用PECVD SiCN填充和具有k=2.7和2.4的PECVD ULK膜执行夹断沉积。实验结果表明,可以获得大体积气隙隔离物(图11中示意性地示出的气隙隔离物262),其在金属栅极结构上方延伸。此外,实验结果已经证明,通过改变沉积工艺参数或用于夹断沉积的材料,可以针对不同应用优化气隙隔离物的尺寸、形状、体积等。
应当理解,本文所讨论的用于制造FEOL/MOL或BEOL层中的气隙间隔物的方法可以结合在用于制造具有各种模拟和数字电路或混合信号电路的半导体器件和集成电路的半导体处理流程中。特别地,集成电路带(dies)可以用各种器件制造,例如场效应晶体管、双极晶体管、金属氧化物半导体晶体管、二极管、电容器、电感器等。根据本发明的集成电路可以用于应用程序、硬件和/或电子系统。用于实现本发明的合适硬件和系统可以包括但不限于个人计算机、通信网络、电子商务系统、便携式通信设备(例如,蜂窝电话)、固态媒体存储设备、功能电路等。包含这种集成电路的系统和硬件被认为是这里描述的实施例的一部分。在给出本文提供的本发明的教导的情况下,本领域普通技术人员将能够想到本发明的技术的其他实现和应用。
尽管这里已经参考附图描述了示例性实施例,但是应该理解,本发明不限于那些精确的实施例,并且在不脱离所附权利要求的范围的情况下,本领域技术人员可以在其中进行各种其他改变和修改。
Claims (14)
1.一种用于制造半导体器件的方法,包括:
在基板上形成第一金属结构和第二金属结构,其中所述第一金属结构和所述第二金属结构彼此相邻设置,具有设置在所述第一金属结构和所述第二金属结构之间的绝缘材料;
蚀刻所述绝缘材料以在所述第一金属结构和所述第二金属结构之间形成空间;以及
在所述第一金属结构和所述第二金属结构上沉积一层介电材料,以在所述第一金属结构和所述第二金属结构之间的所述空间中形成气隙;
其中所述第一金属结构包括晶体管的栅极结构,并且其中所述第二金属结构包括源极/漏极触点;
其中所述气隙的上部分被设置在所述第一金属结构的上表面上方和所述第二金属结构的上表面下方;并且
所述气隙的下部分被设置在所述第二金属结构的底表面下方。
2.根据权利要求1所述的方法,其中所述第一金属结构包括形成在后段线BEOL互连结构的层间电介质ILD层中的第一金属线,并且其中所述第二金属结构包括形成在所述BEOL互连结构的所述ILD层中第二金属线。
3.根据权利要求1所述的方法,其中在所述第一金属结构和所述第二金属结构上沉积介电材料层包括:
沉积非保形电介质材料层以形成介电盖层,该介电盖层具有夹断区域,该夹断区域与所述第一金属结构和所述第二金属结构之间的空间对齐;
其中,所述夹断区域形成在所述第一金属结构和所述第二金属结构的至少一个的上表面上方的所述介电盖层中。
4.根据权利要求3所述的方法,其中沉积所述非保形电介质材料层包括设置等离子体增强化学气相沉积工艺的沉积参数以获得约40%或更低的保形水平。
5.根据权利要求1所述的方法,其中所述介电材料包括介电常数为约5.0或更小的低k介电材料。
6.根据权利要求1所述的方法,其中所述介电材料包括SiCOH、SiCN、SiNO、富碳SiCNH、SiC、p-SiCN-H和SiN中的至少一种。
7.根据权利要求1所述的方法,还包括在将所述介电材料沉积在所述第一金属结构和所述第二金属结构上之前在所述第一金属结构和所述第二金属结构之间的所述空间内形成保形衬垫层,以在所述第一金属结构和所述第二金属结构之间的所述空间中形成气隙。
8. 一种半导体器件,包括:
第一金属结构和第二金属结构,在基板上彼此相邻设置,在所述第一金属结构和所述第二金属结构之间设置有空间;以及
在所述第一金属结构和所述第二金属结构上形成介电盖层,以在所述第一金属结构和所述第二金属结构之间的所述空间中形成气隙;
其中所述第一金属结构包括晶体管的栅极结构,并且其中所述第二金属结构包括源极/漏极触点;
其中所述气隙的上部分被设置在所述第一金属结构的上表面上方和所述第二金属结构的上表面下方;并且
所述气隙的下部分被设置在所述第二金属结构的底表面下方。
9.根据权利要求8所述的器件,其中所述第一金属结构包括形成在后段线BEOL互连结构的层间电介质ILD层中的第一金属线,并且其中所述第二金属结构包括形成在所述BEOL互连结构的所述ILD层中的第二金属线。
10.根据权利要求8所述的器件,其中所述介电盖层包括非保形介电材料层,所述非保形介电材料层包括夹断区域,所述夹断区域与所述第一金属结构和所述第二金属结构之间的所述空间对准;
其中,所述夹断区设置在所述第一金属结构和所述第二金属结构的至少一个的上表面上方的介电盖层中。
11.根据权利要求10所述的器件,其中所述非保形介电材料层的保形水平为约40%或更小。
12.根据权利要求8所述的器件,其中所述介电盖层包含介电常数为约5.0或更小的低k介电材料。
13.根据权利要求8所述的器件,其中所述介电盖层包括SiCOH、多孔p-SiCOH、SiCN、SiNO、富碳SiCNH、SiC、p-SiCNH和SiN中的至少一种。
14.根据权利要求8所述的器件,还包括形成在所述第一金属结构和所述第二金属结构之间的所述空间中的表面上的保形衬垫层。
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CN117423678A (zh) | 2024-01-19 |
US9892961B1 (en) | 2018-02-13 |
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US10115629B2 (en) | 2018-10-30 |
JP2019527933A (ja) | 2019-10-03 |
US20190267279A1 (en) | 2019-08-29 |
JP2022140451A (ja) | 2022-09-26 |
CN117558708A (zh) | 2024-02-13 |
US11658062B2 (en) | 2023-05-23 |
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US20240079266A1 (en) | 2024-03-07 |
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