CN113571517A - 多栅极器件及其形成方法 - Google Patents

多栅极器件及其形成方法 Download PDF

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Publication number
CN113571517A
CN113571517A CN202110789772.8A CN202110789772A CN113571517A CN 113571517 A CN113571517 A CN 113571517A CN 202110789772 A CN202110789772 A CN 202110789772A CN 113571517 A CN113571517 A CN 113571517A
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Prior art keywords
layer
gate
dielectric
gate structure
over
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CN202110789772.8A
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Inventor
游家权
潘冠廷
朱熙甯
江国诚
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/224,334 external-priority patent/US11961763B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113571517A publication Critical patent/CN113571517A/zh
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Abstract

一种器件和方法，第一栅极结构环绕设置在衬底上方的沟道层，第二栅极结构环绕设置在衬底上方的另一个沟道层，以及介电鳍结构形成在浅沟槽隔离部件上方以及第一栅极结构和第二栅极结构之间。至少一个金属化层形成在第一栅极结构、介电鳍状结构和第二栅极结构上，并从第一栅极结构连续延伸至第二栅极结构。本发明的实施例还涉及多栅极器件及其形成方法。

Description

多栅极器件及其形成方法
技术领域
本发明的实施例涉及多栅极器件及其形成方法。
背景技术
电子行业对更越来越快的电子器件的需求越来越多，同时能够支持更多越来越复杂和复杂的功能。为满足这些需求，集成电路(IC)行业存在持续趋势，用于制造低成本、高性能和低功耗IC。到目前为止，通过减少IC尺寸(例如，最小IC部件尺寸)，大部分地实现了这些目标，从而提高了生产效率并降低了相关成本。然而，这种缩放也增加了IC制造过程的复杂性。因此，实现IC器件的持续进步及其性能需要IC制造过程和技术的类似进步。
最近，已经引入了多栅极器件以改善栅极控制。已经观察到多栅极器件增加栅极沟道耦合，减少关闭状态电流和/或减少短沟道效应(SCES)。一种这样的多栅极器件是全环栅(GAA)器件，GAA器件包括可以在沟道区周围围绕沟道区延伸的栅极结构，以便在至少两侧提供对沟道区的存取。GAA器件启用IC技术的积极缩放、维护栅极控制和缓解SCE，同时无缝地与传统IC制造工艺集成。然而，随着GAA器件继续缩放，非自对准栅极切割技术通常被实现为将不同GAA器件的栅极彼此隔离(诸如将来自第二GAA晶体管的第二栅极与第一GAA晶体管的第一栅极隔离)正在阻碍高级IC技术节点所需的IC功能密集封装。因此，尽管现有的GAA器件和制造方法通常适用于其预期目的，但它们没有在所有方面都完全令人满意。
发明内容
根据本发明的一个方面，提供了一种器件，包括：衬底；第一栅极结构，包裹设置在衬底上的沟道层周围；第二栅极结构，包裹设置在衬底上的另一沟道层周围；介电鳍结构，形成在浅沟槽隔离(STI)部件上方，其中，介电鳍结构在第一栅极结构和第二栅极结构之间；至少一个金属化层，在第一栅极结构、介电鳍结构和第二栅结构上，并且从第一栅极结构连续地延伸到第二栅极结构。
根据本发明的另一个方面，提供了一种器件，包括：
第一沟道层，设置在衬底上方的第一源极/漏极部件之间；
第一金属栅极，围绕第一沟道层；
第二沟道层，设置在衬底上方的第二源极/漏极部件之间；
第二金属栅极，围绕第二沟道层；
介电鳍，设置在第一金属栅极和第二金属栅极之间并且分离第一金属栅极和第二金属栅极；
导电层的第一部分，在第一金属栅极上方；
导电层的第二部分，在第二金属栅极上方；以及
隔离层，在导电层的第一部分和第二部分之间并且在介电鳍上方，其中，导电层的第一部分或导电层的第二部分中的至少一个包括邻接隔离层的圆形终端。
根据本发明的又一个方面，提供了一种方法，包括
在衬底上方形成第一全环栅器件的第一栅极结构、第一源极结构和第一漏极结构；
在衬底上方形成第二全环栅器件的第二栅极结构、第二源极结构和第二漏极结构，其中，介电鳍设置在第一栅极结构和第二栅极结构之间；
在第一栅极结构、第二栅极结构和介电鳍上方沉积伪层；
图案化伪层以在介电鳍上方形成在伪层内的沟槽；
用介电材料填充沟槽以形成介电部件；
在填充沟槽之后去除图案化的伪层；以及
沉积具有第一栅极结构上方的第一部分和第二栅极结构的第二部分的至少一个导电层，其中，介电部件插入在第一部分和第二部分之间。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例图案化并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据本公开的各个方面的制造多栅极器件的方法的流程图。
图2、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16、图17、图18、图19、图20A、图21A、图22A、图23A、图24A、图25A、图26A、图27A和图28A是根据本公开的各个方面的各个制造阶段(例如与图1中的方法相关联的那些制造阶段)的多栅极器件(部分或全部)的局部透视图。
图20B、图21B、图22B、图23B、图23B、图24B、图25B、图26B、图27B和图28B是根据本公开的各个方面的各个制造阶段(例如与图1中的方法相关联的那些制造阶段)的多栅极器件(部分或全部)的局部截面图。
图29A和图29B是根据本公开的各个方面可以制造的第二多栅极器件(部分或全部)的另一实施例的局部透视图和截面图。
图30A和图30B是根据本公开的各个方面可以制造的第三多栅极器件(部分或全部)的另一实施例的局部透视图和截面图。
图31A和图31B是根据本公开的各个方面可以制造的第四多栅极器件(部分或全部)的另一实施例的局部透视图和截面图。
图32是根据本公开的一个或多个方面的多栅极器件的金属化的详细视图的局部截面图。
具体实施方式
本公开一般涉及集成电路器件，更具体地，涉及用于多栅极器件的金属栅极切割技术。
以下公开内容提供了许多不同的实施例或示例，用于实现本发明的不同特征。下面描述组件和布置的具体示例以简化本公开。当然，这些只是例子，而不是限制性的。例如，在遵循的描述中形成第一部件或第二部件的形成可以包括其中第一和第二部件在直接接触中形成的实施例，并且还可以包括在第一部件和第二部件之间形成附加特征的实施例，使得第一和第二部件可能不直接接触。另外，空间相对术语，例如，“上”、“下”、“水平”、“垂直”、“之上”、“之下”、“下方”、“下面”、“向上”、“向下”、“顶部”、“底部”等以及其衍生物(例如，“水平地”、“向下地”，“向上地”等)用于易于本公开的一个部件与另一个部件的部件关系。空间相对术语旨在覆盖包括部件的器件的不同取向。此外，当数字或一系列数量描述为“约”、“近似”等时，该术语旨在包括在考虑在制造过程中固有地出现的变化的合理范围内的数字，如本领域普通技术人员所理解的。例如，数字的数量或范围包括基于与制造具有与数量相关联的部件已知的制造公差，包括所描述的数量的合理范围包括所描述的数量，例如在+/-10％内。例如，厚度为约5nm的材料层可以包括从4.5nm至5.5nm的尺寸范围，其中已知与沉积材料层相关的制造公差是本领域普通技术人员的+/10％。此外，本公开可以在各种示例中重复参考数字和/或字母。这种重复是为了简单和清楚起见，并且本身不包括所讨论的各种实施例和/或配置之间的关系。
在形成集成电路时，设计可以提供某些栅极结构以彼此隔离。为了提供这种隔离，工艺有时被称为栅极切割技术，用于提供第一沟道区上的第一栅极结构与第二沟道区上的第二栅极结构隔离。例如，可以形成栅极隔离部件或分离部件(例如由绝缘层组成)，以提供第一栅极和第二栅极之间的电隔离以及与所述栅极的相应电接触件，第一栅极可以设置在第一GAA器件的第一沟道层(即，第一有源器件区)上方，第二栅极可以设置在第二GAA器件(即，第二有源器件区)的第二沟道层上。然而，在器件的其他部分中，工艺包括提供电连接到另外栅极结构(诸如第一栅极结构)的第三栅极结构。
应认识到，提供了可以在不影响或损坏到栅极本身之间的相邻栅极之间形成的工艺(诸如蚀刻工艺)。例如，在形成隔离结构中栅极的不期望的蚀刻或损失可以导致栅极高度的不期望的降低，这可以是对器件的预期可靠性和/或性能的不利影响。这里讨论的方法和器件提供了在连接其他栅极结构的同时形成栅极结构之间的隔离，在一些实施方式中，避免从栅极结构损失材料。避免栅极结构材料的损失允许在器件设计中实现较低的栅极高度，这可以提供改进器件的AC性能。
还认识到，在一些实施方式中，本公开提供了通过自对准工艺提供栅极切割和某些栅极连接的器件和方法。因此，本公开提供了用于多栅极器件的技术，与非自对准栅极切割技术(这需要附加的间隔来解释某些工艺的未对准)的有源器件区之间所需的间距相比，这允许有源器件区之间的较小间隔。因此，在一些实施方式中，所提出的自对准栅极切割技术允许减少尺寸(诸如金属栅极尺寸)，从而增加图案密度。本文在以下页面中描述了用于多栅极器件器件和产生的多栅极器件器件的特定实施例的细节。类似地，本文在以下页面中描述了提供用于多栅极器件之间的栅极结构和得到的多栅极器件之间的栅极结构的自对准栅极电连接的某些实施例的细节。
现在参考图1，示出了用于制造半导体器件200的方法100，在图2-图19、图20A、图21A、图22A、图23A、图24A、图25A、图26A、图27A和图28A中示出半导体器件200的局部截面图，并且在图20B、图21B、图22B、图23B、图24B、图25B、图26B、图27B、图28B和图32示出半导体器件200的局部截面图。除了图29A/图29B、图30A/图30B、图31A/图31B，器件200’、200”和200”’分别在上述参考图的方面中示出，并且可以由方法100的方面形成类似示例性器件。注意，器件200的本示例包括GAA器件，然而，本公开的方面也可能适用于其他器件类型，例如鳍式场效应晶体管(FinFET)。
方法100仅是示例性的，并不旨在将本公开限制于其中在其中明确示出的内容。在方法100之前和之后可以提供附加步骤，并且可以在方法的另外的实施例中替换、消除或移动一些步骤。由于简单性的原因，这里没有详细描述所有步骤。除了在本公开的图中明确示出的内容，半导体器件200可以包括在整个本公开中的附加晶体管、双极结晶体管、电阻器、电容器、电容器、二极管、熔断器等。除了示例性器件200、200’、200”和200”’的具体说明的差异之外，一个器件的描述适用于其他示例性器件。
方法100开始于框102，其中接收到具有形成在其上的多个鳍结构的衬底。参考图2的示例，提供衬底202。在一个实施例中，衬底202可以是硅(Si)衬底。在一些其他实施例中，衬底202可包括其他半导体，例如锗(Ge)，硅锗(SiGe)或III-V半导体材料。示例III-V半导体材料可包括砷化镓(GaAs)、磷化铟(InP)、磷化镓(GaP)、氮化镓(GaN)、砷化镓磷化物(GaAsP)、铝铟砷(AlInAs)、铝镓砷(AlGaAs)、镓铟磷化铟(GaInP)和铟镓砷(InGaAs)。衬底202还可包括绝缘层，诸如氧化硅层，以具有绝缘体上硅(SOI)结构或绝缘体上锗(GOI)结构。在一些实施例中，用于形成不同类型的器件，衬底202可以包括一个或多个阱区，例如掺杂有n型掺杂剂(即，磷(p)或砷(As))的n型阱区或掺杂p型掺杂剂(即，硼(B))的p型阱区。可以进行离子注入工艺，扩散过程和/或其他合适的掺杂过程以形成各种掺杂区。
仍然参考图2，外延层的堆叠204可以设置在衬底202上。堆叠204可以包括由多个牺牲层206交替的多个沟道层208。沟道层208和牺牲层206可以具有不同的半导体成分。牺牲层206和沟道层208交替地、一个接一个地沉积，以形成堆叠204。在一些实施方式中，沟道层208由硅(Si)形成，并且牺牲层206由硅锗形成(SiGe)。在一些实施方式中，牺牲层206中的附加锗含量允许牺牲层206的选择性去除或凹陷，而没有对沟道层208的大量损坏，如下所述。在一些实施例中，可以使用外延工艺以沉积材料来形成包括牺牲层206和沟道层208的堆叠204。示例性技术包括但不限于CVD沉积技术(例如，气相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延(MBE)和/或其他合适的方法。应注意，如图2所示，牺牲层206的三(3)层和沟道层208的三(3)层交替地且垂直地布置。然而，这仅用于说明目的，而不是用于限制本公开中具体叙述的内容。层的数量取决于半导体器件200的所需沟道构件的数量。在一些实施例中，沟道层208的数量在2和10之间。用于图案化目的，可以在堆叠204上设置硬掩模层210。硬掩模层210可以是单层或多层。在一个实施方式中，硬掩模层210包括氧化硅层210A和氮化硅层210B。
方法100的框102可以包括形成延伸在衬底上方的多个鳍结构。每个鳍结构限定衬底上的有源区。参考图2的示例，鳍结构212由外延的堆叠204形成。而两(2)个或四(4)个鳍结构示出在示例性图中，这仅用于说明目的，而不是限制在超出本公开列出的内容之外。鳍结构212可以使用包括光刻和蚀刻工艺的合适方法制造。光刻工艺可包括形成覆盖衬底202的光刻胶层，曝光光刻胶层成图案，执行暴光后烘烤工艺，以及显影光刻胶层以形成包括光刻胶层的掩模元件。在一些实施例中，掩模元件还包括上面讨论的硬掩模层210。在一些实施例中，可以使用电子束(E-束)光刻工艺来执行以形成掩模元件的光刻胶层。鳍结构212可以使用包括双重图案化或多重图案化工艺的合适的工艺来图案化。通常，双重图案化或多重图案化处理结合了光刻和自对准工艺，允许产生的图案具有例如使用单个直接光刻工艺可获得的更小节距。例如，在一个实施例中，在衬底上形成材料层并使用光刻工艺图案化。使用自对准工艺沿着图案化材料层形成间隔件。然后除去材料层并保留间隔件，然后可以使用剩余的间隔件或心轴来图案化鳍结构。因此，示例工艺包括图案化光刻(DPL)工艺(例如，光刻-蚀刻-光刻-蚀刻(LELE)工艺、自对准双重图案化(SADP)工艺、介电间隔件(SID)SADP工艺、其他双重图案化工艺或其组合)、三重图案化工艺(例如，光刻-蚀刻-光刻-蚀刻-蚀刻-蚀刻(LELELE)工艺、自对准三重图案化(SATP)工艺、其他三重图案化工艺或其组合)，其他多重图案化工艺(例如，自对准的四重图案化(SAQP)工艺)、或其组合。
然后可以使用上述掩模元件来保护堆叠204和/或衬底202的区域，同时蚀刻鳍结构212。可以使用干蚀刻(例如，化学氧化物去除)、湿蚀刻、反应离子蚀刻(RIE)和/或其他合适的方法来蚀刻沟槽214。还可以使用在衬底202上形成鳍结构212的多种其他实施例。鳍结构212在衬底202上方垂直(Z方向)延伸，并且沿着沿衬底202的Y方向纵长，并且在X方向上与相邻鳍结构212间隔开。每个鳍结构212包括由衬底部分202'形成的基部和由堆叠204的材料形成的覆盖部。
在一些实施例中，方法100的框102包括在蚀刻的鳍结构上形成层或多层。在一些实施方案中，在衬底和鳍结构上形成氧化物衬垫层(例如，氧化硅)。在一些实施例中，在衬底和鳍结构上形成硅衬垫层。参考图3，在一些实施例中，在鳍结构212上形成氧化物衬垫层216和硅衬垫层218。在一些实施例中，氧化物衬垫层216和/或硅衬垫层218具有基本恒定的厚度。在一些实施例中，通过化学气相沉积(CVD)、物理气相沉积(PVD)、高密度等离子体CVD(HDPCVD)、金属有机CVD(MOCVD)、远程等离子体CVD(RPCVD)、等离子体增强CVD(PECVD)、低压CVD(LPCVD)、原子层CVD(ALCVD)、大气压CVD(APCVD)、亚大气压沉积(SAVCD)、其他合适的方法或其组合形成硅衬垫层218和/或氧化物衬垫层216。在一些实施例中，硅衬垫层218包括n型掺杂剂和/或p型掺杂剂。
然后，方法100进行到框104，形成插入在多个鳍结构中的隔离部件。隔离部件可以称为浅沟槽隔离(STI)部件。参考图4的示例，在鳍结构212之间和沟槽214内形成隔离层402。在实施例中，隔离材料是多层，例如，包括衬垫层和诸如氧化物材料的上覆层。在一些实施方案中，通过可流动的CVD(FCVD)工艺沉积氧化物材料，可流动的CVD(FCVD)工艺例如包括在多栅极器件200上方沉积可流动的氧化物材料(例如，在液态状态)并通过退火工艺将可流动的氧化物材料转换成固体氧化物材料。可流动的氧化物材料可以流入沟槽214并共面为多栅极器件200的暴露表面，使得在一些实施方式中能够无空隙地填充沟槽214。
在一些实施例中，形成隔离层402的绝缘材料可包括SiO2、氮化硅、氮氧化硅、氟掺杂硅酸盐玻璃(FSG)、低k介电、其组合和/或本领域已知的其他合适的材料。在各种示例中，介电材料可以通过CVD工艺、亚大气压化学气相沉积CVD(SACVD)工艺、可流动的CVD工艺、ALD工艺、PVD工艺或其他合适方法沉积。
沉积工艺可以覆盖沟槽214(未示出)，使得用于隔离部件402的材料的厚度大于鳍212的高度。在沉积工艺之后，在材料上进行平坦化工艺，例如化学机械抛光(CMP)工艺，从而减小厚度。在一些实施例中，硅衬垫层218用作蚀刻停止层，并且暴露鳍结构212上的硅衬垫层218而停止平坦化。平坦化形成如图4中所示的表面。
转到如图5所示，然后可以凹陷绝缘材料，使得鳍结构212从由隔离层402形成的隔离部件之间延伸(突出)。蚀刻以凹陷隔离材料的蚀刻工艺被配置为相对于硅衬垫层218选择性地去除材料(例如，氧化物)。例如，选择蚀刻剂，用于以比硅(即，硅衬垫层218)更高的速率蚀刻蚀刻氧化硅(即，隔离部件402)的蚀刻工艺。因此，隔离部件402填充沟槽214的在鳍结构212之间的部分。在一些实施例中，场氧化物、LOCOS部件和/或其他合适的隔离部件可以附加地或替代地在衬底上和/或内实现。
然后，方法100前进到框106，其中在鳍结构上形成盖层106。盖层可以是牺牲层。可以在每个鳍结构上形成盖层。参考图6的示例，在每个鳍元件212上形成盖层602。在一些实施例中，盖层602可以具有与牺牲层206类似的成分。在一个实施例中，盖层602由硅锗(SiGe)形成。在一些实施方案中，盖层602和牺牲层206包括允许在随后工艺中通过单个蚀刻剂释放沟道层208期间选择性去除牺牲层206和盖层602的组合物。在实施例中，盖层602可以使用气相外延(VPE)、分子束外延(MBE)外延生长，或者通过诸如CVD工艺，亚大气压化学气相沉积CVD(SACVD)工艺、可流动的CVD工艺、ALD工艺、PVD工艺或其他合适工艺的沉积方法形成。在沉积之后，在一些实施例中，框106处的操作可以包括回蚀刻，以从隔离部件402中除去盖层602的材料，例如共形地沉积。在一些实现中，可以省略框106。
然后，方法100进入到框108，其中在鳍结构的上部之间形成隔离结构(也被称为介电鳍)，从而分离相邻的有源区。隔离结构可包括填充鳍结构之间的间隙的多层结构，并设置在框104的STI部件上方。图7-图10示出了在有源区之间形成多层隔离结构或介电鳍的实施例。首先参考图7的示例，在器件200上沉积第一介电层702。在实施例中，第一介电层是高k介电。在实施例中，第一介电层702可以是氮化硅碳氮化硅(SiCN)、氧碳氮(SiOCN)或其组合。在一些实施例中，介电层702包括HfO2、HfSiO、HfSiO4、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx、ZrO、ZrO2、ZrSiO2、AlO、AlSiO、Al2O3、TiO、TiO2、LaO、LaSiO、Ta2O3、Ta2O5、Y2O3、SrTiO3、BaZrO、BaTiO3、(Ba,Sr)TiO3、HfO2-Al2O3、其他合适的高k介电材料、或其组合。参考图8的示例，在第一层之后，然后可以在第一介电层702上形成氧化物层802。在一些实施例中，氧化物层802可以通过可流动的CVD工艺、HARP和/或提供合适的间隙填充性的方法沉积。在一些实施方式中，沟槽214可以用氧化物层覆盖，并且在沉积氧化物层802之后，可以执行CMP工艺，提供如图8所示的基本平面的顶表面。在一个实施例中，盖层602为平坦化工艺提供蚀刻停止。
参考图9，层702和/或802被回蚀刻，形成开口902。在实施例中，去除氧化物层802以形成开口902，其具有由第一介电层702限定的侧壁，并且由沟槽214限定。形成开口902的蚀刻工艺可以是干蚀刻工艺、湿蚀刻工艺或其组合。
如图10中所示，介电材料1002形成在开口902内。可以沉积介电材料1002以溢出开口902，随后通过平坦化工艺去除过量的材料。在一个实施例中，介电材料1002是高k介电。在一些实施例中，介电材料1002是与第一介电层702基本相同的成分。在一个实施例中，介电材料1002可以是氮化硅碳氮化硅(SiCN)、氧碳腈(SiOCN)或其组合。在一些实施例中，介电层702包括HfO2、HfSiO、HfSiO4、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx、ZrO、ZrO2、ZrSiO2、AlO、AlSiO、Al2O3、TiO、TiO2、LaO、LaSiO、Ta2O3、Ta2O5、Y2O3、SrTiO3、BaZrO、BaTiO3、(Ba,Sr)TiO3、HfO2-Al2O3、其他合适的高k介电材料、或其组合。介电材料1002可以通过合适的方法沉积，诸如亚大气压化学气相沉积CVD(SACVD)工艺、可流动CVD工艺、其他CVD工艺、ALD工艺、PVD工艺或其他合适的方法。在一些实施方式中，在沉积之后，进行平坦化工艺，从而减薄沉积的介电材料1002以提供平面顶表面。在一些实施方式中，平坦化工艺可以停止在硬掩模210处。
上面讨论的介电层702、802和1002一起形成称为介电鳍1004的隔离结构。介电鳍1004在相邻的有源区之间、鳍结构212、盖层602部分之间延伸。介电鳍1004因此被称为类鳍结构212，介电鳍1004沿衬底202上方垂直(Z方向)(特别是在隔离结构402上方)上方，并且从衬底202沿Y方向纵长地延伸，并且沿X方向与相邻介电鳍1004间隔开。
在一些实施例中，在形成隔离结构或介电鳍1004之后并且在形成伪栅极之前，蚀刻硬掩模和相邻的盖层以形成开口1102，如图11所示。在一些实施例中，蚀刻暴露在沟道区的上表面，如下所述，栅极结构可以形成在沟道区上。
然后，方法100进入到框110，其中在鳍结构上方形成伪栅极。参考图12，在鳍212和介电鳍1004的部分上形成伪栅极结构1202。伪栅极结构1202填充开口1102的部分，并且可以在介电鳍1004上方延伸。伪栅极结构1202在与鳍结构212的长度方向不同的方向(例如垂直于)上纵向延伸。例如，伪栅极结构1202沿X方向彼此基本平行地延伸，具有在X方向上限定的长度，在Y方向上限定的宽度，和在Z方向上定义的高度。伪栅极结构1202设置在多栅极器件200的沟道区上方，以及通过开口1102的剩余部分暴露的多栅极器件200的源极/漏极区(S/D)。每个伪栅极结构1202包括伪栅极介电1204、伪栅电极1206和硬掩模1208(例如包括第一掩模层1208a和第二掩模层1208b，在一些实施方式中包括焊盘氧化物1208a和焊盘氮化物1208b)。伪栅极介电1204包括介电材料，例如氧化硅、高k介电材料、其他合适的介电材料、或其组合。在一些实施例中，伪栅极介电1204包括界面层(包括例如氧化硅)和设置在界面层上的高k介电层。伪栅电极1206包括合适的伪栅极材料，例如多晶硅。在一些实施例中，伪栅极结构1202包括许多其他层，例如覆盖层、界面层、扩散层、阻挡层或其组合。伪栅极结构1202由沉积工艺、光刻工艺、蚀刻工艺其他合适的工艺或其组合形成。例如，执行第一沉积工艺以在多栅极器件200上形成伪栅极介电层，执行第二沉积工艺以在伪栅极介电层上形成伪栅电极层，并且执行第三沉积工艺以形成在伪栅电极层上的硬掩模层。在一个实施方式中，硬掩模层1208包括氧化硅层1208a和氮化硅层1208b。沉积方法包括CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、电镀、其它合适的方法或其组合。然后执行光刻图案化和蚀刻工艺以图案化硬掩模层、伪栅电极层和伪栅极介电层以形成伪栅极结构1202，伪栅极结构1202包括伪栅极介电1204、伪栅电极1206和硬掩模1208，如图12所示。光刻图案化工艺包括光刻胶涂层(例如，旋涂涂层)、软烘烤、掩模对准、曝光、曝光后烘烤、显影光刻胶、冲洗、干燥(例如，硬烘干)、其他合适的光刻工艺或其组合。蚀刻工艺包括干蚀刻工艺、湿蚀刻工艺、其他蚀刻方法或其组合。
转到如图13所示，伪栅极结构1202还可包括沿着伪栅极堆叠1202的侧壁形成的栅极间隔件1302。栅极间隔件1302可以由合适的介电材料构成。介电材料可包括硅、氧、碳、氮、其他合适的材料或其组合(例如，氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅、氧化硅和/或氧化碳羰基族)。在一些实施例中，栅极间隔件1302包括多层结构，例如包括氮化硅的第一介电层和包括氧化硅的第二介电层。在一些实施例中，与伪栅极结构1202相邻地形成多于一组间隔件，诸如密封间隔件、偏移间隔件、牺牲间隔件、伪间隔件和/或主间隔件。
然后，方法100进入到框112，其中凹陷邻接鳍结构的源极/漏极区。在图13中，多栅极器件200的源极/漏极区中的鳍结构212的部分(即，不被栅极结构1202覆盖的鳍结构212的源极/漏极区)也至少部分地去除以形成源极/漏极凹陷或沟槽1304。在所描绘的实施例中，蚀刻工艺完全消除了多栅极器件200的源极/漏极区中的半导体层堆叠204，从而在源极/漏极区中暴露鳍部分202’。在实施例中，蚀刻工艺还完全从源极/漏极区中去除盖层602的部分。在所描绘的实施例中，每个源极/漏极凹槽1304具有由介电鳍1004的相应一个限定的侧壁和由相应的鳍部分202和相应的隔离部件402限定的底部。蚀刻工艺可包括干蚀刻工艺、湿蚀刻工艺、其他合适的蚀刻工艺或其组合。在一些实施例中，蚀刻工艺是多步蚀刻工艺。
参见图14和图15，在一些实施例中，框112还包括略微(横向)蚀刻的牺牲层206，以形成开口1402(例如，在包括栅极间隔件1302的栅极结构1202下方)。开口1402形成在沟道层208的悬挂的端部区域之间。内部间隔件1502可以形成在开口1402内。在一些实施例中，内部间隔件包括介电材料，包括硅、氧、碳、氮、其他合适的材料或其组合(例如，氧化硅、氮化硅、氮氧化硅、碳化硅和/或氧化硅氧化硅)。在一些实施例中，内部间隔件1502包括低k介电材料，例如本文所述的那些。
然后，方法100进入到框114，其中在鳍结构的凹陷的源极/漏极区中生长源极/漏极部件。参考图16，外延源极/漏极部件1602(表示为1602A和1602B)形成在源极/漏极凹槽1304中。在一些实施方式中，从包括衬底202的鳍部分202的暴露表面的晶种区外延生长半导体材料，形成源极/漏极凹槽1304中的外延源极/漏极部件1602A(其与例如n型晶体管的晶体管的第一类型相对应)和源极/漏极凹槽1304中的外延源极/漏极部件1602B(其与例如p型晶体管的晶体管的第二类型相对应)。在一些实施方式中，形成源极/漏极部件1602的外延工艺可以使用CVD沉积技术(例如，LPCVD、VPE和/或UHV-CVD)、分子束外延、其它合适的外延生长过程或其组合。外延工艺可以使用与晶种区的组成相互作用的气态和/或液体前体。外延源极/漏极部件1602分别掺杂有n型掺杂剂和/或p型掺杂剂。在一些实施方案中，对于n型晶体管，外延源极/漏极部件1602A包括硅，其可以掺杂碳、磷、砷、其他n型掺杂剂或其组合(例如，形成Si：C外延源极/漏极部件，Si：P外延源极/漏极部件，或Si：C：P外延源极/漏极部件)。在一些实施方案中，对于p型晶体管，外延源极/漏极部件1602B包括硅锗或锗，其可以掺杂硼、其他p型掺杂剂或其组合(例如，形成Si：Ge：B外延源极/漏极部件)。在一些实施例中，外延源极/漏极部件1602包括一个以上的外延半导体层，其中外延半导体层可包括相同或不同的材料和/或掺杂剂浓度。在一些实施方案中，通过向外延工艺的源材料(即原位)添加杂质，在沉积期间掺杂外延源极/漏极部件1602。在一些实施方案中，通过在生长工艺之后的离子注入工艺外延源极/漏极部件1602被掺杂。在一些实施例中，当形成不同器件类型的外延源极/漏极源极/漏极部件时，在与外延源极/漏极部件1602B分离的工艺序列中形成外延源极/漏极部件1602A。
然后，方法100进入到框116，其中在衬底上形成绝缘材料，包括在源极/漏极部件上方。形成的绝缘材料可以是形成到源极/漏极部件的后续接触元件的材料。绝缘材料提供源极/漏极接触以及例如相邻的栅极结构之间的隔离。绝缘材料可以称为接触蚀刻停止层(CESL)和层间介电(ILD)层。CESL可以用作形成接触元件的蚀刻停止，以形成源极/漏极部件(未示出)。参考图17的示例，进行沉积工艺(例如CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、FCVD、HARP、HDP、其它合适的方法或其组合)形成在器件200上的介电层1702和1704。在一个实施例中，介电层1704是层间介电(ILD)层，介电层1702是底部接触件蚀刻停止层(B-CESL)。介电层1704可包括介电材料，包括例如氧化硅、碳掺杂氧化硅、氮化硅、氮氧化硅、TEOS形成的氧化物、PSG、BSG、BPSG、FSG、黑色金刚石(Santa Clara应用材料,加利福尼亚)、干凝胶、气凝胶、无定形氟化碳、聚丙烯、基于BCB的介电材料、SiLK(陶氏化学，密歇根)、聚酰亚胺、其他合适的介电材料、或其组合。在一些实施例中，介电层1704包括具有小于二氧化硅的介电常数(例如，K<3.9)的介电常数的介电材料。在一些实施例中，介电层1704包括介电常数小于约2.5(即，极低k(ELK)介电材料)的介电材料，例如二氧化硅(SiO2)(例如，多孔硅二氧化硅)、碳化硅(SiC)和/或碳掺杂氧化物(例如，基于SiCOH的材料(例如具有Si-CH3键))，每个被调谐/配置为表现出小于约介电常数2.5。介电层1702包括与介电层1704不同的材料。介电层1702的示例性成分包括但不限于氮化硅或氮氧化硅。
在一些实施方式中，在沉积之后执行CMP工艺和/或其他平坦化工艺，直到曝光伪栅极结构1202的顶部部分。在一些实施例中，平坦化工艺去除伪栅极结构1202的硬掩模层1208以暴露下面的伪栅电极1206(例如，多晶硅)。
然后，方法100进入到框118，其中形成用于金属栅极结构的开口，包括通过去除伪栅极结构和释放鳍结构的沟道区内的沟道层。在框118的一个实施例中，去除框110的伪栅极结构。参考图18的示例，伪栅极结构1202被去除以形成图18所示的开口1802。应注意，如图18所示，与以下附图相同，提供了切割沟道区的透视图，从源极/漏极部件1602偏移，例如图17，这是不可见的。在一些实施例中，诸如所示，在去除栅电极1206时，蚀刻工艺不会去除伪栅极介电1204。在一些实施例中，蚀刻工艺或后续蚀刻工艺部分或完全去除伪栅极介电1204。蚀刻工艺(ES)可以是干蚀刻工艺、湿蚀刻工艺或其组合。
参考图19的示例，沟道释放工艺可以导致在沟道区中去除牺牲层206，从而在沟道区中形成悬挂的半导体层208，其通过间隙和/或鳍部分202彼此分离。释放沟道层208的蚀刻工艺是干蚀刻工艺、湿蚀刻工艺或其组合。沟道释放工艺还可以包括在沟道区中去除盖层602。沟道释放工艺可以包括选择性地蚀刻到盖层602和/或牺牲层206的成分(例如，硅锗)，同时为沟道层208提供至最小蚀刻。沟道层的释放、伪栅极结构去除、以及盖层602去除在器件200的沟道区中提供相应的开口1902，如图19所示。
在一些实施方式中，介质鳍1004未在不同类型的器件(例如，n型或p型)的相邻沟道区之间被去除，因此继续提供不同类型的相邻器件之间的隔离。在一些实施例中，介电鳍1004也没有在相同的器件类型(例如，n型或p型)的相邻沟道区之间除去，并且可以提供用于这些器件的栅极结构的任何互连，而不是由栅电极提供结构本身提供，但是通过如下所述的介电鳍1004上方形成的金属化。
然后，方法100进入到框120，其中金属栅极结构形成在由框118提供的开口中。金属栅极结构可以是完成的器件200的功能栅极。参考图20A和图20B的示例，示出的是形成在由框118提供的开口1902中的金属栅极结构2002。金属栅极结构2002被配置为根据多栅极器件200的设计要求来实现期望的功能。金属栅极结构2002包括栅极介电2004(例如，高k栅极介电和/或诸如氧化硅或氮氧化硅的界面层)和栅电极2006(例如，功函数层和体导电层)。金属栅极结构2002可包括许多其他层，例如覆盖层、界面层、扩散层、阻挡层、硬掩模层或其组合。在一些实施例中，形成金属栅极结构2002包括在沟道区上沉积栅极介电层2004，其中栅极介电层部分地填充在沟道层208之间的间隙，在栅极介电层2004上沉积栅电极层2006，其中栅电极层填充沟道层208之间的剩余间隙。
栅极介电2004包括高k介电层，其包括高k介电材料，出于金属栅极结构2002的目的高k介电材料是指具有大于二氧化硅(k≈3.9)的介电常数的介电材料(k≈3.9)。例如，高k介电层包括HfO2、HfSiO、HfSiO4、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx、ZrO、ZrO2、ZrSiO2、AlO、AlSiO、Al2O3、TiO、TiO2、LaO、LaSiO、Ta2O3、Ta2O5、Y2O3、SrTiO3、BaZrO、BaTiO3(BTO)、(Ba,Sr)TiO3(BST)、Si3N4、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的金属栅极堆叠的高k介电材料或组合它。高k介电层通过本文所述的任何方法形成，例如ALD、CVD、PVD、氧化基沉积工艺、其它合适的过程或其组合。例如，ALD工艺沉积高k介电层。在一些实施例中，ALD工艺是保形沉积工艺，使得高k介电层的厚度在多栅极器件器件200的各种表面上基本均匀(共面)。在一些实施例中，栅极介电2004包括界面层，设置在高k介电层和沟道层208之间。界面层包括介电材料，例如SiO2、HfSiO、SiON、其他硅介电材料、其他合适的介电材料或其组合。界面层通过本文所述的任何方法形成，例如热氧化、化学氧化、ALD、CVD、其它合适的方法或其组合。例如，界面层通过化学氧化工艺形成，化学氧化工艺将沟道层208的暴露表面暴露于氢氟酸。在一些实施例中，界面层通过热氧化工艺形成，热氧化工艺将沟道层208的暴露表面暴露于氧气和/或空气环境。在一些实施例中，在形成高k介电层之后形成界面层。例如，在一些实施方案中，在形成高k介电层之后，可以在氧气和/或氮环境(例如，氧化亚氮)中来退火多栅极器件200。
在栅极介电2004上形成栅电极2006，填充栅极开口1902的剩余部分和包裹沟道层208，使得栅电极2006填充沟道层之间的剩余间隙。栅电极2006包括导电材料，例如多晶硅、铝、铜、钛、钽、钨、钼、钴、TaN、NiSi、CoSi、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN其他导电材料或其组合。在一些实施例中，栅电极2006包括功函数层和体导电层。功函数层是调谐的导电层，以具有所需的功函数(例如，n型功函数或p型功函数)，并且导电体层是形成在功函数层上的导电层。在一些实施方案中，功函数层包括n型功函数材料，例如Ti、银、锰、锆、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN其他合适的n型功函数材料或其组合。在一些实施方案中，功函数层包括p型功函数材料，例如Mo、Al、TiN、TaN、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其他合适的P型功函数材料或其组合。体(或填充)导电层包括合适的导电材料，例如Al、W、Ti、Ta、多晶硅、Cu、金属合金、其它合适的材料或其组合。栅电极2006由本文所述的任何方法形成，例如ALD、CVD、PVD、电镀、其它合适的工艺或其组合。在一种实施方式中，执行CMP工艺，使得栅极结构2002的顶表面基本上是平面的，在CMP工艺之后基本上与ILD层1704的顶表面齐平。
参考图21A和图21B的示例，栅极结构2006被回蚀刻，使得金属栅极结构2002的顶表面基本上与介电鳍1004的顶表面基本共面。这留下设置在金属栅极结构2600上方的开口2102。介电鳍1004在不同沟道区上的金属栅极结构2002之间延伸。例如，执行回蚀刻工艺以凹陷栅电极2006，直到介电鳍1004的顶表面不含栅电极2006材料。
在一些实施方式中，栅极结构2006从介电鳍1004的顶表面进一步凹陷，并且在凹陷栅极结构2006上形成附加层或多层。在一个实施例中，将晶种层设置在金属栅极结构和邻近的介电鳍上。晶种层可以是Ti、TiN、TaN、W、Ru和/或其组合。示例性厚度包括约1nm至2nm之间的厚度。在一些实施方式中，选择厚度以提供足够的厚度，以粘附到覆盖层和下面讨论的上覆金属化的所需电阻率。晶种层的沉积方法可包括CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、PEALD、电镀、无电镀、其它合适的沉积方法或其组合。图30A和图30B示出了形成在栅电极2006上方的晶种层2602并且具有邻接介电鳍1004的侧壁，示出了晶种层2602的凹陷栅极结构2006。虽然在一些实施方式中，如本文所讨论的，图30A和图30B的晶种层2602是在沉积伪层2202之间形成，但是在其它实施例中，图30A和图30B所示的晶种层2602在栅极分离部件之后形成。
在一些实施方式中，栅极结构进一步从介电鳍1004的顶表面凹陷，并且蚀刻停止层设置在金属栅极结构上并与介电鳍相邻。蚀刻停止层可以是金属氮化物和/或其他合适的组合物，其允许导电性。蚀刻停止层的沉积工艺可包括CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、PEALD、电镀、电镀、其它合适的沉积方法或其组合。如图31A和图31B所示，在介电鳍1004附近的栅极结构2002上提供蚀刻停止层3102的示例。蚀刻停止层3102可以在蚀刻沟槽2302时为栅极结构2002提供附加的保护，如下讨论。因此，蚀刻停止层3102可以具有选择以向伪层2202提供蚀刻选择性的成分。
在回蚀刻工艺和/或平坦化之后，相邻的栅电极2006可以不在第一沟道区(鳍212)到第二沟道区(相邻鳍212)之间延伸。换句话说，栅极结构2002的电导率在相邻的沟道区(例如，通过介电鳍1004)之间中断。因此，在一些实施例中，在方法100中，栅电极2006彼此电绝缘。金属栅极切割或分离工艺可以称为自对准，因为栅极隔离结构(这里，介电鳍1004)在相邻的金属栅极结构2002之间对准，而不必在形成金属栅极结构2002之后进行光刻工艺。自对准的介电鳍1004的放置在相邻有源区中的器件之间提供电隔离。
然后，方法100进入到框122，其中在栅极结构上形成伪材料层。在一个实施例中，伪材料层是硅。在其他实施方案中，伪材料包括SiO、SiN、SiC、SiCN、SiON、SiCN、SioCN、AlO、AlN、AlON、ZrO、ZrN、ZrAlO、HfO和/或其他合适的材料。伪材料可以是牺牲的，并且选择伪材料使得它具有合适的蚀刻选择性，例如，当形成例如框124中讨论的沟槽时。在一个实施例中，伪层相对于金属栅极结构2002且特别是栅电极2006的材料具有高蚀刻选择性。晶种层可以通过旋涂、CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、PEALD、其他合适沉积方法或其组合。参考图22A和图22B的示例，形成伪层2202。在一些实施方式中，在沉积之后，进行诸如CMP的平坦化工艺，以除去多余的伪材料并提供平面顶表面，例如图22A和图22B中所示。
然后，方法100进入到框124，其中在伪层中形成多个沟槽定义栅极分离区。栅极分离区是那些被识别为器件的部分的区，此处相邻的栅极结构(例如，相邻的GAA器件)彼此绝缘。在一些实施例中，栅极分离区位于第一类型(例如，N-FET)和第二类型(例如，P-FET)的器件之间。可以通过在伪层上提供部件的图案来形成限定栅极分离区的多个沟槽。在一些实施例中，提供掩模元件以限定在要蚀刻多个沟槽的伪层上的开口。在一些实施例中，光刻工艺可以包括形成覆盖器件200的光刻胶层和伪层2202，将光刻胶层暴露于图案，执行曝光后烘烤以及，以及显影光刻胶层以形成包括光刻胶层的掩模元件。
根据光刻胶层提供的图案，在伪层中蚀刻沟槽。参考图23A和图23B的示例，沟槽2302形成在延伸到介电层1002和/或介电鳍1004的介电层1002和/或顶部的伪层2202中。并且在一些实施方式中，由于伪层2202和栅极结构2002(特别是栅电极2006)的成分，在它们之间的蚀刻选择性可以形成沟槽2302，使得基本上没有蚀刻金属栅极结构2002的材料。在一些实施例中，由于伪层2202和介电层1002的成分以及它们之间的蚀刻选择性，在一些实施方式中，可以形成沟槽2302，使得介电层1002基本上被释放。蚀刻工艺可以通过干蚀刻工艺形成。
然后，方法100进入到框126，其中沟槽填充有介电材料以形成栅极分离部件。填充沟槽的示例性介电材料包括SiO、SiN、SiC、SiCN、SiON、SiCN、SioCN、AlO、AlN、AlON、Zro、ZrN、ZrAlO、HfO和/或其组合。示例性沉积技术包括CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、PEALD、其他合适的沉积方法。在沉积之后，平坦化或其他回蚀刻工艺可以去除多余的材料以形成栅极分离部件。
参考图24A和图24B的示例，在沟槽2302中形成介电材料以形成栅极分离部件2402。在一些实现中，栅极分离部件2402是多层组件。介电材料可以通过各种沉积方法沉积，随后平坦化(例如通过CMP)，以提供图24A和图24B中所示的伪层2202的平面顶表面。
在沟槽中沉积材料之后，除去剩余的伪层。可以通过合适的选择性蚀刻工艺去除伪层，例如干蚀刻、湿蚀刻工艺或剥离工艺。如图25A和图25B的示例中所示，然后去除伪层2202。在一些实施方式中，伪层2202被去除而不撞击(例如，蚀刻)栅极。
然后，方法100前进到框128，其中在栅极结构上形成至少一个金属化层。在一些实施方式中，在相邻的栅极结构上形成至少一个金属化层并在栅极结构之间延伸。换句话说，金属化层可以在第一器件的第一栅极结构上方并与第一器件的第一栅极结构接触，并且延伸以位于相邻的第二器件的第二栅极结构上方并与第二器件的栅极结构接触，从而电连接两个栅极结构。在两个连接的栅极结构之间，金属化层在相邻器件的有源区之间的介质鳍上延伸。由于如上在框126中讨论的栅极分离部件，其他相邻的栅极结构(例如，邻近第一栅极结构的相对侧的第三栅极结构)可以彼此隔离。换句话说，金属化层在具有设置在它们之间的栅极隔离部件的器件的某些栅极之间不延伸，因此，在所述栅极之间不提供电连接。待连接和绝缘的栅极结构的图案化由器件设计确定，并且由形成框124的沟槽的图案(该图案提供栅极分离部件)来定义。
参考图26A和图26B的示例，在一个实施例中，在器件200上形成第一导电层(称为晶种层2602)和金属化层2604。如图26A所示，晶种层2602和金属化层2604可以在诸如从表示为2002A的第一栅极结构的某些栅极结构2002之间延伸到第二栅极结构(表示为2002B)以及第三栅极结构2002C和第四栅极结构2002D。栅极分离部件2402插入第二栅极结构2002B和第三栅极结构2002C，使得层2602和2604的金属化在栅极结构2002B和2002C之间不延伸。因此，金属化层2602、2604各自具有邻接栅极分离部件2402的终端。再次，每个栅极结构2002A、2002B、2002C、2002D为器件200的GAA器件部分提供栅极结构。
晶种层2602可包括Ti、TiN、TaN、W、Ru和/或其组合。示例性厚度包括约1nm至2nm之间的厚度。在一些实施方式中，选择厚度以提供足够的厚度，以粘附到覆盖层和金属化叠层的期望电阻率。金属层2604可包括其W、Ru、Co和/或其组合。示例性厚度包括约2nm和5nm之间的厚度。在一些实施方案中，选择厚度以提供足够的厚度，用于电导率与相邻的栅极堆叠。晶种层2602和/或金属化层2604的沉积工艺可包括CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、PEALD、电镀、无电镀、其他合适的沉积方法或其组合。
在一个实施例中，省略了晶种层2602，而金属层2604提供连接栅极子集的至少一个金属化层。这是图23A和图23B的器件200'的实施例的示例，器件200'的金属化层2604可以基本上类似于参考器件200所讨论的。
然后，方法100进入到框130，其中在框128的金属化层上形成绝缘层。示例性绝缘层材料包括SiO、SiN、SiC、SiCN、SiON、SiCN、SiOCN、AlO、AlN、AlON、ZrO、ZrN、ZrAlO、HfO和/或其组合。绝缘材料可以通过旋涂、HARP、CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、PEALD和/或其他合适方法沉积。在一些实施方式中，在沉积之后，通过平坦化工艺(例如，CMP)蚀刻绝缘材料，以通过栅极分离部件提供基本上共面的顶表面。参考图27A和图27B的示例，绝缘层2702形成在晶种/金属化层2602和2604上并与栅极分离部件2402相邻。在一些实施例中，绝缘层2702具有与栅极分离部件2402相同的组成。在其他实施例中，绝缘层2702与栅极分离部件2402的组成不同。
在一个实施例中，绝缘层2702可以邻接栅极间隔件，栅极间隔件又邻接与ILD1704相邻的B-CESL 1702。
然后，方法100进入到框132，其中形成框128的金属化层的接触元件。参考图28A和图28B的示例，接触元件2802形成为接合金属化层2604。接触元件2802可以提供用于从在器件200上形成的多层互连(MLI)与栅极结构2002电连接的路径。
MLI电耦合各种器件(例如，多栅极器件200的P型晶体管和/或N型晶体管、电阻器、电容器和/或电感器)和/或组件(例如，p型晶体管和/或n型晶体管的栅电极和/或外延源极/漏极部件)，使得各种器件和/或组件可以根据多栅极器件200的设计要求的规定操作。MLI部件通常包括介电层和被配置为形成各种互连结构的导电层(例如，金属层)的组合。导电层被配置为形成垂直互连部件，例如器件级接触件和/或通孔，以及诸如导线的水平互连部件。垂直互连部件通常连接在MLI的不同层(或不同平面)中的水平互连部件。在操作期间，互连部件被配置为在多栅极器件200的器件和/或组件之间路由信号，和/或将信号(例如，时钟信号、电压信号和/或接地信号)分配给多栅极器件200的器件和/或组件。
在一些实施例中，通过在栅极结构上延伸到金属化层的绝缘层中首先蚀刻通孔来形成接触件。在一些实施例中，通孔由光刻工艺限定。光刻工艺可以包括在绝缘层2702上形成光刻胶层，将光刻胶层曝光于图案化的辐射，并显影曝光的光刻胶层，从而形成图案化的光刻胶层，其可以用作用于蚀刻延伸通过绝缘层2702的接触开口的掩模元件的图案化光刻胶层，以暴露器件200的金属化层，特定地至少暴露金属层2604。蚀刻工艺包括干蚀刻工艺、湿蚀刻工艺、其他蚀刻工艺或其组合。此后，接触开口填充有一种或多种导电材料，例如钨、钌、钴、铜、铝、铱、钯、铂、镍、其它低电阻率金属成分、其合金或其组合。导电材料可以通过PVD、CVD、ALD、电镀、化学镀、其他合适的沉积工艺或其组合沉积。在一些实施例中，接触元件2802包括体层(也称为导电插塞)。在一些实施例中，接触元件2802包括阻挡层、粘附层和/或设置在体层和绝缘层2702之间的其他合适的层。在一些实施例中，阻挡层、粘附层和/或其他合适的层包括钛、钛合金(例如，锡)、钽、钽合金(例如，TAN)、其他合适的成分或其组合。MLI的附加部件可以与接触元件2802(包括例如金属线或导电通孔)的顶表面交界。
然后，方法100继续到框134，其中执行附加的制造步骤。附加的制造步骤可包括形成上面讨论的MLI的其他元件，包括与源极/漏极部件(诸如源极/漏极部件1602)的接触件。与源极/漏极部件的接触件(如接触元件2802)包括执行光刻工艺，包括在相应的ILD层1704和CESL1702上形成光刻胶层，将光刻胶层曝光于图案化的辐射，以及显影曝光的光刻胶层，从而形成图案化的光刻胶层，其可用作用于蚀刻通过ILD层1704和CESL1702延伸的源极/漏极接触开口的掩模元件，以暴露外延源极/漏极部件1602。蚀刻工艺包括干蚀刻工艺、湿蚀刻工艺、其它蚀刻工艺或其组合。此后，源极/漏极接触开口填充有一种或多种导电材料，例如钨、钌、钴、铜、铝、铱、钯、铂、镍、其它低电阻率金属成分、其合金、或其组合。导电材料可以通过PVD、CVD、ALD、电镀、化学镀、其他合适的沉积工艺或其组合沉积。在一些实施例中，源极/漏极接触件包括体层(也称为导电塞)，并且还包括阻挡层、粘附层和/或设置在体层和ILD层1704和/或CESL之间的其他合适的层。在一些实施例中，阻挡层、粘附层和/或其他合适的层包括钛、钛合金(例如，锡)、钽、钽合金(例如，TAN)、其它合适的组分或其组合。
因此，多栅极器件200包括多个栅极结构2002。在一些实现中，栅极结构2002A和2002B用于第一器件类型(例如，NFET)。在一些实现中，栅极结构2002C和2002D用于第二器件类型(例如，PFET)。
再次参考图29A和图29B，示出的器件200'基本上类似于器件200但具有金属化层2604并省略晶种层2602。再次参考图30A和图30B，所示的器件200”是基本上类似于器件200，但具有设置在栅极结构2002上的金属化层2604以及在栅极结构之间的晶种层2602。再次参考图31A和图31B，示出的器件200”'基本上类似于器件200，但具有金属化层2604、晶种层2602和蚀刻停止层3102。蚀刻停止层3102进一步详细讨论。
现在参考图32，示出了晶种层2602、金属化2604、栅极结构2002、栅极分离部件2402和绝缘层2702之间的界面的详细视图。如图32所示，这里用金属化层2604所示的金属化层中的至少一个的圆形端部，使得其具有曲线端面。特别地，金属化层2604的端部邻接栅极分离部件2402是圆形/曲线。在一些实施方案中，通过在邻近栅极分离部件2402的开口内形成金属化层2604来提供该曲线端部。图32示出了器件200的实施例，圆形也可以应用于器件200’、200”和/或200”’的一个或多个金属化层。
从前述描述中，可以看出，本公开中描述的多栅极器件提供了优于传统的多栅极器件的优点。然而，应该理解，其他实施例可以提供附加的优点，并且本文必须公开所有优点，并且对于所有实施例，不需要特定优点。一个优点是，与使用传统金属栅极切割技术制造的晶体管相比，本文所述的制造工艺减小了晶体管的金属栅极的尺寸和/或占位面积，从而允许晶体管的更高填充密度并增加IC图案密度。此外，在提供相邻栅极结构之间的分离时，一些实施例提供了避免对栅极结构的损坏，例如栅电极的功函数材料。通过提供分离，在沉积连接相邻栅极结构的金属化层之前，可以避免栅极损坏，例如，通过不切割在金属栅极结构上方的金属化层，其中可能限制蚀刻选择性。
本公开提供了多个不同的实施例。示例性器件包括：衬底；第一栅极结构，包裹设置在所述衬底上的沟道层周围；第二栅极结构，包裹设置在所述衬底上的另一沟道层周围；介电鳍结构，形成在浅沟槽隔离(STI)部件上方，其中，所述介电鳍结构在所述第一栅极结构和所述第二栅极结构之间；至少一个金属化层，在所述第一栅极结构、所述介电鳍结构和所述第二栅结构上，并且从所述第一栅极结构连续地延伸到所述第二栅极结构。
在上述器件中，所述至少一个金属化层包括晶种层和第一金属层。
在上述器件中，所述晶种层包括钛(Ti)、氮化钛(TiN)、钽(Tan)或钨(W)中的至少一种。
在上述器件中，所述晶种层的侧壁界面接合所述介电鳍结构。
在上述器件中，所述至少一个金属化层物理地接合所述介电鳍结构的顶表面。
在上述器件中，所述介电鳍结构的顶表面是高k介电材料。
在上述器件中，还包括：第三栅极结构，通过第二介电鳍与第二栅极结构分离，其中，栅极分离部件设置在所述第二介电鳍上方。
在上述器件中，所述至少一个金属化层邻接所述栅极分离部件的侧壁。
在上述器件中，所述至少金属化层的邻接所述栅极分离部件的侧壁的端部包括曲线表面。
在另外的实施例中，一种器件包括：第一沟道层，设置在衬底上方的第一源极/漏极部件之间；第一金属栅极，围绕所述第一沟道层；第二沟道层，设置在所述衬底上方的第二源极/漏极部件之间；第二金属栅极，围绕所述第二沟道层；介电鳍，设置在所述第一金属栅极和所述第二金属栅极之间并且分离所述第一金属栅极和所述第二金属栅极；导电层的第一部分，在所述第一金属栅极上方；导电层的第二部分，在所述第二金属栅极上方；以及隔离层，在所述导电层的所述第一部分和所述第二部分之间并且在所述介电鳍上方，其中，所述导电层的所述第一部分或所述导电层的所述第二部分中的至少一个包括邻接所述隔离层的圆形终端。
在上述器件中，所述隔离层与所述介电鳍的顶表面交界。
在上述器件中，还包括：在所述导电层的所述第一部分和所述第一金属栅极之间的蚀刻停止层。
在上述器件中，晶种层嵌入所述导电层的所述第一部分和所述第一金属栅极。
在上述器件中，所述晶种层的顶表面低于所述介电鳍的顶表面。
在另外的实施例中，一种方法包括：在衬底上方形成第一全环栅器件的第一栅极结构、第一源极结构和第一漏极结构；在所述衬底上方形成第二全环栅器件的第二栅极结构、第二源极结构和第二漏极结构，其中，介电鳍设置在所述第一栅极结构和所述第二栅极结构之间；在所述第一栅极结构、所述第二栅极结构和所述介电鳍上方沉积伪层；图案化所述伪层以在所述介电鳍上方形成在所述伪层内的沟槽；用介电材料填充所述沟槽以形成介电部件；在填充所述沟槽之后去除图案化的所述伪层；以及沉积具有所述第一栅极结构上方的第一部分和所述第二栅极结构的第二部分的至少一个导电层，其中，所述介电部件插入在所述第一部分和所述第二部分之间。
在上述方法中，还包括：将绝缘材料沉积在所述导电层的所述第一部分和所述第二部分上方。
在上述方法中，还包括：形成到所述导电层的所述第二部分的导电通孔。
在上述方法中，图案化所述伪层以形成所述沟槽包括选择性蚀刻所述伪层的材料，而基本上不蚀刻所述第一栅极结构或所述第二栅极结构。
在上述方法中，所述沉积所述至少一个导电层包括沉积晶种层和覆盖金属层。
在上述方法中，沉积所述至少一个导电层包括沉积具有邻接所述介电部件的圆形终端区的所述至少一个导电层的导电材料。
上述概述了几个实施例的特征，以便本领域技术人员可以更好地理解本公开的各个方面。本领域技术人员应当理解，他们可以容易地使用本公开作为设计或修改用于实现本文所介绍的实施例的相同目的和/或实现其相同优点的其它过程和结构的基础。本领域技术人员还应当认识到，此类等效结构不背离本发明的精神和范围，并且它们可以在不背离本发明的精神和范围的情况下在本发明中进行各种改变、替换以及改变。

Claims (10)

1.一种多栅极器件，包括：
衬底；
第一栅极结构，包裹设置在所述衬底上的沟道层周围；
第二栅极结构，包裹设置在所述衬底上的另一沟道层周围；
介电鳍结构，形成在浅沟槽隔离(STI)部件上方，其中，所述介电鳍结构在所述第一栅极结构和所述第二栅极结构之间；
至少一个金属化层，在所述第一栅极结构、所述介电鳍结构和所述第二栅结构上，并且从所述第一栅极结构连续地延伸到所述第二栅极结构。
2.根据权利要求1所述的多栅极器件，其中，所述至少一个金属化层包括晶种层和第一金属层。
3.根据权利要求2所述的多栅极器件，其中，所述晶种层包括钛(Ti)、氮化钛(TiN)、钽(Tan)或钨(W)中的至少一种。
4.根据权利要求3所述的多栅极器件，其中，所述晶种层的侧壁界面接合所述介电鳍结构。
5.根据权利要求1所述的多栅极器件，其中，所述至少一个金属化层物理地接合所述介电鳍结构的顶表面。
6.根据权利要求5所述的多栅极器件，其中，所述介电鳍结构的顶表面是高k介电材料。
7.根据权利要求1所述的多栅极器件，还包括：
第三栅极结构，通过第二介电鳍与第二栅极结构分离，其中，栅极分离部件设置在所述第二介电鳍上方。
8.根据权利要求7所述的多栅极器件，其中，所述至少一个金属化层邻接所述栅极分离部件的侧壁。
9.一种多栅极器件，包括：
第一沟道层，设置在衬底上方的第一源极/漏极部件之间；
第一金属栅极，围绕所述第一沟道层；
第二沟道层，设置在所述衬底上方的第二源极/漏极部件之间；
第二金属栅极，围绕所述第二沟道层；
介电鳍，设置在所述第一金属栅极和所述第二金属栅极之间并且分离所述第一金属栅极和所述第二金属栅极；
导电层的第一部分，在所述第一金属栅极上方；
导电层的第二部分，在所述第二金属栅极上方；以及
隔离层，在所述导电层的所述第一部分和所述第二部分之间并且在所述介电鳍上方，其中，所述导电层的所述第一部分或所述导电层的所述第二部分中的至少一个包括邻接所述隔离层的圆形终端。
10.一种形成多栅极器件的方法，包括
在衬底上方形成第一全环栅器件的第一栅极结构、第一源极结构和第一漏极结构；
在所述衬底上方形成第二全环栅器件的第二栅极结构、第二源极结构和第二漏极结构，其中，介电鳍设置在所述第一栅极结构和所述第二栅极结构之间；
在所述第一栅极结构、所述第二栅极结构和所述介电鳍上方沉积伪层；
图案化所述伪层以在所述介电鳍上方形成在所述伪层内的沟槽；
用介电材料填充所述沟槽以形成介电部件；
在填充所述沟槽之后去除图案化的所述伪层；以及
沉积具有所述第一栅极结构上方的第一部分和所述第二栅极结构的第二部分的至少一个导电层，其中，所述介电部件插入在所述第一部分和所述第二部分之间。
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