TW202203330A - 積體電路裝置及其製造方法 - Google Patents

積體電路裝置及其製造方法 Download PDF

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TW202203330A
TW202203330A TW110125282A TW110125282A TW202203330A TW 202203330 A TW202203330 A TW 202203330A TW 110125282 A TW110125282 A TW 110125282A TW 110125282 A TW110125282 A TW 110125282A TW 202203330 A TW202203330 A TW 202203330A
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layer
gate
dielectric
gate structure
integrated circuit
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TW110125282A
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TWI798749B (zh
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游家權
潘冠廷
朱熙甯
江國誠
王志豪
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台灣積體電路製造股份有限公司
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Abstract

一種積體電路裝置及其製造方法，包括第一閘極結構，包繞基板上方的通道層；第二閘極結構，包繞基板上方的另一通道層；以及介電鰭片結構，形成於淺溝槽隔離（shallow trench isolation；STI）部件上方，且位於第一閘極結構與第二閘極結構之間。至少一金屬化層，形成於第一閘極結構、介電鰭片結構、以及第二閘極結構上，且自第一閘極結構毗鄰地（contiguously）延伸至第二閘極結構。

Description

積體電路裝置及其製造方法
本發明實施例是關於積體電路裝置，特別是關於多閘極裝置的金屬閘極切割技術。
電子產業對更小及更快的電子裝置經歷了不斷增長的需求，其同時能支持大量越來越複雜及精密的功能性。因此，在半導體產業中一直存在製造低成本、高效能、及低功耗積體電路（integrated circuit ；IC）的趨勢。迄今為止，這些目標很大部分已藉由微縮化半導體積體電路尺寸（例如最小部件尺寸）來實現且因此改善了生產效率及降低了相關成本。然而，此微縮化也同樣增加了半導體生產製程複雜度。因此，若要在半導體積體電路及裝置中實現持續的進展，也需要在半導體生產製程及技術中有近似的進展。
近來，多閘極裝置已被導入以藉由增加閘極通道耦合、降低截止狀態（OFF-state）電流、及降低短通道效應（short-channel effects；SCEs）來試圖改善閘極控制。其中一種多閘極裝置為全繞式閘極（gate-all-around；GAA）裝置，其包括了可以部分地或完全地延伸圍繞通道區的閘極結構，以提供對通道區至少兩側上的存取。全繞式閘極裝置允許積體電路技術激進地微縮化同時維持閘極控制及減輕短通道效應，同時與傳統積體電路製造製程無縫地整合。然而，隨著全繞式閘極持續的微縮化，通常用於將不同的全繞式閘極裝置的多個閘極相互隔離的非自對準（non-self-aligned）閘極切割技術，諸如將第一全繞式閘極電晶體的第一閘極與第二全繞式閘極電晶體的第二閘極隔離，正阻礙著先進的積體電路技術節點所需的積體電路部件的密集封裝。因此，儘管現有的全繞式閘極裝置與其製造的方法通常都能滿足其預期的目的，但並非在所有面向上都完全令人滿意。
本發明實施例提供一種積體電路裝置，包括：基板；第一閘極結構，包繞基板上方的通道層；第二閘極結構，包繞基板上方的另一通道層；介電鰭片結構，形成於淺溝槽隔離（shallow trench isolation；STI）部件上方，其中介電鰭片結構位於第一閘極結構與第二閘極結構之間；以及至少一金屬化層，於第一閘極結構、介電鰭片結構、以及第二閘極結構上，且自第一閘極結構毗鄰地（contiguously）延伸至第二閘極結構。
本發明實施例提供一種積體電路裝置，包括：第一通道層，設置於基板上方的多個第一源極∕汲極部件之間；第一金屬閘極，圍繞第一通道層；第二通道層，設置於基板上方的多個第二源極∕汲極部件之間；第二金屬閘極，圍繞第二通道層；介電鰭片，設置於第一金屬閘極與第二金屬閘極之間且分隔第一金屬閘極與第二金屬閘極；導電層的第一部份，於第一金屬閘極上方；導電層的第二部份，於第二金屬閘極上方；以及隔離層，於導電層的第一部份與導電層的第二部分之間以及介電鰭片上方，其中導電層的第一部份或導電層的第二部分的至少其一包括圓化終端與隔離層鄰接。
本發明實施例提供一種積體電路裝置的製造方法，包括：形成第一全繞式閘極裝置的第一閘極結構、第一源極結構以及第一汲極結構於基板上方；形成第二全繞式閘極裝置的第二閘極結構、第二源極結構以及第二汲極結構於基板上方，其中介電鰭片設置於第一閘極結構與第二閘極結構之間；沉積虛置層於第一閘極結構、第二閘極結構、以及介電鰭片上方；圖案化虛置層以形成溝槽於介電鰭片上方的虛置層之中；以介電材料填充溝槽以形成介電部件；於填充溝槽後移除圖案化的虛置層；以及沉積至少一導電層，其具有第一部份位於第一閘極結構上方與第二部分位於第二閘極結構上方，其中介電部件穿插於第一部份與第二部分之間。
本發明實施例是關於積體電路裝置，特別是關於多閘極裝置的金屬閘極切割技術。
以下揭露提供了許多的實施例或範例，用於實施所提供的標的物之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複參考數值以及∕或字母。如此重複是為了簡明和清楚之目的，而非用以表示所討論的不同實施例及∕或配置之間的關係。
再者，其中可能用到與空間相對用詞，例如「較低的」、「較高的」、「水平的」、「垂直的」、「在……之上」、「上方」、「下方」、「在……之下」、「上部」、「下部」、「頂部」、「底部」等類似用詞以及上述之衍生詞（例如「水平地」、「向下地」、「向上地」等），是為了便於描述圖式中一個（些）部件或特徵與另一個（些）部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
此外，當使用 「大約」、「近似」等描述一個數字或數字範圍時，此用語意圖涵蓋合理範圍內的數字，此範圍是根據本領域具有通常知識者所理解的製造過程中固有出現的變異而加以考量。 例如，基於製造具有該數字相關特徵的部件的已知製造公差，數字的數量或範圍涵蓋了包括所述數字在內的合理範圍，例如所述數字的+/-10%以內。 例如，本領域具有通常知識者已知與沈積材料層相關的製造公差為+/- 10%，具有 「約5奈米」厚度的材料層可以涵蓋4. 5奈米至5.5奈米的尺寸範圍。
在形成積體電路的過程中，可以透過設計來提供使某些閘極結構彼此隔離。為了提供此隔離，有時被稱作閘極切割技術的這些製程，被使用來提供位於第一通道區上方的第一閘極結構與位於第二通道區上方的第二閘極結構彼此分隔以及隔離。可形成例如包括多個絕緣層的閘極隔離部件或閘極分隔部件，以提供電性隔離於第一閘極與第二閘極之間以及各個閘極的電性接觸件之間，第一閘極可設置於第一全繞式閘極裝置的第一通道層上方（亦即，第一主動裝置區），第二閘極可設置於第二全繞式閘極裝置的第二通道層上方（亦即，第二主動裝置區）。然而，在裝置的其他部分中，這些製程包含了提供第三閘極結構電性地連接至另一個閘極結構，諸如第一閘極結構。
於此了解到，如何提供可形成分隔結構於鄰近的閘極之間且不損害或傷害閘極本身的製程，諸如蝕刻製程，是非常重要的。例如，在形成分隔結構中非期望的閘極蝕刻或損失可能導致非期望的閘極高度降低，其可能不利於裝置預期的可靠度及∕或性能表現。本文所討論的方法及裝置提供了形成分隔物於多個閘極結構之間，同時連接其他閘極結構，在一些實施例中避免了閘極結構材料的損失。避免閘極結構材料的損失允許了在裝置設計中可存在較低閘極高度的實施例，其可提供裝置的交流電（Alternating Current；AC）性能的改善。
同樣於此了解到，在一些實施例中，本揭露提供了透過自對準製程提供閘極切割、以及部分閘極連接的裝置及方法。本揭露因此提供了多閘極裝置的技術，相較於非自對準閘極切割技術的主動裝置區之間因為某些製程失準需要額外的間距，本揭露的技術允許了主動裝置區之間具有更小的間距。因此，在一些實施例中，本揭露提出的自對準閘極切割技術允許了諸如金屬閘極的尺寸的減少，從而增加了圖案的密度。本揭露所提出的多閘極裝置的自對準閘極分隔（或切割）技術以及所形成的多閘極裝置之某些實施例的細節已於本文下方描述。同樣地，本揭露所提出的於多閘極裝置的多個閘極結構之間提供自對準閘極電性連接的形成技術以及所形成的多閘極裝置之某些實施例的細節已於本文下方描述。
現在參見第1圖，第1圖繪示出製造半導體裝置200的方法100流程圖，第2-19、20A、21A、22A、23A、24A、25A、26A、27A圖以及第28A圖繪示出局部的透視示意圖，第20B、21B、22B、23B、24B、25B、26B、27B、28B圖以及第32圖繪示出局部的剖面示意圖。裝置200’、200’’以及200’’’繪示於上述參考圖的多個面向中，此外第29A∕B、30A∕B、31A∕B圖各自對應於上述的裝置200’、200’’以及200’’’，且皆為可由方法100的多個面向形成的近似地例示性裝置。值得注意的是，裝置200揭露的示例包含全繞式閘極裝置，然而，本揭露的多個面向可同樣應用於其他裝置類型諸如鰭片型的場效電晶體（fin-type field effect transistors；FinFET）。
方法100僅為示例，且不意圖將本揭露作出除了請求項中明確記載範圍之外的限制。可提供額外的步驟於方法100之前、期間、及之後，且一些描述的步驟可以為了方法的額外實施例被替換、消除、或移動。為了簡單起見，此處並無詳細描述所有步驟。而除了本發明實施例明確繪示的圖之外，半導體裝置200可包括額外的電晶體、雙極性電晶體（bipolar junction transistors）、電阻器、電容器、二極體、熔斷器（fuses）等等，但皆已被簡化以更好地理解本揭露的發明概念。在本發明實施例全文中，除非另有說明或描述，相似的元件符號用來表示相似的部件。除非特別指出例示性裝置200、200’、200’’、以及200’’’的不同之處，本文對其中一個裝置的描述可適用於其他例示性裝置。
方法100於方框102開始，接收了具有形成複數個鰭片結構於上方的基板。參見第2圖的示例，提供了基板202。在一實施例中，基板202可以為矽（Si）基板。在一些其他實施例中，基板202可包含其他的半導體諸如鍺（Ge）、矽鍺（SiGe）、或III-V族半導體材料。例示的III-V族半導體材料可包括砷化鎵（GaAs）、磷化銦（InP）、磷化鎵（GaP）、氮化鎵（GaN）、磷砷化鎵（GaAsP）、砷化鋁銦（AlInAs）、砷化鋁鎵（AlGaAs）、磷化鎵銦（GaInP）、以及砷化銦鎵（InGaAs）。基板202可同樣包含絕緣層，諸如氧化矽層，以具有絕緣體上覆矽（silicon-on-insulator；SOI）結構或絕緣體上覆鍺（germanium-on-insulator；GOI）結構。在一些實施例中，為了形成不同裝置的類型，基板202可包含一或多個井區，諸如摻雜n型摻質（亦即，磷（P）或砷（As））的n型井區或摻雜p型摻質（亦即，硼（B））的p型井區。可進行離子佈植製程、擴散製程、及∕或其他合適的摻雜製程以形成各種摻雜區。
繼續參見第2圖，可設置多個磊晶層的堆疊204於基板202上。堆疊204可包含交織（interleaved）在一起的複數個犧牲層206與複數個通道層208。通道層208與犧牲層206可具有不同的半導體組成。犧牲層206與通道層208為交替地沉積，一個接著另一個，以形成堆疊204。在一些實施例中，通道層208是由矽（Si）形成而犧牲層206是由矽鍺（SiGe）形成。在一些實施例中，犧牲層206中額外的鍺含量可允許犧牲層206的選擇性移除或凹蝕且避免對通道層208造成實質的傷害，如下方的討論。在一些實施例中，包含了犧牲層206與通道層208的堆疊204可使用磊晶製程沉積材料來形成。例示性技術包括但不限於化學氣相沉積（Chemical Vapor Deposition；CVD）技術（例如氣相磊晶（vapor-phase epitaxy；VPE）及∕或超高真空化學氣相沉積（ultra-high vacuum CVD；UHV-CVD））、分子束磊晶（molecular beam epitaxy；MBE）、及∕或其他合適的製程。值得注意的是，三層的犧牲層206以及三層的通道層208為交替地且垂直地配置（arrange），如第2圖所繪示。然而，此處僅作說明之用且不意圖將本揭露作出除了請求項中明確記載範圍之外的限制。膜層的數目取決於半導體裝置200之通道數所需的數目。在一些實施例中，通道層208的數目在2與10之間。為了方便圖案化，可設置硬遮罩層210於堆疊204上方。硬遮罩層210可為單層或多層。在一實施例中，硬遮罩層210包含氧化矽層210A以及氮化矽層210B。
方法100的方框102可包含形成複數個鰭片結構延伸至基板上方。每個鰭片結構定義了基板上的主動區。參見第2圖的示例，鰭片結構212是由磊晶的堆疊204所形成。儘管在例示性示意圖中僅繪示出二或四個鰭片結構，此處僅作說明之用且不意圖將本揭露作出除了請求項中明確記載範圍之外的限制。鰭片結構212可使用包含光學微影與蝕刻製程的合適製程來製造。光學微影製程可包含形成光阻層上覆於基板202、將圖案曝光至光阻層、執行後曝光烘烤（post-exposure bake）製程、以及對光阻層顯影以形成包括光阻層的遮罩元件。在一些實施例中，遮罩元件更包含於上方所討論的硬遮罩層210。在一些實施例中，可使用電子束微影製程來進行圖案化光阻層以形成遮罩元件。可使用包含了雙重圖案化或多重圖案化製程之合適的製程來圖案化鰭片結構212。一般來說，雙重圖案化或多重圖案化製程結合了微影製程與自對準製程，以創建出例如，比使用單一、直接微影製程所得的節距更小的圖案。例如，在一實施例中，在基板上方形成犧牲層，並使用微影製程對其進行圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。之後去除犧牲層，然後可以使用剩餘的間隔物或心軸作為遮罩以圖案化鰭片。因此，例示的製程包含了雙重圖案化微影製程（double patterning lithography；DPL）（例如，微影-蝕刻-微影-蝕刻（lithography-etch-lithography-etch；LELE）製程、自對準雙重圖案化（self-aligned double patterning；SADP）製程、介電間隔物（spacer-is-dielectric；SID）自對準雙重圖案化製程、其他雙重圖案化製程、或上述之組合）、三重圖案化製程（例如，微影-蝕刻-微影-蝕刻-微影-蝕刻（lithography-etch-lithography-etch-lithography-etch；LELELE）製程、自對準三重圖案化（self-aligned triple patterning；SATP）製程、其他三重圖案化製程、或上述之組合）、其他多重圖案化製程（例如，自對準四重圖案化（self-aligned quadruple patterning；SAQP）製程）、或上述之組合。
上方描述的（多個）遮罩元件可接著在蝕刻鰭片結構212時被使用來保護堆疊204及∕或基板202的區域。溝槽214的蝕刻可使用乾式蝕刻（例如，化學氧化物移除）、濕式蝕刻、反應式離子蝕刻（reactive ion etching；RIE）、及∕或其他合適的製程。也可以使用眾多的方法的其他實施例來形成鰭片結構212於基板202上。鰭片結構212垂直地（Z方向）延伸至基板202上方，而長度方向則沿著基板202的Y方向，且在X方向上與鄰近的鰭片結構212間隔。每個鰭片結構212包含了由部分基板202’形成的基底部分以及由堆疊204的多個材料形成的上覆部分。
在一些實施例中，方法100的方框102包含了形成一或多層膜層於蝕刻後的鰭片結構上方。在一些實施例中，形成氧化物襯層（例如，氧化矽）於基板以及鰭片結構上方。在一些實施例中，形成矽襯層於基板以及鰭片結構上方。參見第3圖，形成氧化物襯層216以及矽襯層218於鰭片結構212上方。在一些實施例中，氧化物襯層216及∕或矽襯層218為順應的膜層，具有實質上為定值的厚度。在一些實施例中，氧化物襯層216及∕或矽襯層218是由化學氣相沉積、物理氣相沉積（physical vapor deposition；PVD）、高密度電漿化學氣相沉積（high density plasma CVD；HDPCVD）、有機金屬化學氣相沉積（metal organic CVD；MOCVD）、遠距電漿化學氣相沉積（remote plasma CVD；RPCVD）、電漿增強化學氣相沉積（plasma enhanced CVD；PECVD）、低壓化學氣相沉積（low-pressure CVD；LPCVD）、原子層化學氣相沉積（atomic layer CVD；ALCVD）、常壓化學氣相沉積（atmospheric pressure CVD；APCVD）、次常壓化學氣相沉積（sub-atmospheric CVD；SACVD）、其他合適的方法、或上述之組合來形成。在一些實施例中，矽襯層218包含了n型摻質及∕或p型摻質。
方法100接著進行至方框104，形成多個隔離部件穿插於複數個鰭片結構之間。隔離部件可被稱為淺溝槽隔離部件。參見第4圖的示例，形成隔離層402於鰭片結構212之間與溝槽214之內。在一實施例中，隔離材料為諸如包含了襯層以及如氧化物材料的上覆層的多膜層。在一些實施例中，氧化物材料是由可流動化學氣相沉積（flowable CVD；FCVD）製程來沉積，其包含了例如沉積可流動的氧化物材料（如液態材料）於多閘極裝置200上方以及透過退火製程將可流動的氧化物材料轉化為固態的氧化物材料。可流動的氧化物材料可流入溝槽214之中以及順應多閘極裝置200暴露的表面，在一些實施例中可實現溝槽214的無孔洞填充。
在一些實施例中，形成隔離層402的隔離材料可包含SiO2 、氮化矽、氮氧化矽、氟摻雜矽酸鹽玻璃（fluorine-doped silicate glass；FSG）、低介電常數介電材料、上述之組合、及∕或本發明所屬技術領域中已知的其他合適的材料。在各種示例中，介電材料可由化學氣相沉積製程、次常壓化學氣相沉積製程、可流動化學氣相沉積製程、原子層沉積（atomic layer deposition；ALD）製程、物理氣相沉積製程、或其他合適的製程來沉積。
沉積製程可過度填充溝槽214（未繪示）使得隔離部件402的材料的厚度會大於鰭片結構212的高度。在沉積製程後，對材料進行平坦化製程，例如化學機械拋光（chemical mechanical polishing；CMP）處理，從而減少厚度。在一些實施例中，矽襯層218是作為蝕刻停止層且平坦化會在暴露鰭片結構212上方的矽襯層218後停止。此平坦化形成了諸如第4圖中所繪示的表面。
接著參見第5圖，可接著凹蝕（多個）絕緣材料，使得鰭片結構212於藉由隔離層402所形成的隔離部件之間延伸（突出）。凹蝕隔離材料的蝕刻製程被設定為相對矽襯層218而言，可選擇性地移除其他材料（例如，氧化物）。例如，蝕刻製程會選擇對氧化矽（亦即，隔離部件402的氧化矽）的蝕刻速率大於對矽（亦即，矽襯層218）的蝕刻速率的蝕刻劑。因此，隔離部件402填充鰭片結構212之間的溝槽214的多個部分。在一些實施例中，場氧化物、矽的局部氧化（Local Oxidation Of Silicon；LOCOS）部件、及∕或其他合適的隔離部件可額外地或替代地實施於基板上及∕或基板之中。
方法100接著進行至方框106，形成包覆層（cladding layer）於鰭片結構上方。包覆層可為犧牲層。可形成包覆層於每個鰭片結構上方。參見第6圖的示例，形成包覆層602於每個鰭片結構212上。在一些實施例中，包覆層602可具有與犧牲層206相似的組成。在一實施例中，包覆層602是由矽鍺（SiGe）所形成。在一些實施例中，包覆層602與犧牲層206包含了允許在後續的製程中透過單一蝕刻劑釋放通道層208時可被選擇性去除的犧牲層206以及包覆層602的組成，將在下方更詳細的討論。 在一實施例中，可磊晶地成長包覆層602，如使用氣相磊晶（vapor phase epitaxy；VPE）、分子束磊晶（molecular bean epitaxy；MBE）、或由諸如化學氣相沉積製程、次常壓化學氣相沉積製程、可流動化學氣相沉積製程、原子層沉積製程、物理氣相沉積製程、或其他合適的製程等沉積的製程來形成。在進行沉積後，在一些實施例中，方框106的操作步驟可包含回蝕刻製程以從隔離部件402上移除例如順應地沉積的包覆層602的材料。在一些實施例中，方框106可被省略。
方法100接著進行至方框108，形成分隔結構（也被稱作介電鰭片）於鰭片結構的上部部分之間，因此分隔了鄰近的多個主動區。分隔結構可包含填充鰭片結構之間的空隙與設置於方框104的淺溝槽隔離部件上方的多膜層結構。第7-10圖繪示出形成多膜層分隔結構或介電鰭片於多個主動區之間的一實施例。首先參見第7圖的示例，沉積第一介電層702於裝置200上方。在一實施例中，第一介電層702為高介電常數介電質。在一實施例中，第一介電層702可以為氮化矽、氮碳化矽（SiCN）、氮碳氧化矽（SiOCN）、或上述之組合。在一些實施例中，第一介電層702包含HfO2 、HfSiO、HfSiO4 、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx 、ZrO、ZrO2 、ZrSiO2 、AlO、AlSiO、Al2 O3 、TiO、TiO2 、LaO、LaSiO、Ta2 O3 、Ta2 O5 、Y2 O3 、SrTiO3 、BaZrO、BaTiO3 （BTO）、（Ba,Sr）TiO3 （BST）、HfO2 -Al2 O3 、其他合適的高介電常數介電材料、或上述之組合。接續第一層，參見第8圖的示例，可接著形成氧化物層802於第一介電層702上方。在一些實施例中，氧化物層802可以由可流動化學氣相沉積製程、高深寬比製程（High aspect ratio process；HARP）、及∕或其他製程來沉積以提供合適的空隙填充特性。在一些實施例中，氧化物層802可過度填充溝槽214，且在氧化物層802的沉積後，可進行化學機械拋光處理以提供實質上平坦的頂表面，如第8圖所繪示。在一實施例中，包覆層602在此平坦化處理中提供了使蝕刻停止的作用。
參見第9圖，回蝕刻第一介電層702及∕或氧化物層802以形成開口902。在一實施例中，移除氧化物層802以形成開口902，開口902具有的側壁是由第一介電層702所定義且受限於溝槽214。形成開口902的蝕刻製程可以是乾式蝕刻製程、濕式蝕刻製程、或上述之組合。
如第10圖所繪示，形成介電材料1002於開口902之中。可沉積介電材料1002並使得其溢出開口902，且隨後多餘的材料將透過平坦化處理來移除。在一實施例中，介電材料1002為高介電常數介電質。在一些實施例中，介電材料1002實質上與第一介電層702具有相同的組成。在一實施例中，介電材料1002可以為氮化矽、氮碳化矽（SiCN）、氮碳氧化矽（SiOCN）、或上述之組合。在一些實施例中，介電材料1002包含HfO2 、HfSiO、HfSiO4 、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx 、ZrO、ZrO2 、ZrSiO2 、AlO、AlSiO、Al2 O3 、TiO、TiO2 、LaO、LaSiO、Ta2 O3 、Ta2 O5 、Y2 O3 、SrTiO3 、BaZrO、BaTiO3 、（Ba、Sr）TiO3 、HfO2 -Al2 O3 、其他合適的高介電常數介電材料、或上述之組合。介電材料1002可以由合適的製程沉積，諸如次常壓化學氣相沉積製程、可流動化學氣相沉積製程、其他化學氣相沉積製程、原子層沉積製程、物理氣相沉積製程、或其他合適的製程。在一些實施例中，接續沉積製程，進行平坦化處理從而使沉積的介電材料1002變薄以提供平坦的頂表面。在一些實施例中，平坦化處理可停止於硬遮罩層210。
上方討論的介電層702、802、以及1002共同形成了分隔結構，也被稱作介電鰭片1004。介電鰭片1004延伸於鄰近的主動區與鰭片結構212之間，以及延伸於包覆層602的多個部分之間。介電鰭片1004也被視為近似於鰭片結構212，介電鰭片1004垂直地（Z方向）延伸至基板202上方（特別是隔離結構402上方），而長度方向則沿著基板202的Y方向，且在X方向上與鄰近的借電鰭片1004間隔。
在一些實施例中，在形成分隔結構或介電鰭片1004後以及準備形成虛置閘極之前，蝕刻硬遮罩層210與鄰近的包覆層602以形成開口1102，如第11圖所繪示。在一些實施例中，蝕刻暴露了通道區的上表面，下方將討論如何形成閘極結構於通道區的上表面上。
方法100接著進行至方框110，形成虛置閘極於鰭片結構上方。參見第12圖，形成虛置閘極結構1202於鰭片結構212的多個部分與介電鰭片1004的多個部分上方。虛置閘極結構1202填充開口1102的多個部分且可延伸至介電鰭片1004上方。虛置閘極結構1202的長度方向延伸至不同於（例如，垂直於）鰭片結構212的長度方向的方向中。例如，實質上彼此平行的虛置閘極結構1202沿著X方向延伸，長度的定義為X方向上的長度，寬度的定義為Y方向上的寬度，以及高度的定義為Z方向上的高度。設置虛置閘極結構1202於多閘極裝置200的多個通道區上方以及於多閘極裝置200的多個源極∕汲極區之間，亦即被開口1102的剩餘物所暴露的區域。每個虛置閘極結構1202包含虛置閘極介電質1204、虛置閘極電極1206、以及硬遮罩1208（包含例如第一遮罩層1208A以及第二遮罩層1208B，在一些實施例中，包含墊氧化物1208A以及墊氮化物1208B）。虛置閘極介電質1204包含介電材料（諸如氧化矽）、高介電常數介電材料、其他合適的介電材料、或上述之組合。在一些實施例中，虛置閘極介電質1204包含界面層（包含例如氧化矽）以及設置於界面層上方的高介電常數介電層。虛置閘極電及1206包含了合適的虛置閘極材料，諸如多晶矽。在一些實施例中，虛置閘極結構1202包含了多個其他的膜層，例如蓋層、界面層、擴散層、阻障層、或上述之組合。虛置閘極結構1202是由沉積製程、微影製程、蝕刻製程、其他合適的製程、或上述之組合的製程所形成。例如，進行第一沉積製程以形成虛置閘極介電質於多閘極裝置200上方，進行第二沉積製程以形成虛置閘極電極層於虛置閘極介電質上方，以及進行第三沉積製程以形成硬遮罩層於虛置閘極電極層上方。在一實施例中，硬遮罩層1208包含了氧化矽層1208A以及氮化矽層1208B。沉積製程包含了化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠距電漿化學氣相沉積、電漿增強化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、電鍍、其他合適的方法、或上述之組合。接著進行微影圖案化與蝕刻製程以圖案化硬遮罩層、虛置閘極電極層、以及虛置閘極介電質以形成虛置閘極結構1202，虛置閘極結構1202包含了虛置閘極介電質1204、虛置閘極電極1206、以及硬遮罩1208，如第12圖所描繪。微影圖案化製程包含了光阻塗佈（例如，旋轉塗佈（spin-on coating））、軟烘烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、潤洗、乾燥（例如，硬烘烤）、其他合適的微影製程、或上述之組合。蝕刻製程包含了乾式蝕刻製程、濕式蝕刻製程、其他蝕刻方法、或上述之組合。
參見第13圖，虛置閘極結構1202可進一步包含沿著虛置閘極結構1202的側壁形成閘極間隔物1302。閘極間隔物1302可包含合適的介電材料。合適的介電材料可包含矽、氧、碳、氮、其他合適的材料、或上述之組合（例如，氧化矽、氮化矽、氮氧化矽、碳化矽、氮碳化矽、碳氧化矽、及∕或氮碳氧化矽）。在一些實施例中，閘極間隔物1302包含多膜層結構，例如包含氮化矽的第一介電層以及包含氧化矽的第二介電層。在一些實施例中，可形成一組以上的間隔物鄰近於虛置閘極結構1202，例如密封間隔物、偏移間隔物、犧牲間隔物、虛置間隔物、及∕或主要間隔物。
方法100接著進行至方框112，凹蝕鄰近虛置閘極結構的鰭片結構的源極∕汲極區。在第13圖中，在多閘極裝置200的源極∕汲極區中的鰭片結構的多個部分（亦即，未被閘極結構1202覆蓋的鰭片結構212的源極∕汲極區）也至少部分地被移除，以形成源極∕汲極凹槽或溝槽1304。在描繪的實施例中，蝕刻製程完全地移除了多閘極裝置200的源極∕汲極區中的半導體層堆疊204，從而暴露源極∕汲極區中的鰭片部分202’。在一些實施例中，蝕刻製程同樣完全地移除了源極∕汲極區中的包覆層602的多個部分。在描繪的實施例中，每個源極∕汲極凹槽1304因而具有由各自的一個介電鰭片1004定義的側壁以及由各自的鰭片部分202’與各自的隔離部件402定義的底部。蝕刻製程可包含乾式蝕刻製程、濕式蝕刻製程、其他合適的蝕刻製程、或上述之組合。在一些實施例中，蝕刻製程為多步驟蝕刻製程。
參見第14圖以及第15圖，在一些實施例中，方格112更包含了輕微地（橫向地）蝕刻犧牲層206以形成開口1402（例如，於閘極結構1202下方並包含閘極間隔物1302）。形成開口1402於通道層208的多個懸浮終端區之間。可形成內間隔物1502於開口1402之中。在一些實施例中，內間隔物1502包含介電材料，其包括了矽、氧、碳、氮、其他合適的材料、或上述之組合（例如，氧化矽、氮化矽、氮氧化矽、碳化矽、及∕或氮碳氧化矽）。在一些實施例中，內間隔物1502包含低介電常數介電材料，諸如此處所描述的材料。
方法100接著進行至方框114，成長源極∕汲極部件於鰭片結構凹蝕的源極∕汲極區中。參見第16圖，形成磊晶源極∕汲極部件1602，標示為1602A與1602B，於源極∕汲極凹槽1304中。在一些實施例中，從包含基板202的鰭片部分202’的暴露表面的晶種區磊晶地成長半導體材料，形成磊晶源極∕汲極部件1602A於源極∕汲極凹槽1304中，磊晶源極∕汲極部件1602A對應於第一類型的電晶體諸如n型電晶體，形成磊晶源極∕汲極部件1602B於源極∕汲極凹槽1304中，磊晶源極∕汲極部件1602B對應於第二類型的電晶體諸如p型電晶體。在一些實施例中，形成磊晶源極∕汲極部件1602的磊晶製程可使用化學氣相沉積技術（例如，低壓化學氣相沉積、氣相磊晶、及∕或超高壓化學氣相沉積）、分子束磊晶、其他合適的磊晶成長製程、或上述之組合。磊晶製程可使用氣態及∕或液態的前驅物，其與（多個）晶種區的組成相互影響。磊晶源極∕汲極部件1602A與1602B為各自摻雜n型摻質及∕或p型摻質。在一些實施例中，對n型電晶體來說，磊晶源極∕汲極部件1602A包含了矽，其可以被摻雜碳、磷、砷、其它n型摻質、或上述之組合（例如，形成Si：C磊晶源極∕汲極部件、Si：P磊晶源極∕汲極部件、或Si：C：P磊晶源極∕汲極部件）。在一些實施例中，對p型電晶體來說，磊晶源極∕汲極部件1602B包含了矽鍺或鍺，其可以被摻雜硼、其它p型摻質、或上述之組合（例如，形成Si：Ge：B磊晶源極∕汲極部件）。在一些實施例中，磊晶源極∕汲極部件1602包含了一層以上的磊晶半導體層，其中磊晶半導體層可包含相同或不同的材料及∕或相同或不同的摻質濃度。在一些實施例中，磊晶源極∕汲極部件1602是在沉積期間藉由加入雜質至磊晶製程的源材料中來進行摻雜（亦即，原位（in-situ））。在一些實施例中，磊晶源極∕汲極部件1602是藉由成長製程後的離子佈植製程來進行摻雜。在一些實施例中，當形成不同裝置類型的磊晶源極∕汲極部件時，磊晶源極∕汲極部件1602A與磊晶源極∕汲極部件1602B是以分開的製程順序形成。
方法100接著進行至方框116，形成絕緣材料於包含源極∕汲極部件上方的基板上。所形成的絕緣材料可以是讓後續形成連接至源極∕汲極部件的接觸元件穿過的材料。絕緣材料提供了源極∕汲極接觸件與例如鄰近的閘極結構之間的隔離性。絕緣材料也可被稱作接觸蝕刻停止層（contact etch stop layer；CESL）以及層間介電層（interlayer dielectric；ILD）。接觸蝕刻停止層可用作使形成連接至源極∕汲極部件的接觸元件的蝕刻停止（未繪示）。參見第17圖的示例，進行（多個）沉積製程（諸如化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠距電漿化學氣相沉積、電漿增強化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、可流動化學氣相沉積、高深寬比製程、高密度電漿、其它合適的方法、或上述之組合）以形成介電層1702以及1704於裝置200上。在一實施例中，介電層1704為層間介電層而介電層1702為底部接觸蝕刻停止層。介電層1704可包含介電材料包括如氧化矽、碳摻雜氧化矽、氮化矽、氮氧化矽、四乙氧基矽烷（Tetraethoxy silane；TEOS）形成的氧化物、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽酸鹽玻璃（borosilicate glass；BSG）、硼磷矽酸鹽玻璃（borophosphosilicate glass, BPSG）、氟矽酸鹽玻璃（Fluorosilicate glass；FSG）、Black Diamond®（應用材料，加州聖塔克拉拉）、乾凝膠（xerogel）、氣凝膠（aerogel）、非晶質氟化碳（amorphous fluorinated carbon）、聚對二甲苯（parylene）、苯並環丁烯（benzocyclobutene, BCB）為主的介電材料、SiLK®（陶氏化學，密西根米特蘭）、聚亞醯胺（polyimide）、其它合適的介電材料、或上述之組合。在一些實施例中，介電層1704包含了具有小於二氧化矽的介電常數（例如，介電常數＜3.9）的介電材料。在一些實施例中，介電層1704包含了具有小於介電常數2.5（亦即，超低介電常數（extreme low-k；ELK）介電材料）的介電材料，諸如二氧化矽（SiO2 ）（例如，多孔二氧化矽）、碳化矽（SiC）、及∕或碳摻雜氧化物（例如，以SiCOH為主的材料（具有如Si-CH3 鍵結）），其中每個介電材料都被調整∕配置（configured）為表現出低於約2.5的介電常數。介電層1702包含了不同於介電層1704的材料。介電層1702的例示性組成包括但不限於氮化矽或氮氧化矽。
在一些實施例中，進行化學拋光處理及∕或其他平坦化處理於沉積後直至暴露虛置閘極結構1202的頂部部分。在一些實施例中，平坦化處理移除了虛置閘極結構1202的硬遮罩層1208以暴露下方的虛置閘極電極1206（例如，多晶矽）。
方法100接著進行至方框118，形成金屬閘極結構的開口，包含藉由移除虛置閘極結構以及釋放鰭片結構的通道區之中的通道層。在方框118的實施例中，移除方框110的虛置閘極結構。參見第18圖的示例，移除虛置閘極結構1202以形成開口1802，如第18圖所繪示。值得注意的是，第18圖，相似於後續的附圖，提供了具有穿過通道區切面的透視示意圖，第18圖自如第17圖所繪示的源極∕汲極部件1602偏移，因此看不見源極∕汲極部件1602。在一些實施例中，如第18圖所描繪，當移除虛置閘極電極1206時，蝕刻製程並未移除虛置閘極介電質1204。在一些實施例中，此蝕刻製程或後續進行的蝕刻製程部分地或完全地移除了虛置閘極介電質1204。（多個）蝕刻製程可以是乾式蝕刻製程、濕式蝕刻製程、或上述之組合。
參見第19圖的示例，通道釋放製程可能導致通道區中犧牲層206的移除，從而形成懸空的多個半導體層208於通道區中，半導體層208彼此之間及∕或鰭片部分202’被空隙所分隔。釋放通道層208的蝕刻製程可為乾式蝕刻製程、濕式蝕刻製程、或上述之組合。通道釋放製程可進一步包含移除通道區中的包覆層602。通道釋放製程可包含蝕刻製程選擇性蝕刻包覆層602的組成物（例如，矽鍺）及∕或犧牲層206，同時對通道層208不進行任何蝕刻或僅進行最小程度的蝕刻。通道層的釋放、虛置閘極結構的移除、以及包覆層602的移除各自提供了裝置200的通道區中的開口1902，如第19圖所繪示。
在一些實施例中，介電鰭片1004並未自不同類型的裝置（例如，n型或p型）鄰近的通道區之間移除，因此，持續提供隔離性於鄰近的不同類型的裝置之間。在一些實施例中，介電鰭片1004同樣未自相同類型的裝置（例如，n型或p型）鄰近的通道區之間移除，而這些裝置的閘極結構的任何互連可以不由閘極電極結構的本身提供，而是由形成於介電鰭片1004上方的金屬化層來提供，如下方所討論。
方法100接著進行至方框120，形成金屬閘極結構於方框118所提供的多個開口中。金屬閘極結構可為完整的裝置200的（多個）功能性閘極。參見第20A圖以及第20B圖的示例，第20A圖以及第20B圖繪示出形成金屬閘極結構2002於方框118所提供的開口1902中。金屬閘極結構2002根據多閘極裝置200的設計需求被配置為達到所需的功能性。每個金屬閘極結構2002包含了閘極介電質2004（例如，高介電常數閘極介電質及∕或諸如氧化矽或氮氧化矽的界面層）以及閘極電極2006（例如，功函數層以及塊（bulk）導電層）。金屬閘極結構2002可包含數個其它的膜層，例如蓋層、界面層、擴散層、阻障層、硬遮罩層、或上述之組合。在一些實施例中，形成金屬閘極結構2002包含沉積閘極介電層2004於通道區上方，其中閘極介電層部分地填充通道層208之間的空隙、以及沉積閘極電極層2006於閘極介電層2004上方，其中閘極電極層填充了通道層208之間的剩餘空隙。
閘極介電質2004包含了高介電常數介電層，其包含了高介電常數介電材料，對金屬閘極結構2002而言，高介電常數介電材料指的是具有大於二氧化矽的介電常數（介電常數≈3.9）的介電材料。例如，高介電常數介電層包含HfO2 、HfSiO、HfSiO4 、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx 、ZrO、ZrO2 、ZrSiO2 、AlO、AlSiO、Al2 O3 、TiO、TiO2 、LaO、LaSiO、Ta2 O3 、Ta2 O5 、Y2 O3 、SrTiO3 、BaZrO、BaTiO3 （BTO）、（Ba, Sr）TiO3 （BST）、Si3 N4 、HfO2 -Al2 O3 合金、其他適合金屬閘極堆疊的合適的高介電常數介電材料、或上述之組合。高介電常數介電層可由任何此處所描述的製程形成，諸如原子層沉積、化學氣相沉積、物理氣相沉積、以氧化為主的沉積製程、其他合適的製程、或上述之組合。例如，使用原子層沉積製程沉積高介電常數介電層。在一些實施例中，原子層沉積製程為順應的沉積製程，使得在多閘極裝置200的各種表面上方，高介電常數介電層的厚度實質上是均勻的（順應的）。在一些實施例中，閘極介電質2004包含了設置界面層於高介電常數介電層與通道層208之間。界面層包含了介電材料，例如SiO2 、HfSiO、SiON、其它包含矽的介電材料、其它合適的介電材料、或上述之組合。界面層可由任何此處所描述的製程形成，諸如熱氧化、化學氧化、原子層沉積、化學氣相沉積、其他合適的製程、或上述之組合。例如，藉由化學氧化製程形成界面層，化學氧化製程將通道層208暴露的表面暴露於氫氟酸中。在一些實施例中，藉由熱氧化製程形成界面層，熱氧化製程將通道層208暴露的表面暴露於氧氣及∕或大氣環境中。在一些實施例中，在形成高介電常數介電層後形成界面層。例如，在一些實施例中，在形成高介電常數介電層後，可將多閘極裝置200置於氧氣及∕或氮氣環境中（例如，一氧化二氮）進行退火。
形成閘極電極2006於閘極介電質2004上方，填充剩餘的閘極開口1902以及包繞通道層208。使得閘極電極2006填充通道層之間剩餘的空隙。閘極電極2006包含導電材料，例如多晶矽、鋁、銅、鈦、鉭、鎢、鉬、鈷、TaN、NiSi、CoSi、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、其它導電材料、或上述之組合。在一些實施例中，閘極電極2006包含功函數層以及塊導電層。功函數層為將導電層調整至具有所需的功函數（例如，n型功函數或p型功函數），而塊導電層為形成導電層於功函數層上方。在一些實施例中，功函數層包含n型功函數材料，諸如鈦、銀、錳、鋯、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、其他合適的n型功函數材料、或上述之組合。在一些實施例中，功函數層包含p型功函數材料，諸如釕、Mo、Al、TiN、TaN、WN、ZrSi2 、MoSi2 、TaSi2 、NiSi2 、WN、其他合適的p型功函數材料、或上述之組合。塊（或填充）導電層包含合適的導電材料，諸如Al、W、Ti、Ta、多晶矽、Cu、金屬合金、其他合適的材料、或上述之組合。閘極電極2006可由任何此處所描述的製程形成，諸如原子層沉積、化學氣相沉積、物理氣相沉積、電鍍、其他合適的製程、或上述之組合。在一實施例中，進行平坦化處理以移除多閘極裝置200的一些多餘的閘極材料。例如，執行化學機械拋光處理使得在化學機械拋光處理後閘極結構2002的頂表面實質上與層間介電層1704的頂表面齊平。
參見第21A圖以及第21B圖的示例，回蝕刻閘極電極2006使得金屬閘極結構2002的頂表面實質上與介電鰭片1004的表面齊平。此留下了設置於金屬閘極電極2006上方的開口2102。介電鰭片1004延伸至不同通道區的金屬閘極結構2002之間。例如，進行回蝕刻製程以凹蝕閘極電極2006直至介電鰭片1004的頂表面上沒有閘極電極2006的材料。
在一些實施例中，自介電鰭片1004的頂表面進一步凹蝕閘極電極2006以及形成一或多層額外的膜層於凹蝕的閘極電極2006上。在一實施例中，設置晶種層於金屬閘極結構上方以及鄰近介電鰭片。晶種層可以是Ti、TiN、TaN、W、Ru、及∕或上述之組合。例示性厚度範圍為大約1奈米至2奈米之間。在一些實施例中，會選擇能提供足夠的厚度以便黏附（adhesion）於上覆層以及提供下方討論的上覆金屬化層具有所需電阻率的厚度。晶種層的沉積製程可包含化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠距電漿化學氣相沉積、電漿增強化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、電漿增強原子層沉積（plasma-enhanced ALD；PEALD）、電鍍、無電電鍍、其他合適的沉積方法、或上述之組合。第30A圖以及第30B圖繪示出形成晶種層2602於閘極電極2006上方且具有與介電鰭片1004鄰接（abut）的側壁，以及繪示出設置晶種層2602於凹蝕的閘極電極2006上。雖然在一些實施例中，如在此所述的，形成第30A圖以及第30B圖的晶種層2602於沉積虛置層2202之前，但在其他實施例中，形成第30A圖以及第30B圖的晶種層2602於形成閘極分隔部件後。
在一些實施例中，進一步自介電鰭片1004的頂表面凹蝕閘極結構以及設置蝕刻停止層於金屬閘極結構上方以及鄰近介電鰭片。蝕刻停止層可以是金屬氮化物、及∕或其他合適的組成物。蝕刻停止層為導電的膜層，以允許閘極結構的互連。蝕刻停止層的沉積製程可包含化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠距電漿化學氣相沉積、電漿增強化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、電漿增強原子層沉積、電鍍、無電電鍍、其他合適的沉積方法、或上述之組合。第31A圖以及第31B圖提供了蝕刻停止層3102於閘極結構2002上方以及鄰近介電鰭片1004的示例。蝕刻停止層3102可於下方討論的在蝕刻溝槽2302時提供閘極結構2002額外的保護。因此，蝕刻停止層3102可選擇具有提供對虛置層2202的蝕刻選擇性的組成。
在進行（多個）回蝕刻製程以及平坦化處理後，鄰近的閘極電極2006可能不在第一通道區（鰭片212）與第二通道區（鄰近的鰭片212）之間延伸。換句話說，閘極結構2002的導電性在鄰近的通道區之間中斷（例如，藉由介電鰭片1004中斷）。因此，在一些實施例中，此時在方法100中，閘極電極2006彼此之間為電性地絕緣。金屬閘極切割或分隔製程可被稱作自對準，因為閘極隔離結構（此處指介電鰭片1004）在鄰近的金屬閘極結構2002之間為對準的，不必在形成金屬閘極結構2002後進行微影製程。介電鰭片1004自對準的位置提供了電性絕緣於裝置中鄰近的主動區之間。
方法100接著進行至方框122，形成虛置材料層於閘極結構上方。在一實施例中，虛置材料層為矽。在其他實施例中，虛置材料包含SiO、SiN、SiC、SiCN、SiON、SiCN、SiOCN、AlO、AlN、AlON、ZrO、ZrN、ZrAlO、HfO、及∕或其他合適的材料。虛置材料可被犧牲且被選擇使其具有合適的蝕刻選擇性，例如當形成如方框124所討論的溝槽時。在一實施例中，虛置層相對於金屬閘極結構2002以及特別是閘極電極2006的材料具有高蝕刻選擇性。虛置材料層可藉由旋轉塗佈、化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠距電漿化學氣相沉積、電漿增強化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、電漿增強原子層沉積、其他合適的沉積方法、或上述之組合。參見第22A圖以及第22B圖的示例，形成虛置層2202。在一些實施例中，在沉積後，執行諸如化學機械拋光的平坦化處理以移除多餘的虛置材料以及提供如第22A圖以及第22B圖所繪示的平坦頂表面。
方法100接著進行至方框124，形成定義出閘極分隔區的複數個溝槽於虛置層中。閘極分隔區為那些被確定為裝置鄰近的閘極結構（例如，鄰近的全繞式閘極裝置）彼此絕緣的部分的區域。在一些實施例中，閘極分隔區為第一類型的裝置（例如，n型場效電晶體）與第二類型的裝置（例如，p型場效電晶體）之間的區域。定義出閘極分隔區的複數個溝槽可藉由提供部件的圖案於虛置層上方來形成。在一些實施例中，提供遮罩元件以定義虛置層上方的開口，也就是之後將蝕刻出複數個溝槽的位置。在一些實施例中，光學微影製程可包含形成光阻層上覆於裝置200以及虛置層2202，以及顯影光阻層以形成包含光阻層的遮罩元件。
根據光阻層所提供的圖案，蝕刻虛置層中的溝槽。參見第23A圖以及第23B圖的示例，形成溝槽2302於虛置層2202中，延伸至介電層1002及∕或介電鰭片1004的頂部。由於虛置層2202以及閘極結構2002的組成，特別是閘極電極2006，以及上述之間的蝕刻選擇性，在一些實施例中，有可能形成溝槽2302並使得實質上沒有金屬閘極結構的材料被蝕刻。在一些實施例中，由於虛置層2202與介電層1002以及兩者之間的蝕刻選擇性，在一些實施例中，有可能形成溝槽2302並使得介電層1002實質上未被蝕刻。蝕刻製程可由乾式蝕刻製程來形成。
方法100接著進行至方框126，以（多個）介電材料填充溝槽以形成閘極分隔部件。填充溝槽的例示性介電材料包含SiO、SiN、SiC、SiCN、SiON、SiCN、SiOCN、AlO、AlN、AlON、ZrO、ZrN、ZrAlO、HfO、及∕或上述之組合。例示性沉積技術包含化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠距電漿化學氣相沉積、電漿增強化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、電漿增強原子層沉積、其他合適的沉積方法、或上述之組合。在沉積後，平坦化處理或其他的回蝕刻製程可移除多餘的材料以形成閘極分隔部件。
參見第24A圖以及第24B圖的示例，形成介電材料於溝槽2302中以形成閘極分隔部件2402。在一些實施例中，閘極分隔部件2402為多膜層元件。介電材料可藉由各種沉積方法來沉積，且執行諸如化學機械拋光以達到實質上的平坦，以提供虛置層2202平坦的頂表面，如第24A圖以及第24B圖所繪示。
在沉積材料於溝槽中之後，移除虛置層的剩餘物。虛置層可藉由合適的選擇性蝕刻製程如乾式蝕刻製程、濕式蝕刻製程、或剝離（strip）製程來移除。如第25A圖以及第25B圖所繪示的示例，隨後移除虛置層2202。在一些實施例中，移除虛置層2202並未傷害（例如，蝕刻）閘極。
方法100接著進行至方框128，形成至少一金屬化層於閘極結構上方。在一些實施例中，形成至少一金屬化層於鄰近的閘極結構上方並延伸於閘極結構之間。換句話說，可沉積（多個）金屬化層於第一裝置的第一閘極結構上方並與其接觸，且延伸金屬化層以設置於第二裝置的第二（相鄰的）閘極結構上方並與其接觸，從而電性連接這兩個閘極結構。在兩個相連的閘極結構之間，（多個）金屬化層延伸於鄰近裝置的主動區之間的介電鰭片上方。由於上方方框126討論過的閘極分隔部件，其他具有閘極分隔部件於其之間的鄰近的閘極結構（例如，鄰近於第一閘極結構另一側的第三閘極結構）也可彼此隔離。換句話說，（多個）金屬化層並未延伸至具有閘極隔離部件的裝置的一些閘極之間，且因此，不提供電性連接於上述的閘極之間。閘極結構的圖案化為連接或絕緣取決於裝置的設計，且是由形成方框124的溝槽的圖案來定義，此圖案提供了閘極分隔部件。
參見第26A圖以及第26B圖的示例，在一實施例中，形成第一導電層，也被稱作晶種層2602，以及金屬化層2604於裝置200上。如第26A圖所繪示，晶種層2602以及金屬化層2604可延伸於一些閘極結構2002之間諸如從標示為2002A的第一閘極結構延伸至標示為2002B的第二閘極結構以及延伸於第三閘極結構2002C與第四閘極結構2002D之間。閘極分隔部件2402穿插於第二閘極結構2002B以及第三閘極結構2002C之間，使得晶種層2602以及金屬化層2604並未延伸於第二閘極結構2002B與第三閘極結構2002C之間。因此，晶種層2602以及金屬化層2604各自具有與閘極隔離部件2402鄰接的終端。同樣，每個閘極結構2002A、2002B、2002C、以及2002D提供了裝置200部分的全繞式閘極裝置的閘極結構。
晶種層2602可包含Ti、TiN、TaN、W、Ru、及∕或上述之組合。例示性的厚度範圍為大約1奈米至2奈米之間。在一些實施例中，會選擇能提供足夠的厚度以便黏附於上覆層以及提供金屬化層堆疊所需電阻率的厚度。金屬化層2604可包含W、Ru、Co、及∕或上述之組合。例示性的厚度範圍為大約2奈米至5奈米之間。在一些實施例中，會選擇能提供足夠的厚度於鄰近的閘極堆疊所需導電性的厚度。晶種層2602及∕或金屬化層2604的沉積製程可包含化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠距電漿化學氣相沉積、電漿增強化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、電漿增強原子層沉積、電鍍、無電電鍍、其他合適的沉積方法、或上述之組合。在一些實施例中，沉積晶種層2602的材料並隨後進行回蝕刻以提供相對應的開口。
在一實施例中，可省略晶種層2602，同時金屬化層2604提供了至少一金屬化層連接至閘極的子集合（subset）。此可以由第29A圖以及第29B圖的裝置200’的實施例來舉例說明。在第29A圖以及第29B圖中的裝置200’的金屬化層2604可實質上近似於上方討論過的裝置200。
方法100接著進行至方框130，形成絕緣層於方框128的（多個）金屬化層上方。例示性的絕緣層材料可包含SiO、SiN、SiC、SiCN、SiON、SiCN、SiOCN、AlO、AlN、AlON、ZrO、ZrN、ZrAlO、HfO、及∕或上述之組合。絕緣材料的沉積可藉由旋轉塗佈、高深寬比製程、化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠距電漿化學氣相沉積、電漿增強化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、電漿增強原子層沉積、及∕或其他合適的方法。在一些實施例中，在沉積後，對絕緣材料進行諸如平坦化處理（例如，化學機械拋光）的回蝕刻以提供實質上與閘極分隔部件共平面的頂表面。參見第27A圖以及第27B圖的示例，形成絕緣層2702於晶種層2602以及金屬化層2604上方且鄰近閘極分隔部件2402。在一些實施例中，絕緣層2702具有與閘極分隔部件2402相同的組成。在其他實施例中，絕緣層2702具有不同於閘極分隔部件2402的組成。
在一實施例中，絕緣層2702可與閘極間隔物鄰接，其中與鄰近層間介電層1704的底部接觸蝕刻停止層1702鄰接。
方法100接著進行至方框132，形成連接至方框128的（多個）金屬化層的接觸元件。參見第28A圖以及第28B圖的示例，形成接觸元件2802以與金屬化層2604交界（interface）。接觸元件2802可提供從形成於裝置200上方的多膜層互連（multilayer interconnect；MLI）至閘極結構2002的電性連接路徑。
多膜層互連電性地耦合各種裝置（例如，多閘極裝置200的p型及∕或n型的電晶體、電阻器、電容器及∕或電感器）及∕或元件（例如，p型電晶體及∕或n型電晶體的的閘極電極及∕或磊晶源極∕汲極部件），使得各種裝置及∕或元件可按照多閘極裝置200的設計需求進行操作。多膜層互連部件通常會包含介電層以及電性導電層（例如，金屬層）的結合以配置形成各種互連結構。配置導電層以形成垂直的互連部件，例如裝置級別的接觸件及∕或導孔，及∕或水平的互連部件，例如導線。垂直的互連部件通常會在多膜層互連的不同膜層（或不同平面）連接水平的互連部件。在操作步驟期間，配置互連部件以提供訊號路徑於裝置及∕或多閘極裝置200的元件之間，及∕或分配訊號（例如，時鐘訊號、電壓訊號及∕或接地訊號）至裝置及∕或多閘極裝置200的元件。
在一些實施例中，首先藉由於絕緣層中蝕刻一個延伸至閘極結構上方的（多個）金屬化層的導孔來形成接觸件。在一些實施例中，導孔是由光學微影製程來定義。微影製程可包含形成阻抗層於絕緣層2702上方，曝光阻抗層至圖案化輻射，以及顯影曝光的阻抗層，從而形成圖案化的阻抗層，其可被使用作蝕刻出延伸通過絕緣層2702以暴露裝置200的（多個）金屬化層的（多個）接觸件開口的遮罩元件，具體來說，至少暴露金屬層2604。蝕刻製程包含乾式蝕刻製程、濕式蝕刻製程、其它蝕刻製程、或上述之組合。之後，填充一或多個電性導電材料於（多個）接觸件開口，諸如鎢、釕、鈷、銅、鋁、銥、鈀、鉑、鎳、其它低電阻率的金屬組成、上述之合金、或上述之組合。（多個）導電材料可以由物理氣相沉積、化學氣相沉積、原子層沉積、電鍍、無電電鍍、其他合適的沉積製程、或上述之組合製程來沉積。在一些實施例中，接觸元件2802包含塊層（也被稱作導電插塞（plug））。在一些實施例中，接觸元件2802包含設置阻障層、黏附層、及∕或其他合適的膜層於塊層以及絕緣層2702之間。在一些實施例中，阻障層、黏附層、及∕或其他合適的膜層包含鈦、鈦合金（例如，TiN）、鉭、鉭合金（例如，TaN）、其它合適的組成、或上述之組合。多膜層互連的額外部件可與接觸元件2802的頂表面交界，包含如金屬線或導電導孔。
方法100接著進行至方框134，進行額外的製造步驟。額外的製造步驟可包含形成上方討論過的多膜層互連的其它元件，包括連接至源極∕汲極部件（例如磊晶源極∕汲極部件1602）的接觸件。連接至源極∕汲極部件的接觸件可類似於接觸元件2802，包含進行微影製程，其包括形成阻抗層於對應的層間介電層1704與接觸蝕刻停止層1702上方，曝光阻抗層至圖案化輻射，以及顯影曝光的阻抗層，從而形成圖案化的阻抗層，其可被使用作蝕刻出通過層間介電層1704以及接觸蝕刻停止層1702的（多個）源極∕汲極接觸件開口以暴露磊晶源極∕汲極部件1602的遮罩元件。蝕刻製程包含乾式蝕刻製程、濕式蝕刻製程、其他蝕刻製程、或上述之組合。之後，填充一或多個電性導電材料於（多個）源極∕汲極接觸件開口，諸如鎢、釕、鈷、銅、鋁、銥、鈀、鉑、鎳、其它低電阻率的金屬組成、上述之合金、或上述之組合。（多個）導電材料可以由物理氣相沉積、化學氣相沉積、原子層沉積、電鍍、無電電鍍、其他合適的沉積製程、或上述之組合製程來沉積。在一些實施例中，源極∕汲極接觸件包含塊層（也被稱作導電插塞）以及更包含設置阻障層、黏附層、及∕或其他合適的膜層於塊層與層間介電層1704及∕或接觸蝕刻停止層1702之間。在一些實施例中，阻障層、黏附層、及∕或其他合適的膜層包含鈦、鈦合金（例如，TiN）、鉭、鉭合金（例如，TaN）、其它合適的組成、或上述之組合。
因此，多閘極裝置200包含了複數個閘極結構2002。在一些實施例中，閘極結構2002A以及閘極結構2002B為第一裝置類型（例如，n型場效電晶體）。在一些實施例中，閘極結構2002C以及閘極結構2002D為第二裝置類型（例如，p型場效電晶體）。
再參見第29A圖以及第29B圖，第29A圖以及第29B圖繪示出實質上近似於裝置200但卻僅具有金屬化層2604且省略晶種層2602的裝置200’。 再參見第30A圖以及第30B圖，第30A圖以及第30B圖繪示出實質上近似於裝置200但僅具有設置於閘極結構2002上方而未延伸至閘極結構之間的金屬化層2604以及晶種層2602的裝置200’’。 再參見第31A圖以及第31B圖，第31A圖以及第31B圖繪示出實質上近似於裝置200但具有金屬化層2604、晶種層2602、以及蝕刻停止層3102的裝置200’’’。蝕刻停止層已於上方進行詳細的討論。
現在參見第32圖，第32圖繪示出晶種層2602、金屬化層2604、閘極結構2002、閘極分隔部件2402、以及絕緣層2702之間的界面的詳細示意圖。如第32圖所繪示，此處繪示出金屬化層2604，至少一金屬化層的終端為圓化，使得金屬化層的終端具有曲線的末端表面。特別是，與閘極分隔部件2402鄰接的金屬化層2604的末端為圓化∕曲線化。在一些實施例中，此曲線末端是由在鄰近的閘極分隔部件2402的開口之中（參見第25A、25B圖）的金屬化層2604的形成來提供。同時，第32圖繪示出裝置200的實施例的圓化，此圓化可同樣應用至裝置200’、200’’、 及∕或200’’’的一或多層金屬化層。
根據上方的描述，可以看出本發明實施例所描述的多閘極裝置提供了數個優點於常規的多閘極裝置。應理解的是，並非全部的優點皆已必然在此討論，也非所有實施例都需要具備特定的優點，且其他實施例可提供不同的優點。其中一優點為此處描述的製造製程相對於使用常規的金屬閘極切割技術製造的電晶體，本揭露能減少電晶體的尺寸大小及∕或金屬閘極的所占大小，從而允許更高的電晶體封裝密度並增加積體電路的圖案密度。再者，一些實施例在提供鄰近的閘極結構分隔性的同時，提供了避免對諸如閘極電極的功函數材料的閘極結構造成傷害。藉由在沉積連接至鄰近的閘極結構的金屬化層之前提供分隔性，亦即〝切割〞，相較之下可避免對閘極的傷害，例如，透過不切割金屬閘極結構上方的金屬化層，可能會具有受限的蝕刻選擇性。
本發明實施例提供了許多不同的實施例。例示性的裝置包含了一種裝置，包括基板；第一閘極結構，包繞設置於基板上方的通道層；第二閘極結構，包繞設置於基板上方的另一通道層；以及介電鰭片結構，形成於淺溝槽隔離部件上方。至少一金屬化層，形成於第一閘極結構、介電鰭片結構、以及第二閘極結構上，且自第一閘極結構毗鄰地（contiguously）延伸至第二閘極結構。
在進一步的實施例中，至少一金屬化層包括晶種層以及第一金屬層。晶種層包括鈦（Ti）、氮化鈦（TiN）、氮化鉭（TaN）、或鎢（W）中的至少一種。在一些實施例中，晶種層的側壁與介電鰭片結構交界。在一實施例中，至少一金屬化層與介電鰭片結構的頂表面物理地交界。介電鰭片結構的頂表面為高介電常數介電材料。在一實施例中，第三閘極結構，透過第二介電鰭片與第二閘極結構分隔。閘極分隔部件設置於第二介電鰭片上方。在一些實施例中，至少一金屬化層與閘極分隔部件的側壁鄰接。在進一步的實施例中，至少一金屬化層的末端與閘極分隔部件的側壁鄰接，且末端包括曲線表面。
在本文討論的另一實施例中提供一種裝置，包括第一通道層，設置於基板上方的多個第一源極∕汲極部件之間；第一金屬閘極，圍繞第一通道層；第二通道層，設置於基板上方的多個第二源極∕汲極部件之間；第二金屬閘極，圍繞第二通道層；介電鰭片，設置於第一金屬閘極與第二金屬閘極之間且分隔第一金屬閘極與第二金屬閘極；導電層的第一部份，形成於第一金屬閘極上方；導電層的第二部份，形成於第二金屬閘極上方。裝置更包括隔離層，於導電層的第一部份與導電層的第二部分之間以及介電鰭片上方，其中導電層的第一部份或導電層的第二部分的至少其一包括圓化終端與隔離層鄰接。
在進一步的實施例中，裝置包括隔離層與介電鰭片的頂表面交界。在一實施例中，蝕刻停止層，設置於導電層的第一部份與第一金屬閘極之間。在一實施例中，晶種層穿插於導電層的第一部份與第一金屬閘極之間。在一些實施例中，晶種層的頂表面低於介電鰭片的頂表面。
在本文討論的另一更廣泛的實施例中提供一種方法包括形成第一全繞式閘極裝置的第一閘極結構、第一源極結構以及第一汲極結構於基板上方。此方法繼續包括形成第二全繞式閘極裝置的第二閘極結構、第二源極結構以及第二汲極結構於基板上方，其中介電鰭片設置於第一閘極結構與第二閘極結構之間。沉積虛置層於第一閘極結構、第二閘極結構、以及介電鰭片上方。圖案化虛置層以形成溝槽於介電鰭片上方的虛置層之中。以介電材料填充溝槽以形成介電部件。此方法繼續於填充溝槽後移除圖案化的虛置層。沉積至少一導電層，其具有第一部份位於第一閘極結構上方與第二部分位於第二閘極結構上方。介電部件穿插於第一部份與第二部分之間。
在進一步的實施例中，方法包括沉積絕緣材料於導電層的第一部分與第二部分上方。在一實施例中，方法包括形成導電導孔連接至導電層的第二部分。在一實施例中，方法包括圖案化虛置層以形成溝槽包括選擇性蝕刻虛置層的材料，而實質上不蝕刻第一閘極結構或第二閘極結構。此方法可進一步提供沉積至少一導電層包括沉積晶種層以及上覆金屬層。在一實施例中，方法包括沉積至少一導電層包括沉積至少一導電層的導電材料，其具有圓化終端且與介電部件鄰接。
以上概述數個實施例之特徵，以使本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解，可輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且可在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
200:半導體裝置 202:基板 202’:部分基板 204:半導體層堆疊 206:犧牲層 208:通道層 210:硬遮罩層 210A:氧化矽層 210B:氮化矽層 212:鰭片結構 214:溝槽 216:氧化物襯層 218:矽襯層 402:隔離層 602:包覆層 702:第一介電層 802:氧化物層 902:開口 1002:介電材料 1004:介電鰭片 1102:開口 1202:虛置閘極結構 1204:虛置閘極介電質 1206:虛置閘極電極 1208:硬遮罩 1208A:第一遮罩層 1208B:第二遮罩層 1302:閘極間隔物 1304:源極∕汲極凹槽∕溝槽 1402:開口 1502:內間隔物 1602:磊晶源極∕汲極部件 1602A:磊晶源極∕汲極部件 1602B:磊晶源極∕汲極部件 1702:介電層 1704:介電層 1802:開口 2002:金屬閘極結構 2002A:第一閘極結構 2002B:第二閘極結構 2002C:第三閘極結構 2002D:第四閘極結構 2004:閘極介電質 2006:閘極電極 2102:開口 2202:虛置層 2302:溝槽 2402:閘極分隔部件 2602:晶種層 2604:金屬化層 2702:絕緣層 2802:接觸元件 3102:蝕刻停止層
由以下的詳細敘述配合所附圖式，可最好地理解本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用於說明。事實上，可任意地放大或縮小各種元件的尺寸，以清楚地表現出本發明實施例之特徵。 第1圖是根據本發明實施例的各種面向，繪示出製造多閘極裝置的方法流程圖。 第2、3、4、5、6、7、8、9、10、11、12、13、14、15、16、17、18、19、20A、21A、22A、23A、24A、25A、26A、27A圖以及第28A圖是根據本發明實施例的各種面向，部分或完整地繪示出於各種製造階段（諸如與第1圖中的方法相關的製造階段）的多閘極裝置的局部透視示意圖。 第20B、21B、22B、23B、24B、25B、26B、27B圖以及第28B圖是根據本發明實施例的各種面向，部分或完整地繪示出於各種製造階段（諸如與第1圖中的方法相關的製造階段）的多閘極裝置的局部剖面示意圖。 第29A圖以及第29B圖是根據本發明實施例的各種面向所進行的製造，部分或完整地繪示出第二多閘極裝置的另一實施例的局部透視示意圖以及剖面示意圖。 第30A圖以及第30B圖是根據本發明實施例的各種面向所進行的製造，部分或完整地繪示出第三多閘極裝置的另一實施例的局部透視示意圖以及剖面示意圖。 第31A圖以及第31B圖是根據本發明實施例的各種面向所進行的製造，部分或完整地繪示出第四多閘極裝置的另一實施例的局部透視示意圖以及剖面示意圖。 第32圖是根據本發明實施例的一或多種面向，繪示出多閘極裝置的金屬化層之詳細的局部剖面示意圖。
200:半導體裝置
202:基板
202’:部分基板
208:通道層
402:隔離層
802:氧化物層
1002:介電材料
1004:介電鰭片
1302:閘極間隔物
1702:介電層
1704:介電層
2002A:第一閘極結構
2002B:第二閘極結構
2002C:第三閘極結構
2002D:第四閘極結構
2402:閘極分隔部件
2602:晶種層
2604:金屬化層
2702:絕緣層
2802:接觸元件

Claims (20)

  1. 一種積體電路裝置，包括： 一基板； 一第一閘極結構，包繞該基板上方的一通道層； 一第二閘極結構，包繞該基板上方的另一通道層； 一介電鰭片結構，形成於一淺溝槽隔離（shallow trench isolation；STI）部件上方，其中該介電鰭片結構位於該第一閘極結構與該第二閘極結構之間；以及 至少一金屬化層，於該第一閘極結構、該介電鰭片結構、以及該第二閘極結構上，且自該第一閘極結構毗鄰地（contiguously）延伸至該第二閘極結構。
  2. 如請求項1之積體電路裝置，其中該至少一金屬化層包括一晶種層以及一第一金屬層。
  3. 如請求項2之積體電路裝置，其中該晶種層包括鈦（Ti）、氮化鈦（TiN）、氮化鉭（TaN）、或鎢（W）中的至少一種。
  4. 如請求項3之積體電路裝置，其中該晶種層的一側壁與該介電鰭片結構交界(interface)。
  5. 如請求項1之積體電路裝置，其中該至少一金屬化層與該介電鰭片結構的一頂表面物理地交界。
  6. 如請求項5之積體電路裝置，其中該介電鰭片結構的該頂表面為一高介電常數介電材料。
  7. 如請求項1之積體電路裝置，更包括： 一第三閘極結構，透過一第二介電鰭片與該第二閘極結構分隔，其中一閘極分隔部件設置於該第二介電鰭片上方。
  8. 如請求項7之積體電路裝置，其中該至少一金屬化層與該閘極分隔部件的一側壁鄰接（abut）。
  9. 如請求項8之積體電路裝置，其中該至少一金屬化層的一末端與該閘極分隔部件的該側壁鄰接，且該末端包括一曲線表面。
  10. 一種積體電路裝置，包括： 一第一通道層，設置於一基板上方的多個第一源極∕汲極部件之間； 一第一金屬閘極，圍繞該第一通道層； 一第二通道層，設置於該基板上方的多個第二源極∕汲極部件之間； 一第二金屬閘極，圍繞該第二通道層； 一介電鰭片，設置於該第一金屬閘極與該第二金屬閘極之間且分隔該第一金屬閘極與該第二金屬閘極； 一導電層的一第一部份，於該第一金屬閘極上方； 該導電層的一第二部份，於該第二金屬閘極上方；以及 一隔離層，於該導電層的該第一部份與該導電層的該第二部分之間以及該介電鰭片上方，其中該導電層的該第一部份或該導電層的該第二部分的至少其一包括一圓化終端與該隔離層鄰接。
  11. 如請求項10之積體電路裝置，其中該隔離層與該介電鰭片的一頂表面交界。
  12. 如請求項10之積體電路裝置，更包括：一蝕刻停止層，於該導電層的該第一部份與該第一金屬閘極之間。
  13. 如請求項10之積體電路裝置，其中一晶種層穿插於該導電層的該第一部份與該第一金屬閘極之間。
  14. 如請求項13之積體電路裝置，其中該晶種層的一頂表面低於該介電鰭片的一頂表面。
  15. 一種積體電路裝置的製造方法，包括： 形成一第一全繞式閘極（gate all around；GAA）裝置的一第一閘極結構、一第一源極結構以及一第一汲極結構於一基板上方； 形成一第二全繞式閘極裝置的一第二閘極結構、一第二源極結構以及一第二汲極結構於該基板上方，其中一介電鰭片設置於該第一閘極結構與該第二閘極結構之間； 沉積一虛置層於該第一閘極結構、該第二閘極結構、以及該介電鰭片上方； 圖案化該虛置層以形成一溝槽於該介電鰭片上方的該虛置層之中； 以一介電材料填充該溝槽以形成一介電部件； 於填充該溝槽後移除圖案化的該虛置層；以及 沉積至少一導電層，其具有一第一部份位於該第一閘極結構上方與一第二部分位於該第二閘極結構上方，其中該介電部件穿插於該第一部份與該第二部分之間。
  16. 如請求項15之積體電路裝置的製造方法，更包括： 沉積一絕緣材料於該導電層的該第一部分與該第二部分上方。
  17. 如請求項15之積體電路裝置的製造方法，更包括： 形成一導電導孔連接至該導電層的該第二部分。
  18. 如請求項15之積體電路裝置的製造方法，其中圖案化該虛置層以形成該溝槽包括選擇性蝕刻該虛置層的材料，而實質上不蝕刻該第一閘極結構或該第二閘極結構。
  19. 如請求項15之積體電路裝置的製造方法，其中沉積該至少一導電層包括沉積一晶種層以及一上覆金屬層。
  20. 如請求項15之積體電路裝置的製造方法，其中沉積該至少一導電層包括沉積該至少一導電層的導電材料，其具有圓化終端且與該介電部件鄰接。
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