CN1206726C - 半导体器件的制造方法 - Google Patents
半导体器件的制造方法 Download PDFInfo
- Publication number
- CN1206726C CN1206726C CNB008026181A CN00802618A CN1206726C CN 1206726 C CN1206726 C CN 1206726C CN B008026181 A CNB008026181 A CN B008026181A CN 00802618 A CN00802618 A CN 00802618A CN 1206726 C CN1206726 C CN 1206726C
- Authority
- CN
- China
- Prior art keywords
- semiconductor wafer
- diaphragm seal
- groove
- semiconductor device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 122
- 238000000034 method Methods 0.000 title claims description 25
- 238000005520 cutting process Methods 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000007789 sealing Methods 0.000 claims description 13
- 238000004299 exfoliation Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 57
- 239000010703 silicon Substances 0.000 abstract description 57
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 45
- 239000000758 substrate Substances 0.000 abstract description 9
- 230000003321 amplification Effects 0.000 description 21
- 238000003199 nucleic acid amplification method Methods 0.000 description 21
- 150000003376 silicon Chemical class 0.000 description 15
- 239000012634 fragment Substances 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 238000002507 cathodic stripping potentiometry Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Pressure Sensors (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP321416/1999 | 1999-11-11 | ||
JP32141699A JP3455762B2 (ja) | 1999-11-11 | 1999-11-11 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1337065A CN1337065A (zh) | 2002-02-20 |
CN1206726C true CN1206726C (zh) | 2005-06-15 |
Family
ID=18132313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB008026181A Expired - Lifetime CN1206726C (zh) | 1999-11-11 | 2000-10-31 | 半导体器件的制造方法 |
Country Status (9)
Country | Link |
---|---|
US (1) | US6607970B1 (zh) |
EP (1) | EP1145310A1 (zh) |
JP (1) | JP3455762B2 (zh) |
KR (1) | KR100434974B1 (zh) |
CN (1) | CN1206726C (zh) |
AU (1) | AU7964700A (zh) |
CA (1) | CA2356938C (zh) |
TW (1) | TW484194B (zh) |
WO (1) | WO2001035461A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101388367B (zh) * | 2007-09-13 | 2011-04-20 | 海华科技股份有限公司 | 晶圆级封装方法及其封装结构 |
CN101244613B (zh) * | 2007-02-16 | 2012-02-22 | 探微科技股份有限公司 | 保护晶片正面结构及进行晶片切割的方法 |
Families Citing this family (85)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6506681B2 (en) * | 2000-12-06 | 2003-01-14 | Micron Technology, Inc. | Thin flip—chip method |
JP2002373958A (ja) * | 2001-06-15 | 2002-12-26 | Casio Micronics Co Ltd | 半導体チップの実装構造及び半導体チップの実装方法 |
US6686225B2 (en) * | 2001-07-27 | 2004-02-03 | Texas Instruments Incorporated | Method of separating semiconductor dies from a wafer |
DE10137184B4 (de) * | 2001-07-31 | 2007-09-06 | Infineon Technologies Ag | Verfahren zur Herstellung eines elektronischen Bauteils mit einem Kuststoffgehäuse und elektronisches Bauteil |
JP2003059865A (ja) * | 2001-08-20 | 2003-02-28 | Towa Corp | 切断装置及び切断方法 |
EP1289010A1 (en) * | 2001-08-29 | 2003-03-05 | United Test Center Inc. | Semiconductor device without use of chip carrier and method of making the same |
US6818475B2 (en) * | 2001-10-22 | 2004-11-16 | Wen-Kun Yang | Wafer level package and the process of the same |
JP3706573B2 (ja) * | 2001-11-22 | 2005-10-12 | 株式会社ルネサステクノロジ | 半導体パッケージ及び半導体パッケージの製造方法 |
DE10202881B4 (de) * | 2002-01-25 | 2007-09-20 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleiterchips mit einer Chipkantenschutzschicht, insondere für Wafer Level Packaging Chips |
TW577160B (en) | 2002-02-04 | 2004-02-21 | Casio Computer Co Ltd | Semiconductor device and manufacturing method thereof |
US6908784B1 (en) | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
US6794273B2 (en) * | 2002-05-24 | 2004-09-21 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
CN1287435C (zh) * | 2002-06-27 | 2006-11-29 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
AU2003253425C1 (en) | 2002-08-09 | 2006-06-15 | Casio Computer Co., Ltd. | Semiconductor device and method of manufacturing the same |
US6903442B2 (en) * | 2002-08-29 | 2005-06-07 | Micron Technology, Inc. | Semiconductor component having backside pin contacts |
US6649445B1 (en) * | 2002-09-11 | 2003-11-18 | Motorola, Inc. | Wafer coating and singulation method |
AU2003291199A1 (en) * | 2002-12-09 | 2004-06-30 | Advanced Interconnect Technologies Limited | Package having exposed integrated circuit device |
US6881610B2 (en) * | 2003-01-02 | 2005-04-19 | Intel Corporation | Method and apparatus for preparing a plurality of dice in wafers |
JP3844467B2 (ja) * | 2003-01-08 | 2006-11-15 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
JP2004221125A (ja) * | 2003-01-09 | 2004-08-05 | Sharp Corp | 半導体装置及びその製造方法 |
US7510908B1 (en) | 2003-02-20 | 2009-03-31 | National Semiconductor Corporation | Method to dispense light blocking material for wafer level CSP |
DE10333841B4 (de) * | 2003-07-24 | 2007-05-10 | Infineon Technologies Ag | Verfahren zur Herstellung eines Nutzens mit in Zeilen und Spalten angeordneten Halbleiterbauteilpositionen und Verfahren zur Herstellung eines Halbleiterbauteils |
FR2871291B1 (fr) * | 2004-06-02 | 2006-12-08 | Tracit Technologies | Procede de transfert de plaques |
JP3830497B2 (ja) * | 2004-06-11 | 2006-10-04 | シャープ株式会社 | 半導体ウエハの製造方法及び半導体装置の製造方法 |
JP4165467B2 (ja) * | 2004-07-12 | 2008-10-15 | セイコーエプソン株式会社 | ダイシングシート、半導体装置の製造方法 |
WO2006008795A1 (ja) * | 2004-07-16 | 2006-01-26 | Shinko Electric Industries Co., Ltd. | 半導体装置の製造方法 |
DE102005015036B4 (de) * | 2004-07-19 | 2008-08-28 | Qimonda Ag | Verfahren zur Montage eines Chips auf einer Unterlage |
US7591958B2 (en) * | 2004-09-14 | 2009-09-22 | Stmicroelectronics Sa | Thin glass chip for an electronic component and manufacturing method |
WO2006059589A1 (ja) * | 2004-11-30 | 2006-06-08 | Kyushu Institute Of Technology | パッケージングされた積層型半導体装置及びその製造方法 |
JP4103896B2 (ja) * | 2005-03-16 | 2008-06-18 | ヤマハ株式会社 | 半導体装置の製造方法および半導体装置 |
KR100738730B1 (ko) | 2005-03-16 | 2007-07-12 | 야마하 가부시키가이샤 | 반도체 장치의 제조방법 및 반도체 장치 |
US7238258B2 (en) * | 2005-04-22 | 2007-07-03 | Stats Chippac Ltd. | System for peeling semiconductor chips from tape |
US7468545B2 (en) * | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
JP4497112B2 (ja) * | 2005-05-18 | 2010-07-07 | ヤマハ株式会社 | 半導体装置の製造方法 |
US7582556B2 (en) | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
TWI303870B (en) * | 2005-12-30 | 2008-12-01 | Advanced Semiconductor Eng | Structure and mtehod for packaging a chip |
JP5165207B2 (ja) | 2006-03-29 | 2013-03-21 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置の製造方法 |
JP2007266421A (ja) * | 2006-03-29 | 2007-10-11 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP4193897B2 (ja) * | 2006-05-19 | 2008-12-10 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
US7569422B2 (en) | 2006-08-11 | 2009-08-04 | Megica Corporation | Chip package and method for fabricating the same |
US20080079150A1 (en) * | 2006-09-28 | 2008-04-03 | Juergen Simon | Die arrangement and method for producing a die arrangement |
JP5028988B2 (ja) | 2006-12-13 | 2012-09-19 | ヤマハ株式会社 | 半導体装置の製造方法 |
US20080153265A1 (en) * | 2006-12-21 | 2008-06-26 | Texas Instruments Incorporated | Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a Wafer |
TWI364793B (en) * | 2007-05-08 | 2012-05-21 | Mutual Pak Technology Co Ltd | Package structure for integrated circuit device and method of the same |
US7838424B2 (en) * | 2007-07-03 | 2010-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching |
US7662669B2 (en) * | 2007-07-24 | 2010-02-16 | Northrop Grumman Space & Mission Systems Corp. | Method of exposing circuit lateral interconnect contacts by wafer saw |
US7777339B2 (en) * | 2007-07-30 | 2010-08-17 | International Business Machines Corporation | Semiconductor chips with reduced stress from underfill at edge of chip |
US20090079072A1 (en) * | 2007-09-21 | 2009-03-26 | Casio Computer Co., Ltd. | Semiconductor device having low dielectric insulating film and manufacturing method of the same |
JP2009117450A (ja) | 2007-11-02 | 2009-05-28 | Rohm Co Ltd | モジュールおよびその製造方法 |
US20090160053A1 (en) * | 2007-12-19 | 2009-06-25 | Infineon Technologies Ag | Method of manufacturing a semiconducotor device |
US7824962B2 (en) * | 2008-01-29 | 2010-11-02 | Infineon Technologies Ag | Method of integrated circuit fabrication |
US7968378B2 (en) * | 2008-02-06 | 2011-06-28 | Infineon Technologies Ag | Electronic device |
DE102008014927A1 (de) * | 2008-02-22 | 2009-08-27 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung einer Mehrzahl von strahlungsemittierenden Bauelementen und strahlungsemittierendes Bauelement |
JP4538764B2 (ja) | 2008-07-24 | 2010-09-08 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
US8580657B2 (en) * | 2008-09-23 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protecting sidewalls of semiconductor chips using insulation films |
US20100078811A1 (en) * | 2008-09-30 | 2010-04-01 | Infineon Technologies Ag | Method of producing semiconductor devices |
JP5297139B2 (ja) * | 2008-10-09 | 2013-09-25 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US8138014B2 (en) | 2010-01-29 | 2012-03-20 | Stats Chippac, Ltd. | Method of forming thin profile WLCSP with vertical interconnect over package footprint |
US8236613B2 (en) * | 2010-05-24 | 2012-08-07 | Alpha & Omega Semiconductor Inc. | Wafer level chip scale package method using clip array |
CN102403236B (zh) * | 2010-09-07 | 2015-03-04 | 万国半导体(开曼)股份有限公司 | 芯片外露的半导体器件及其生产方法 |
CN101982872A (zh) * | 2010-10-30 | 2011-03-02 | 强茂电子(无锡)有限公司 | 沟槽式二极管芯片的制造方法 |
CN102543767B (zh) * | 2010-12-07 | 2015-04-08 | 万国半导体(开曼)股份有限公司 | 一种在晶圆级封装的塑封工序中避免晶圆破损的方法 |
CN102709198A (zh) * | 2011-03-28 | 2012-10-03 | 华东科技股份有限公司 | 防止基板周边外露的模封阵列处理方法 |
US20120273935A1 (en) * | 2011-04-29 | 2012-11-01 | Stefan Martens | Semiconductor Device and Method of Making a Semiconductor Device |
US8652941B2 (en) * | 2011-12-08 | 2014-02-18 | International Business Machines Corporation | Wafer dicing employing edge region underfill removal |
US8685761B2 (en) * | 2012-02-02 | 2014-04-01 | Harris Corporation | Method for making a redistributed electronic device using a transferrable redistribution layer |
US9202754B2 (en) * | 2012-04-23 | 2015-12-01 | Seagate Technology Llc | Laser submounts formed using etching process |
US9275924B2 (en) | 2012-08-14 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package having a recess filled with a molding compound |
US9406632B2 (en) | 2012-08-14 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package including a substrate with a stepped sidewall structure |
US9799590B2 (en) | 2013-03-13 | 2017-10-24 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package |
US9318386B2 (en) * | 2013-07-17 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer alignment methods in die sawing process |
EP2950338B1 (en) * | 2014-05-28 | 2019-04-24 | ams AG | Dicing method for wafer-level packaging |
CN105328804B (zh) * | 2014-06-20 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | 一种晶圆的切割方法 |
US9390993B2 (en) | 2014-08-15 | 2016-07-12 | Broadcom Corporation | Semiconductor border protection sealant |
US10163709B2 (en) | 2015-02-13 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
CN104658925B (zh) * | 2015-03-02 | 2017-04-19 | 山东盛品电子技术有限公司 | 一种封装管壳产品在切单后避免型腔清洗的方法 |
JP6598723B2 (ja) * | 2016-04-06 | 2019-10-30 | 株式会社ディスコ | パッケージウェーハの製造方法 |
JP6636377B2 (ja) * | 2016-04-08 | 2020-01-29 | 株式会社ディスコ | パッケージウェーハの製造方法及びデバイスチップの製造方法 |
CN107611091A (zh) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体(江阴)有限公司 | 晶圆级芯片封装结构及其制备方法 |
JP6816046B2 (ja) * | 2018-02-06 | 2021-01-20 | アオイ電子株式会社 | 半導体装置の製造方法 |
CN111354701A (zh) * | 2018-12-20 | 2020-06-30 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
JP2020136600A (ja) * | 2019-02-25 | 2020-08-31 | 東レ株式会社 | 半導体または電子部品製造用粘着フィルムならびに半導体または電子部品の製造方法 |
CN110098131A (zh) * | 2019-04-18 | 2019-08-06 | 电子科技大学 | 一种功率mos型器件与集成电路晶圆级重构封装方法 |
JP2021048205A (ja) | 2019-09-17 | 2021-03-25 | キオクシア株式会社 | 半導体装置の製造方法 |
JP7433020B2 (ja) * | 2019-11-07 | 2024-02-19 | ローム株式会社 | チップ部品およびその製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5155068A (en) * | 1989-08-31 | 1992-10-13 | Sharp Kabushiki Kaisha | Method for manufacturing an IC module for an IC card whereby an IC device and surrounding encapsulant are thinned by material removal |
JPH0870081A (ja) * | 1994-08-29 | 1996-03-12 | Nippondenso Co Ltd | Icパッケージおよびその製造方法 |
DE69527017T2 (de) * | 1994-10-03 | 2003-01-02 | Kabushiki Kaisha Toshiba, Kawasaki | Verfahren zur Herstellung einer Halbleiterpackung integral mit Halbleiterchip |
EP1189271A3 (en) * | 1996-07-12 | 2003-07-16 | Fujitsu Limited | Wiring boards and mounting of semiconductor devices thereon |
JP3351706B2 (ja) * | 1997-05-14 | 2002-12-03 | 株式会社東芝 | 半導体装置およびその製造方法 |
JPH1140520A (ja) * | 1997-07-23 | 1999-02-12 | Toshiba Corp | ウェーハの分割方法及び半導体装置の製造方法 |
JP3526731B2 (ja) * | 1997-10-08 | 2004-05-17 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
US6441487B2 (en) * | 1997-10-20 | 2002-08-27 | Flip Chip Technologies, L.L.C. | Chip scale package using large ductile solder balls |
JPH11224890A (ja) * | 1997-12-01 | 1999-08-17 | Mitsui High Tec Inc | 半導体装置およびその製造方法 |
JPH11224980A (ja) | 1998-02-05 | 1999-08-17 | Oki Electric Ind Co Ltd | 半田バンプ形成方法及び半田バンプ形成装置 |
JP3420703B2 (ja) * | 1998-07-16 | 2003-06-30 | 株式会社東芝 | 半導体装置の製造方法 |
JP3516592B2 (ja) * | 1998-08-18 | 2004-04-05 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
-
1999
- 1999-11-11 JP JP32141699A patent/JP3455762B2/ja not_active Expired - Fee Related
-
2000
- 2000-10-31 CA CA002356938A patent/CA2356938C/en not_active Expired - Fee Related
- 2000-10-31 CN CNB008026181A patent/CN1206726C/zh not_active Expired - Lifetime
- 2000-10-31 WO PCT/JP2000/007659 patent/WO2001035461A1/en not_active Application Discontinuation
- 2000-10-31 EP EP00970234A patent/EP1145310A1/en not_active Withdrawn
- 2000-10-31 AU AU79647/00A patent/AU7964700A/en not_active Abandoned
- 2000-10-31 KR KR10-2001-7008239A patent/KR100434974B1/ko not_active IP Right Cessation
- 2000-11-01 US US09/704,156 patent/US6607970B1/en not_active Expired - Lifetime
- 2000-11-03 TW TW089123189A patent/TW484194B/zh active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101244613B (zh) * | 2007-02-16 | 2012-02-22 | 探微科技股份有限公司 | 保护晶片正面结构及进行晶片切割的方法 |
CN101388367B (zh) * | 2007-09-13 | 2011-04-20 | 海华科技股份有限公司 | 晶圆级封装方法及其封装结构 |
Also Published As
Publication number | Publication date |
---|---|
CA2356938A1 (en) | 2001-05-17 |
US6607970B1 (en) | 2003-08-19 |
WO2001035461A1 (en) | 2001-05-17 |
KR100434974B1 (ko) | 2004-06-09 |
TW484194B (en) | 2002-04-21 |
AU7964700A (en) | 2001-06-06 |
JP2001144121A (ja) | 2001-05-25 |
EP1145310A1 (en) | 2001-10-17 |
CN1337065A (zh) | 2002-02-20 |
CA2356938C (en) | 2006-03-21 |
KR20010089726A (ko) | 2001-10-08 |
JP3455762B2 (ja) | 2003-10-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1206726C (zh) | 半导体器件的制造方法 | |
US11848237B2 (en) | Composite wafer, semiconductor device and electronic component | |
CN102176433B (zh) | 具有低介电性绝缘膜的半导体器件及其制造方法 | |
CN1186810C (zh) | 半导体器件的芯片规模表面安装封装及其制造方法 | |
KR100609806B1 (ko) | 반도체 장치의 제조 방법 | |
CN1110842C (zh) | 具有间断绝缘区的半导体ic器件及其制造方法 | |
CN1320617C (zh) | 半导体器件的芯片规模表面安装封装及其制造方法 | |
US20050095750A1 (en) | Wafer level transparent packaging | |
CN1581428A (zh) | 半导体装置及其制造方法 | |
CN1697127A (zh) | 制造半导体器件的方法 | |
CN1633705A (zh) | 半导体装置及其制造方法 | |
KR20040092435A (ko) | 반도체 장치 및 그 제조 방법 | |
CN1758433A (zh) | 半导体器件及其制造方法 | |
CN1716601A (zh) | 半导体器件和半导体晶片及其制造方法 | |
CN1825590A (zh) | 半导体器件及其制造方法 | |
CN1819166A (zh) | 封装结构 | |
US20100081257A1 (en) | Dice by grind for back surface metallized dies | |
WO2013095527A1 (en) | Electrostatic discharge compliant patterned adhesive tape | |
CN1675766A (zh) | 电引线架的制造方法,表面安装的半导体器件的制造方法和引线架带 | |
CN1755927A (zh) | 半导体器件及其制造方法 | |
CN101226889A (zh) | 重配置线路结构及其制造方法 | |
CN1729562A (zh) | 电子器件及其制造方法 | |
TWI229370B (en) | Semiconductor device | |
CN1063580C (zh) | 制造具有多层互连的半导体器件的方法 | |
EP4141914A1 (en) | Leadframe with varying thicknesses and method of manufacturing semiconductor packages |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
C10 | Entry into substantive examination | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: ZHAOZHUANGWEI CO., LTD. Free format text: FORMER OWNER: CASIO COMPUTER CO., LTD. Effective date: 20120316 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20120316 Address after: Tokyo, Japan Patentee after: Zhaozhuang Micro Co.,Ltd. Address before: Tokyo, Japan Patentee before: CASIO COMPUTER Co.,Ltd. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20170405 Address after: Kagawa Patentee after: AOI ELECTRONICS Co.,Ltd. Address before: Kanagawa Patentee before: Zhao Tan Jing Co.,Ltd. Effective date of registration: 20170405 Address after: Kanagawa Patentee after: Zhao Tan Jing Co.,Ltd. Address before: Tokyo, Japan Patentee before: Zhaozhuang Micro Co.,Ltd. |
|
CX01 | Expiry of patent term |
Granted publication date: 20050615 |
|
CX01 | Expiry of patent term |