CN101226889A - 重配置线路结构及其制造方法 - Google Patents
重配置线路结构及其制造方法 Download PDFInfo
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- CN101226889A CN101226889A CNA2007100009542A CN200710000954A CN101226889A CN 101226889 A CN101226889 A CN 101226889A CN A2007100009542 A CNA2007100009542 A CN A2007100009542A CN 200710000954 A CN200710000954 A CN 200710000954A CN 101226889 A CN101226889 A CN 101226889A
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- Wire Bonding (AREA)
Abstract
一种重配置线路结构的制造方法。提供一基板,且此基板具有多个接垫与一保护层,其中保护层具有多个第一开口,且各第一开口暴露出相对应的接垫的一部分。在保护层上形成一第一图案化光阻层,其中第一图案化光阻层具有多个第二开口,且各第二开口暴露出第一接垫的一部分。在开口内形成多个第一凸块。在基板上方形成一球底金属材料层,以覆盖第一图案化光阻层与第一凸块。在第一凸块上方的球底金属材料层上形成多个导线层。以导线层为遮罩,图案化此球底金属材料层,以形成多个球底金属层。因此,此种重配置线路结构能够承受较大的冲击能量。
Description
技术领域
本发明是有关于一种线路结构,且特别是有关于一种重配置线路结构及其制造方法。
背景技术
近年来,随着电子产业的蓬勃发展,带动了半导体的广泛应用,因此,为因应电子产业的需求,许多关于半导体制程的技术亦相当迅速地发展中。半导体制程粗分为前段制程与后段制程,前段制程包括半导体基底(substrate)的形成例如硅单晶成长及磊晶成长(epitaxial growth),与半导体元件制造例如金氧半导体(metal oxide semiconductor,MOS)制程、多重金属内连线(metal interconnection)等。此外,后段制程则是构装制程(packaging process),而构装的目的在于保护晶片,避免湿气侵入晶片内及避免受到外力破坏,且构装体的对外接点可以使晶片与外界电子元件电性连接。
承上所述,构装形式约略可分为打线制程(wire bond,WB)、贴带自动接合(tape automatic bonding,TAB)制程与覆晶(flip chip,FC)制程。其中,打线制程的技术发展完整,在各种电子构装(electronic package)中均占有重要的地位。打线制程主要是利用一打线导线(wire)连接晶片的接点(connection point)与承载器(carrier)的接点,借此将晶片的电子讯号传输到外界,其中承载器例如是构装基板或导线架(lead frame)。一般而言,晶片的接点通常与承载器的接点相距不远,以利于打线制程的进行。然而,有时因为承载器的接点的位置改变,或者因应不同产品需求,造成晶片接点与承载器接点之间的距离过远,造成打线导线的强度(strength)不佳,或者造成打线导线的长度过长而有电性上的疑虑。此时,必需使用重配置制程(redistribution),以改变晶片上对外接点的线路布局。值得一提的是,打线制程需辅助一接合力(Bonding force),故接垫的下方区域承受相当大的冲击能量。因此,电子元件通常不会配置于接垫下方,以避免冲击能量对于晶片造成损害。如此一来,此种配置方式将增加晶片面积。
发明内容
本发明提供一种重配置线路结构的制造方法,以降低冲击能量对于晶片造成损害可能性。
本发明提供一种重配置线路结构,其具有较佳的可靠度。
本发明提出一种重配置线路结构的制造方法,其包括下列步骤。首先,提供一基板,且此基板具有多个接垫与一保护层,其中保护层具有多个第一开口,且各第一开口暴露出相对应的接垫的一部分。在保护层上形成一第一图案化光阻层,其中第一图案化光阻层具有多个第二开口,且各第二开口暴露出第一接垫的一部分。在开口内形成多个第一凸块。在基板上方形成一第一球底金属材料层,以覆盖第一图案化光阻层与第一凸块。在第一凸块上方的第一球底金属材料层上形成多个导线层。以导线层为遮罩,图案化此第一球底金属材料层,以形成多个第一球底金属层。
在本发明的一实施例中,形成导线层的步骤更包括在第一球底金属材料层上形成一第二图案化光阻层,且第二图案化光阻层具有多个第三开口,其分别暴露出第一凸块上方的第一球底金属材料层。在第二开口内形成导线层。移除第二图案化光阻层。
在本发明的一实施例中,在形成导线层之后,重配置线路结构的制造方法更包括在导线层上形成多个第二凸块。
在本发明的一实施例中,形成上述第二凸块的步骤包括在第一球底金属材料层与部分导线层上形成一第三图案化光阻层,且第三图案化光阻层具有多个第四开口,其分别暴露出部分导线层。在第四开口内形成第二凸块。移除第三图案化光阻层。
在本发明的一实施例中,第二凸块的材质包括金。
在本发明的一实施例中,导线层的材质包括铜。
在本发明的一实施例中,第一凸块的材质包括铝。
在本发明的一实施例中,接垫与第一凸块的材质不同时,在形成第一图案化光阻层之前,此重配置线路结构的制造方法更包括在保护层上形成一第二球底金属层,以覆盖第一开口所暴露出的接垫。
本发明提出一种重配置线路结构,其适于配置于一基板上,且此基板具有一接垫与一保护层,其中保护层具有一开口,且开口暴露出接垫的一部分。此重配置线路结构包括一第一凸块、一图案化光阻层、一第一球底金属层与一导线层,其中第一凸块配置于开口内,并与接垫电性连接。图案化光阻层配置于保护层上,并暴露出第一凸块。第一球底金属层配置于第一凸块与部分图案化光阻层上而导线层配置于第一球底金属层上。
在本发明的一实施例中,第一凸块的面积小于开口的面积。
在本发明的一实施例中,导线层的面积大于第一凸块的面积。
在本发明的一实施例中,重配置线路结构更包括一第二凸块,其配置于导线层上。
在本发明的一实施例中,第二凸块的材质包括金。
在本发明的一实施例中,导线层的材质包括铜。
在本发明的一实施例中,第一凸块的材质包括铝。
在本发明的一实施例中,多层凸块结构更包括一第二球底金属层,其配置于第一开口内,并位于接垫与第一凸块之间。
基于上述,本发明在导线层下方配置一图案化光阻层,而此图案化光阻层可作为缓冲层,因此采用此种重配置线路结构的晶片能够接受较大的冲击能量。换言之,此种采用此种重配置线路结构的晶片具有较佳的可靠度。
为让本发明的上述特征和优点能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下。
附图说明
图1A至图1C为本发明的第一实施例的一种重配置线路结构的制造方法的示意图。
图2A至图2D为本发明的第二实施例的一种重配置线路结构的制造方法的示意图。
图3为本发明的第三实施例的一种重配置线路结构的示意图。
图4为本发明的第四实施例的一种重配置线路结构的示意图。
110:基板 120:接垫
130:保护层 130a:第一开口
210:第一图案化光阻层 210a:第二开口
220:第一凸块 230:第一球底金属材料层
232:第一球底金属层 240:导线层
250:第二凸块 262:第二球底金属层
310:第二图案化光阻层 310a:第三开口
320:第三图案化光阻层 320a:第四开口
具体实施方式
第一实施例
图1A至图1C为本发明的第一实施例的一种重配置线路结构的制造方法的示意图。请先参考图1A,本实施例的重配置线路结构的制造方法包括下列步骤。首先,提供一基板110,而基板110具有多个接垫120与一保护层130,其中保护层130具有多个第一开口130a,且各第一开口130a分别暴露出相对应的接垫120的一部分。值得注意的是,为了便于说明,本实施例的第一开130a与接垫120均仅绘示一个。此外,此基板110可以是晶圆或是其他承载器,而接垫120的材质可以是铝、铜或是其他金属。
请继续参考图1A,在保护层130上形成一第一图案化光阻层210,其中第一图案化光阻层210具有多个第二开口210a,且各第二开口210a暴露出相对应的接垫120的一部分。值得注意的是,第二开口210a小于接垫120以及第一开口230a。然后,在第二开口210a内形成第一凸块220。换言之,在保护层130所暴露出的接垫120上形成多个第一凸块220。此外,形成第一凸块220的方法可以是电镀制程。在本实施例中,第一凸块220为铝凸块。然而,在其他实施例中,第一凸块220也可以是其他金属材质。
请继续参考图1A,在基板110上方形成一球底金属材料层230,以覆盖第一图案化光阻层210与第一凸块220。此外,形成球底金属材料层230的方法可以是溅镀制程或是其他物理气相沉积制程。
请参考图1B,在球底金属材料层230上形成一第二图案化光阻层310,且第二图案化光阻层310具有多个第三开口310a,其分别暴露出第一凸块220上方的球底金属材料层230。然后,在这些第三开口310a形成多个导线层240。此外,形成导线层240的方法可以是电镀制程。在本实施例中,导线层240为铜。然而,在其他实施例中,导线层240也可以是其他金属。
请参考图1B与图1C,然后,移除第二图案化光阻层310,以暴露出球底金属材料层230。然后,以导线层240为遮罩进行一蚀刻制程,移除部分球底金属材料层230,以形成球底金属层232。至此,大致完成本实施例的重配置线路结构的制造流程。此外,在形成球底金属层232之后,也可以对于基板110进行一切割制程,以形成多个晶片结构(未绘示)。以下将就此重配置线路结构的细部结构进行说明。
请继续参考图1C,此重配置线路结构适于配置于一基板110上。此基板110具有一接垫120与一保护层130,其中保护层130具有一第一开口130a,其暴露出接垫120的一部分。此外,基板110可以是晶片或晶圆。此重配置线路结构包括一第一图案化光阻层210、第一凸块220、一球底金属层232与一导线层240,其中第一凸块220配置于第一开口130a内,并与接垫120电性连接。此外,第一凸块220的底面积小于第一开口130a的底面积。第一图案化光阻层210配置于保护层130上,并暴露出第一凸块220。换言之,第一图案化光阻层210具有一第二开口210a,其暴露出部分接垫120,而第一凸块220配置于第二开口210a内。球底金属层232配置于第一凸块220与部分第一图案化光阻层210上,而导线层240配置于球底金属层232上。另外,导线层240的面积大于第一凸块220的面积。
由于部分导线层240与球底金属层232下方配置有第一图案化光阻层210,因此对于此重配置线路结构进行打线制程时,第一图案化光阻层210可以作为缓冲层,以降低第一图案化光阻层210下方的线路结构受到损伤的可能性。
第二实施例
图2A至图2D为本发明的第二实施例的一种重配置线路结构的制造方法的示意图。请先参考图2A,本实施例的重配置线路结构的制造方法与上述实施例相似,主要都是依序形成第一图案化光阻层210、第一凸块220与球底金属材料层230。
请参考图2B,图2B所绘示的内容与图1B相似,主要都是在形成球底金属材料层230之后,依序形成第二图案化光阻层310与形成导线层240。
请参考图2C,在形成导线层240之后,移除第二图案化光阻层310。然后,在球底金属材料层230与部分导线层240上形成一第三图案化光阻层320,且第三图案化光阻层320具有多个第四开口320a,其分别暴露出部分导线层240。接着,在第四开口320内形成第二凸块250。此外,第二凸块250的材质可以是金或其他金属,而形成第二凸块250的方法可以是电镀制程。再来,移除第三图案化光阻层320。
请参考图2C与图2D,以导线层240为遮罩进行一蚀刻制程,移除部分球底金属材料层230,以形成球底金属层232。至此,大致完成本实施例的重配置线路结构的制造流程。此外,在形成球底金属层232之后,也可以对于基板110进行一切割制程,以形成多个晶片结构(未绘示)。以下将就此重配置线路结构的细部结构进行说明。
请继续参考图2D,本实施例的重配置线路结构与第一实施例相似,其不同之处在于:本实施例的重配置线路结构更包括多个第二凸块250,其配置导线层240上,因此采用此种重配置线路结构的晶片将可以应用于采用覆晶接合技术的晶片封装体。此外,由于第二凸块250形成于平坦的导线层240上,因此此种第二凸块250具有平坦的顶面。再者,当采用此种重配置线路结构的晶片进行接合时,由于导线层240下方配置有第一图案化光阻层210,因此应力集中(stress concentration)所产生的破坏的可能性可以降低。
第三实施例
图3为本发明的第三实施例的一种重配置线路结构的示意图。请参考图3,本实施例与第一实施例相似,其不同之处在于:当接垫120与第一凸块220的材质为不同时,重配置线路结构更包括一第二球底金属层262,其配置于第一开口130a内,并位于接垫120与第一凸块220之间。举例而言,当接垫120的材质为铝,而第一凸块220的材质不是铝时,在接垫120与第一凸块220之间需配置第二球底金属层262。此外,形成第二球底金属层262的步骤可以是先在保护层130上形成一第二球底金属材料层(未绘示),以覆盖第一开口130a所暴露出的接垫120。另外,形成第二球底金属材料层的方法可以是溅镀制程、物理气相沉积制程或化学气相沉积制程。然后,图案化此第二球底金属材料层,以形成第二球底金属层262。
第四实施例
图4为本发明的第四实施例的一种重配置线路结构的示意图。请参考图4,本实施例与第二实施例相似,其不同之处在于:当接垫120与第一凸块220的材质为不同时,重配置线路结构更包括一第二球底金属层262,其配置于第一开口130a内,并位于接垫120与第一凸块220之间。举例而言,当接垫120的材质为铝,而第一凸块220的材质不是铝时,在接垫120与第一凸块220之间需配置第二球底金属层262。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视所附的权利要求所界定者为准。
Claims (16)
1.一种重配置线路结构的制造方法,其特征在于其包括以下步骤:
提供一基板,该基板具有多个接垫与一保护层,其中该保护层具有多个第一开口,且各第一开口暴露出相对应的该接垫的一部分;
在该保护层上形成一第一图案化光阻层,其中该第一图案化光阻层具有多个第二开口,且各第二开口暴露出该第一接垫的一部分;
在上述开口内形成多个第一凸块;
在该基板上方形成一第一球底金属材料层,以覆盖该第一图案化光阻层与上述第一凸块;
在上述第一凸块上方的该第一球底金属材料层上形成多个导线层;以及
以上述导线层为遮罩,图案化该第一球底金属材料层,以形成多个第一球底金属层。
2.根据权利要求1所述的重配置线路结构的制造方法,其特征在于其中形成导线层的步骤包括:
在该第一球底金属材料层上形成一第二图案化光阻层,且该第二图案化光阻层具有多个第三开口,分别暴露出上述第一凸块上方的该第一球底金属材料层;
在上述第二开口内形成上述导线层;以及
移除该第二图案化光阻层。
3.根据权利要求1所述的重配置线路结构的制造方法,其特征在于其中在形成导线层之后,更包括在上述导线层上形成多个第二凸块。
4.根据权利要求3所述的重配置线路结构的制造方法,其特征在于其中形成上述第二凸块的步骤包括:
在该球底金属材料层与部分上述导线层上形成一第三图案化光阻层,且该第三图案化光阻层具有多个第四开口,分别暴露出部分上述导线层;
在上述第四开口内形成上述第二凸块;以及
移除该第三图案化光阻层。
5.根据权利要求3所述的重配置线路结构的制造方法,其特征在于其中上述第二凸块的材质包括金。
6.根据权利要求1所述的重配置线路结构的制造方法,其特征在于其中上述导线层的材质包括铜。
7.根据权利要求1所述的重配置线路结构的制造方法,其特征在于其中上述第一凸块的材质包括铝。
8.根据权利要求1所述的重配置线路结构的制造方法,其特征在于其中上述接垫与上述第一凸块的材质不同时,在形成该第一图案化光阻层之前,更包括在该保护层上形成一第二球底金属层,以覆盖上述第一开口所暴露出的上述接垫。
9.一种重配置线路结构,适于配置于一基板上,该基板具有一接垫与一保护层,其中该保护层具有一开口,且该开口暴露出该接垫的一部分,其特征在于该重配置线路结构包括:
一第一凸块,配置于该开口内,并与该接垫电性连接;
一图案化光阻层,配置于该保护层上,并暴露出该第一凸块;
一球底金属层,配置于该第一凸块与部分该图案化光阻层上;以及
一导线层,配置于该球底金属层上。
10.根据权利要求9所述的重配置线路结构,其特征在于其中该第一凸块的面积小于该开口的面积。
11.根据权利要求9所述的重配置线路结构,其特征在于其中该导线层的面积大于该第一凸块的面积。
12.根据权利要求9所述的重配置线路结构,其特征在于更包括一第二凸块,配置于该导线层上。
13.根据权利要求12所述的重配置线路结构,其特征在于其中上述第二凸块的材质包括金。
14.根据权利要求9所述的重配置线路结构,其特征在于其中上述导线层的材质包括铜。
15.根据权利要求9所述的重配置线路结构,其特征在于其中上述第一凸块的材质包括铝。
16.根据权利要求9所述的重配置线路结构,其特征在于更包括一第二球底金属层,配置于该第一开口内,并位于该接垫与该第一凸块之间。
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CN200710000954A CN101226889B (zh) | 2007-01-15 | 2007-01-15 | 重配置线路结构及其制造方法 |
US11/693,734 US7498251B2 (en) | 2007-01-15 | 2007-03-30 | Redistribution circuit structure |
US12/352,592 US7648902B2 (en) | 2007-01-15 | 2009-01-12 | Manufacturing method of redistribution circuit structure |
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CN200710000954A CN101226889B (zh) | 2007-01-15 | 2007-01-15 | 重配置线路结构及其制造方法 |
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CN101226889B (zh) * | 2007-01-15 | 2010-05-19 | 百慕达南茂科技股份有限公司 | 重配置线路结构及其制造方法 |
US7858438B2 (en) * | 2007-06-13 | 2010-12-28 | Himax Technologies Limited | Semiconductor device, chip package and method of fabricating the same |
US7994045B1 (en) * | 2009-09-08 | 2011-08-09 | Amkor Technology, Inc. | Bumped chip package fabrication method and structure |
SG11201601295TA (en) | 2013-08-28 | 2016-03-30 | Inst Of Technical Education | Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device |
US20170365567A1 (en) * | 2016-06-20 | 2017-12-21 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
US10504862B2 (en) * | 2017-10-25 | 2019-12-10 | Avago Technologies International Sales Pte. Limited | Redistribution metal and under bump metal interconnect structures and method |
KR102542573B1 (ko) | 2018-09-13 | 2023-06-13 | 삼성전자주식회사 | 재배선 기판, 이의 제조 방법, 및 이를 포함하는 반도체 패키지 |
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KR100313706B1 (ko) * | 1999-09-29 | 2001-11-26 | 윤종용 | 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법 |
KR100306842B1 (ko) * | 1999-09-30 | 2001-11-02 | 윤종용 | 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법 |
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US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
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US20080169558A1 (en) | 2008-07-17 |
US7648902B2 (en) | 2010-01-19 |
US7498251B2 (en) | 2009-03-03 |
CN101226889B (zh) | 2010-05-19 |
US20090130839A1 (en) | 2009-05-21 |
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