SG11201601295TA - Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device - Google Patents
Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor deviceInfo
- Publication number
- SG11201601295TA SG11201601295TA SG11201601295TA SG11201601295TA SG11201601295TA SG 11201601295T A SG11201601295T A SG 11201601295TA SG 11201601295T A SG11201601295T A SG 11201601295TA SG 11201601295T A SG11201601295T A SG 11201601295TA SG 11201601295T A SG11201601295T A SG 11201601295TA
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor device
- multilayer structure
- forming
- multilayer
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 2
Classifications
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/SG2013/000374 WO2015030670A1 (en) | 2013-08-28 | 2013-08-28 | Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device |
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SG11201601295TA true SG11201601295TA (en) | 2016-03-30 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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SG11201601295TA SG11201601295TA (en) | 2013-08-28 | 2013-08-28 | Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device |
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US (1) | US9806013B2 (en) |
SG (1) | SG11201601295TA (en) |
WO (1) | WO2015030670A1 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160343646A1 (en) * | 2015-05-21 | 2016-11-24 | Qualcomm Incorporated | High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) package |
US10297563B2 (en) * | 2016-09-15 | 2019-05-21 | Intel Corporation | Copper seed layer and nickel-tin microbump structures |
US10332856B2 (en) * | 2017-11-08 | 2019-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of fabricating the same |
KR102028715B1 (en) * | 2017-12-19 | 2019-10-07 | 삼성전자주식회사 | Semiconductor package |
JP7259530B2 (en) * | 2019-05-08 | 2023-04-18 | 住友電気工業株式会社 | Surface emitting laser, electronic device, manufacturing method of surface emitting laser |
CN113140521B (en) * | 2020-01-20 | 2022-11-22 | 上海艾为电子技术股份有限公司 | Wafer level packaging method and wafer level packaging structure |
US11621229B2 (en) * | 2020-10-15 | 2023-04-04 | Advanced Semiconductor Engineering, Inc. | Wiring structure and method for manufacturing the same |
FR3118285B1 (en) * | 2020-12-22 | 2023-01-13 | Commissariat Energie Atomique | Semi-buried electrical connection insert rod device |
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JPS61258453A (en) * | 1985-05-13 | 1986-11-15 | Toshiba Corp | Manufacture of semiconductor device |
US5229257A (en) * | 1990-04-30 | 1993-07-20 | International Business Machines Corporation | Process for forming multi-level coplanar conductor/insulator films employing photosensitive polymide polymer compositions |
TW488052B (en) * | 2001-05-16 | 2002-05-21 | Ind Tech Res Inst | Manufacture process of bumps of double layers or more |
US6911386B1 (en) | 2002-06-21 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated process for fuse opening and passivation process for CU/LOW-K IMD |
US7307013B2 (en) * | 2004-06-30 | 2007-12-11 | Sandisk 3D Llc | Nonselective unpatterned etchback to expose buried patterned features |
JP2007109825A (en) | 2005-10-12 | 2007-04-26 | Nec Corp | Multilayer wiring board, semiconductor device using the same, and their manufacturing methods |
KR100886706B1 (en) | 2006-12-29 | 2009-03-04 | 주식회사 하이닉스반도체 | Stack package and manufacturing method of the same |
CN101226889B (en) * | 2007-01-15 | 2010-05-19 | 百慕达南茂科技股份有限公司 | Reconfiguration line structure and manufacturing method thereof |
KR100889553B1 (en) | 2007-07-23 | 2009-03-23 | 주식회사 동부하이텍 | System in package and method for fabricating the same |
WO2009050207A1 (en) * | 2007-10-15 | 2009-04-23 | Interuniversitair Microelectronica Centrum Vzw | Method for producing electrical interconnects and devices made thereof |
US7989953B1 (en) * | 2007-12-28 | 2011-08-02 | Volterra Semiconductor Corporation | Flip chip power switch with under bump metallization stack |
US8058163B2 (en) | 2008-08-07 | 2011-11-15 | Flipchip International, Llc | Enhanced reliability for semiconductor devices using dielectric encasement |
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2013
- 2013-08-28 US US14/914,775 patent/US9806013B2/en not_active Expired - Fee Related
- 2013-08-28 SG SG11201601295TA patent/SG11201601295TA/en unknown
- 2013-08-28 WO PCT/SG2013/000374 patent/WO2015030670A1/en active Application Filing
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US20160211206A1 (en) | 2016-07-21 |
WO2015030670A1 (en) | 2015-03-05 |
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