CN1729562A - 电子器件及其制造方法 - Google Patents

电子器件及其制造方法 Download PDF

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Publication number
CN1729562A
CN1729562A CNA2003801071095A CN200380107109A CN1729562A CN 1729562 A CN1729562 A CN 1729562A CN A2003801071095 A CNA2003801071095 A CN A2003801071095A CN 200380107109 A CN200380107109 A CN 200380107109A CN 1729562 A CN1729562 A CN 1729562A
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layer
paillon foil
substrate
patterned
conductive layer
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CN100365792C (zh
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J·W·维坎普
M·A·德桑伯
E·C·E·范格伦斯文
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Abstract

本发明的器件包含半导体元件、第一连接元件、第一图形化导电层和第二图形化导电层。该器件进一步设有封装，封装除了是为衬底一部分的第一导电层之外所有部分。该器件可以适当地制造，因为第二导电层以预图形化的形式设有可渗透隔离层作为箔片。

Description

电子器件及其制造方法
本发明涉及电子器件的制造方法，包括如下步骤：
在具有第一导电层的衬底的第一侧上提供包括半导体元件和第一连接元件的元件，从而使所述元件中的至少两个和第一层内相应的导体电接触，该至少两个元件中的一个为第一连接元件；
在所述元件的任一侧上应用第二导电层，从而使至少该两个元件和该第二层电接触；
应用钝化材料，其形成元件的封装；以及
分离衬底、封装和第二导电层的组件，从而形成该电子器件。
本发明还涉及具有第一侧和对立的第二侧的电子器件，第二侧设有具有位于第一和第二导电材料层之间的第一和第二连接区域的半导体元件，该第一和第二导电材料层分别位于第一和第二侧上，这些层通过至少第一连接元件被电互连，在所述层内根据期望图形定义导体，半导体元件经由连接区域和至少多个所述导体电连接，所述器件在第一侧上设有用于外部接触的接触面，所述接触面与第一层内导体的至少部分电连接，所述元件至少基本上被钝化材料封装所封装。
本发明进一步涉及箔片(foil)。
未公开的专利IB 02/02305(PHNL010398)中描述了该方法和该器件。在所述应用中，半导体元件为在第一侧上设有多个连接区域并第二侧上设有一个连接区域的晶体管或者稍微更加复杂的元件，这些区域用于使用导电胶(即热沉或接触)形成导电与/或导热连接。包含连接元件的该器件具有的优点为外部接触可位于单侧上，这种情况下为第一侧，尽管连接区域位于对立侧上。连接元件为例如硅或铜体。
在已知的方法中，衬底和第二导电层分别采用导电板的形式。元件设在第二导电板上并使用导电胶粘附。所述元件设有第一侧上的凸起。接下来，第一导电板设在所述凸起上。接着，从该器件的侧边缘提供隔离材料(这种情况下为所谓的底层填充材料(underfill material))并且还固化该隔离材料。为了在凸起和第一导电板之间建立导电连接，优选地执行回火步骤(temperature step)。随后使用掩模图形化第一板。
从侧边缘提供隔离材料在实际中证实是不利的。如果同时制造大量器件，用隔离材料封装所有元件需要相当长的时间。此外存在元件和凸起未被完全封装的巨大风险，这会导致机械应力和失效。而且，材料选择限于由底层填充材料形成的组。
因此本发明的第一目标是提供开篇段落中所描述的类型的方法，采用该方法可以容易地提供隔离材料，且该方法还使得可以从衬底开始制造该器件且用于外部接触的所有接触面位于一侧上。如下实现该第一目标：
第二层被图形化并包含互连的连接导体和导体；
第二层作为箔片的一部分提供，由此将至少该两个元件和连接导体电接触；以及
从半导体元件第二侧穿过箔片提供钝化材料。
在根据本发明的方法中，使用箔片代替平板形式的第二导电层。所述箔片包含已经为图形化形式的第二导电层，但由于另外的箔片部分的连接功能，可以整体地提供该第二导电层。所述另外的箔片部分包括例如电隔离层，该隔离层可以或者不可以被分离或者图形化。借助该“可渗透的”箔片，可以从半导体元件的第二侧提供隔离材料。因此，更大的表面可用于提供隔离材料，这导致更快速的工艺以及更小的未完全封装的风险。
根据本发明的方法的一个优点在于锯切路径内没有第二导电层。在锯切路径中存在导电层，尤其是铜，使锯切工艺复杂且对所用的锯的使用寿命有负面影响。因此，优选采用光刻方法除去铜。然而，由于装配厂中的实际条件，装配工艺之后的光刻步骤也不是理想的。在根据本发明的方法中，基本上不存在该问题。
另一个优点在于第二导电层可包含用于增加功能的附加图形。可以提供例如线圈、耦合器、挡板、和微波传输带。
尤其优选的优点在于第二导电层可包含更多的图形。这使得要制造的模块能够包含大量元件，而不需要所有元件都通过第二导电层被互连。该方法的另外优点在于可以使用用于封装的各种隔离材料。其例子包括玻璃环氧化物(glass epoxide)、丙烯酸酯、聚酰亚胺，也包括可以固化成玻璃的溶胶-凝胶材料。可以使用各种涂敷技术执行通过该箔片提供隔离材料。其例子包括注模、喷射、旋涂或网模(web)涂敷等。
在根据本发明的第一实施例中，箔片包括可分离的层，在半导体元件的第二侧上提供箔片之后该层被清除。该箔片可以被清除，因为第二图形化层由元件，特别是其第二侧上的连接装置支撑。熟知的连接装置包含金属凸起和导电胶。本实施例的一个优点在于第二图形化层基本上可以用作另外元件的衬底。优选在应用隔离材料之前提供这些元件。可以根据另外的元件的质量调整第二导电层的厚度。然而优选地，该厚度受到限制，约为100nm至50μm。元件的例子为半导体元件、传感器、热沉、无源元件等。
在第二实施例中，箔片包含图形化的电隔离层，以使得第二图形化层面向元件的方式提供箔片。隔离层优选嵌入在隔离材料内。因此要求隔离层和隔离材料结合得足够牢固。此外，隔离层必须可以承受为了固化封装的隔离材料并重新熔化焊料与/或金属所进行的热处理。此外，隔离材料不应该对器件的操作有负面影响。实际上，使用特别是可以从Norton商业获得的干焊料抗蚀剂和诸如聚酰亚胺和苯并环丁烯(benzocyclobutene)的结构材料，已经获得令人满意的结果。
在第三实施例中，箔片包含电隔离纱网(gauze)，以使得第二图形化层面向元件的方式提供箔片。已经发现，该纱网的强度足以将第二导电层保持在一起。同时，借助纱网的开口结构，对封装的机械和热稳定性以及器件的操作没有负面影响。纱网由例如尼龙材料或玻璃纤维制成，基本上具有足以承受所述热处理的热稳定性。然而，如果纱网会在该热处理期间熔化，那么封装可以容易地应付这一点。同时，纱网的机械功能已经变得多余。当然可以在可分离的层上提供纱网以简化处理。
原则上，衬底的选择完全自由并只取决于特定的应用和装配时的条件。在该连接中，优选利用已经在第一层内确定连接导体的衬底。该衬底具有如下优点：提供隔离材料之后，可以省去上述方法中应用的光刻步骤。该衬底的第一实例为例如引线框。这仍然具有如下缺点：衬底的承载功能和连接功能没有分离，使得必须切割该金属引线框以分离衬底和封装的组件。该衬底的第二实例为具有第一导电层的箔片，该箔片是可分离的。该衬底的第三实例为具有第一导电层的载体层。
尤其优选衬底包含牺牲层，在提供钝化材料后至少部分清除该牺牲层。牺牲层基本上为临时载体层。和箔片相比，牺牲层的优点在于其尺寸稳定性和机械稳定性。同时，锯切路径上可以没有第一导电层。可以通过蚀刻、抛光、或暴露在紫外辐射下进行清除。
使用牺牲层提供了两个附加的可能性。首先，通过在提供隔离材料之前选择性清除牺牲层，第一导电层可以锚定在封装中。这使得衬底和封装之间更好的粘附。特别地，导电层在远离第一侧的侧上连接到基本上根据和导电层相同的图形进行图形化的层。作为牺牲层的中间层或者子层的图形在平行于该层的平面内具有较小的直径，引起所述锚定。
牺牲层的第二个优点在于，在背离衬底第一侧的衬底第二侧上可以容易地形成用于外部接触的接触面。特别地，穿过隔离载体层的通路可以省略。
如未公开申请EP 02076425.4(PHNL 020318)中所述的采用铝牺牲层和铜导电层，以及如未公开申请EP 02076426.2(PHNL 020327)和EP 02079544.9(PHNL 021100)中所述的采用Cu-Al-Cu的三层或多层概念，获得了尤其有利的结果。
此外，优选在具有凸起的第一侧上以及具有导电胶的第二侧上提供元件。这种情况下，通过在衬底和元件之间应用诸如丙烯酸酯层的溶解性层，可以获得极佳的元件封装，从未公开申请EP 02077228.1(PHNL020471)已知该方法本身。
在另一个修改中，钝化材料也封装第二图形化层，且衬底包含在背离第一侧的第二侧上的用于外部接触的接触面。根据本发明的器件的一个重要优点在于，用于外部接触的所有接触面位于单一侧上。其结果为，如果将排列成球网格或者岛网格阵列的凸起等用于外部接触，接触面可以出现在衬底内或者在第二导电层之内或之上。通过在衬底内确定接触面，第二导电层可以被完全封装。通过这种方式，无需提供附加的层，就可获得只在一侧上具有向外突出的导电部分的器件。而且，通过在衬底内定位接触面可以最小化第二导电层中图形的数目。这提高了提供隔离材料的容易度。
本发明的第二目标是提供开篇段落中所描述的类型的电子器件，该电子器件可以采用根据本发明的方法进行制造，且其设有内部导体用于将第二侧上的连接区域和接触面连接。
如下实现该目标：
第二导电层被图形化并设有用于半导体元件的第二连接区域的第一连接导体和用于该连接元件的第二连接导体，这些连接导体被互连；以及
除了所述元件，封装还基本上封装第二导电层。
由于第二导电层的所述封装，获得所要求的器件。
对于半导体元件，可以利用所有类型的元件。基本上，可以区别至少三种类别的元件；第一种元件包括在元件的两侧上均具有连接区域的垂直半导体元件。这些元件尤其为例如二极管和双极晶体管。通过可以是导电体或球以及半导体元件和无源元件的连接元件，导体被反馈到接触面。
第二种半导体元件包括这样的半导体元件，其中与第二层的连接用于散热与/或接地。其例子为，尤其是放大器和集成电路(IC)。该方法尤其适合于制造IC的HVQFN封装。这种情况下，半导体元件的后侧，即半导体本体，放置在第一层中定义为热沉的导体上。这时的连接元件为体或优选金属或焊料凸起。随后，半导体元件上的连接区域连接到第二层内的导体。经由连接元件，这些被反馈到器件第一侧上的接触面。这仅仅通过使用箔片而变得可能。毕竟，箔片具有有利的影响，第二层可以制成薄层，即大约0.1至10μm。由此，图形的分辨率由此可以提高到具有几十个连接区域的集成电路所要求的水平。
从US 6,300,161已知一种参照器件本身。然而在所述文件中，第二层出现在分离的载体层上，也称为插入层。该载体层没有被钝化材料封装。与该已知器件相比，根据本发明的器件的优点主要在于紧凑性，尤其是厚度方面，其次为装配的容易性。和传统HVQFN装配技术相比的另外优点在于分离工艺不需要锯切HVQFN引线框。如果利用牺牲层作为衬底的一部分，可以获得另一个优点，即仅在制造的非常后期(例如测试之后)最终分离单个器件。在已经分离封装之后，通过清除该牺牲层(例如通过在适当浴器中蚀刻)进行所述分离。
第三种半导体元件包括只与第一层连接的半导体元件。此外，在第二层中与/或作为连接元件，存在提供附加功能的元件。特别地，这里使用的半导体元件是集成电路。提供附加功能的元件为例如保护二极管、退耦电容器、以及在第二层内定义的线圈、电阻器或者传感器。
连接元件优选为硅或铜体。或者，其可以是金属或者焊料球，特别是如果该半导体元件厚度小。然而连接元件本身也可以是半导体元件或者无源元件。
使用根据本发明的方法可以以有利的方式获得该器件，而且该器件优选具有与前述的衬底、第二导电层内图形等等相关的一个或多个特殊特征。
第三个目标是提供用于本发明的箔片。通过包含图形化的电隔离载体层和图形化的导电层的箔片实现该目标。在导电层中，根据期望图形提供连接导体、互连连接等。该载体层为例如纱网或焊料抗蚀剂。特别地，该载体层由能够承受200至300℃的热处理的材料制成，因为其可以集成到器件内。载体层内的图形包含钝化材料可以流过的孔。尤其是如果使用注模工艺，该孔优选等于或者大于箔片和模子之间的距离。这种情况下的通常尺寸为约300μm。箔片可设有可分离的层。
参照下文中描述的一个(多个)实施例，本发明的这些和其它方面变得明显并将得到阐述。
在附图中：
图1A至F为该方法中多个阶段的器件的示意性截面视图；
图2为器件的第二实施例的截面视图；
图3为器件的第三实施例的截面视图；
图4为器件的第四实施例的截面视图；以及
图5A至C为用于该方法的箔片的三个实施例的平面视图。
附图并未按比例绘制，为了清楚而将部分尺寸放大。相应区域或部分总是具有相同的参考数字。
图1A至F为使用根据本发明的方法制造电子器件过程中多个阶段的示意性截面视图。这里使用的导电材料为铜且厚度优选为1至10μm，而这种情况下牺牲层11包含铝或者铝的合金。第一层1设有用于例如锡的焊料的粘性层。在第一层1内确定连接导体12、13、14。如果需要，也可具有其它未示出的导体。第一层1可被图形化，尤其是通过蚀刻，例如通过应用光掩模并使用氯化铁(ferrichloride)作为蚀刻剂。在本实例中，在图形化第一层1之后已经执行了蚀刻步骤，尽管该步骤不是必须的。在该刻蚀步骤中，刻蚀牺牲层，使得第一层1内的导体12、13、14部分地刻蚀不足。适当的蚀刻剂为氢氧化钠溶液。
图1B示出了在衬底的第一侧101上提供连续的电隔离层7之后的衬底10。所述隔离层7在此为包含丙烯酸酯箔片的厚25μm的合成树脂。所述丙烯酸酯箔片被施加小的压力并适度加热以将其粘附到设有锡层的第一图形化层1。
图1C示出了已经在衬底10的第一侧101上设有半导体元件20和第一互连元件30之后，临时的尚未分隔的器件90。半导体元件20在此为双极晶体管，而第一连接元件30为铜体。元件20、30设有在此为由Au制成的金属球22。所述金属球22位于半导体元件上的连接区域21上，连接区域21通常在半导体元件中确定。通过在提供该元件期间或者之后进行例如高达100℃的热处理，丙烯酸酯的隔离层被软化且金属球22下沉到衬底10的表面，在此之后通过进一步加热到例如265℃，从而建立金属连接。本领域技术人员将了解到，该温度依赖于所使用的焊料材料。如果需要，可以利用压力装置，该装置并未在图中示出。同样地，置于衬底10的下侧处的加热装置未在图中示出。
图1D示出了箔片40已经应用到元件20、30之后的器件90。所述箔片40包含厚度优选为30至60μm的第二图形化层2，以及在该实例中的干膜焊料抗蚀剂形成的图形化隔离层41。使用粘性层42、43将该箔片粘附到元件20、30，该粘性层由本领域技术人员所熟知的导电胶如填充银的环氧树脂制成。
图1E示出了已经提供隔离材料以形成非封装50之后的器件90。这种情况下，借助于穿过箔片40的隔离层41在模子(未示出)内的注模提供隔离材料。对于隔离材料则利用例如通过热处理进行固化的环氧树脂。封装50包含丙烯酸酯层7，且不仅封装元件20、30，也封装第二图形化层2和隔离层41。
图1F示出了牺牲层11已被清除且接着器件与未示出的相邻器件分离之后的器件100。接触面12、13、14在这种情况下与连接导体相同并形成第一层1的部分，因此出现在器件100的第一侧91上的表面处，而器件第二侧92上的第二层2嵌入在封装50内。
图2为器件100第二实施例的截面视图。在该实施例中，使用了具有可分离载体层的箔片。其结果为，器件100中的箔片40仅包含第二图形化层2和粘性层42、43。与图1所示器件的另外的差别与衬底10有关。该衬底在此实例中包含一个五层的叠层，最上面的粘性层未示出。其它层为第一图形化层1、这种情况下为铝合金的中间层81、铜的下层82、以及例如钛的用于焊料的粘性层83。当然也可以使用其它材料。由于中间层81中的图形的直径小于第一层1中的图形的直径，第一层1被机械锚定在封装50内，即在这种情况下锚定在由丙烯酸酯层7形成的部分中。在中间层81被部分地清除后，提供该衬底10。在提供封装50之后，使用用于焊料的粘性层83作为蚀刻掩模，部分地清除下层82。
图3为根据本发明的器件100的第三实施例的截面视图。在此实例中第一层1被图形化以形成HVQFN((High-Voltage Quad Flat Non-leaded)高压四平无铅)引线框形式的导体16、18、19。除了此时为集成电路的半导体元件20之外，在其上还存在第一和第二连接元件30、31。使用导电胶44、45、46将这些元件置于第一层1之上。为此目的，第一层1在制造时可由牺牲层(未示出)支撑，该牺牲层在稍后的阶段中被清除；然而该牺牲层并非是必须的。在此实例中第一层1包含铜。元件20、30、31置于第一层1之上，并已经设有金属球22。金属球上为具有图形化隔离层4的箔片1和第二层2，所述第二层面向金属球22，而且形成金属连接。为此目的，第二层2优选设有适当的粘性层。在第二层中确定连接导体12、13、14、15，其中导体12、15提供位于半导体元件20处的相关接触和连接元件30、31之间的电连接。同样地，导体13、14形成到另外的连接元件的互连连接，其中该另外的连接元件未示出。实际上，比所示接触的数目更多的接触是可能的，尤其是在复杂的集成电路情况下。为了在第二层2中容纳这些数目的导体，优选地制造所述层2使其为厚度为5μm且分辨率小于5μm的薄层。元件20、30、31由封装50进行封装，这种情况下形成第一层1的部分的接触面16、17、18位于器件100的第一侧91之上。在第二侧92上，封装延伸到隔离层41上。然而，这不是必须的。
图4为器件100的第四实施例的截面视图。其包含在此为集成电路的半导体元件20，该元件通过金属球22连接到第一层1。此外，器件100包含第一和第二连接元件30、31，其中的第一个为二极管，第二个为导电体。第二层2在此为互连第一和第二连接元件30、31的互连层。第一层1中的连接导体经由中间层81被进一步连接到下层82中的接触面16、17、18。衬底10进一步包含隔离材料85。
图5A至C为箔片40的三个实施例的平面视图。箔片包含载体层41，该载体层41至少在图5A和5C所示的实施例中是由电隔离材料制成。箔片40进一步包含其中定义了期望图形的第二图形化层2。在这里所示的实施例中，所述各层(？)组成两个导体，如图1和图2所示，元件20、30可以通过所述导体被互连。图5A示出了使用例如尼龙的纱网作为载体层41的实施例。图5B示出了可分离的层被用作载体层的实施例。为此目的，可以适当地利用其上涂敷了需要的粘接的粘性层的聚合物层。图5C示出了其中使用图形化层作为载体层41的实施例。该载体层设有孔49，使用已知的优选不昂贵的图形化技术获得该孔。优选通过也使用焊料抗蚀剂作为蚀刻掩模并欠蚀刻除去所述蚀刻掩模下的特定图形，制造图5C所示的箔片。然而，其结果为要求导电层具有几十微米的厚度，例如30至60微米。如果使用其它技术并使用分开的蚀刻掩模，当然可能产生具有更小厚度并因此具有更高分辨率的导电层，例如迹线宽度和迹线间距为5至10微米。

Claims (12)

1、电子器件的制造方法，包括如下步骤：
提供具有导电材料制成的第一层的衬底，在该层中根据期望图形确定或者将确定多个导体；
提供具有导电材料制成的第二层的箔片，在该层中根据期望图形确定多个导体；
在衬底的第一侧上提供包括半导体元件和第一连接元件的元件，从而使所述元件中的至少两个和第一层内相应的导体电接触，所述至少两个元件中的一个为第一连接元件；
在元件的任一侧上都提供第二导电层，从而在至少该两个元件和第二层中相应导体之间建立电接触；
从半导体元件的第二侧通过箔片提供钝化材料，该钝化材料形成元件的封装；以及
分离衬底、封装和第二导电层的组件，从而形成该电子器件。
2、权利要求1中所述的方法，其特征在于该箔片包含可分离的层，在半导体元件第二侧上提供箔片之后该层被除去。
3、权利要求1中所述的方法，其特征在于箔片包含图形化的电隔离层，以使得第二图形化层面向元件的方式提供箔片。
4、权利要求1中所述的方法，其特征在于箔片包含电隔离纱网，以使得第二图形化层面向元件的方式提供箔片。
5、权利要求1中所述的方法，其特征在于使用其中已经在第一层中确定连接导体的衬底。
6、权利要求5中所述的方法，其特征在于衬底包含牺牲层，在提供钝化材料之后该牺牲层至少部分地被除去。
7、权利要求1或5中所述的方法，其特征在于钝化材料也封装第二图形化层，并且衬底具有位于背离第一侧的第二侧上的用于外部接触的接触面。
8、一种电子器件，其具有第一侧和相对的第二侧，该第二侧设有具有位于第一和第二图形化导电材料层之间的第一和第二连接区域的半导体元件，该第一和第二图形化导电材料层分别位于第一和第二侧上，这些图形化层至少通过第一连接元件被电互连，在所述层内根据期望图形确定的导体，并且该半导体元件通过连接区域和至少一个所述层中的导体电连接，所述器件在第一侧上设有用于外部接触的接触面，所述接触面与第一图形化层内的导体的至少一部分电连接，所述元件和所述第二图形化层至少基本上被钝化材料封装所封装。
9、权利要求8中所述的电子器件，其特征在于第二导电层在背离元件的侧上设有图形化隔离层。
10、权利要求8中所述的电子器件，其特征在于第二导电层在背离元件的侧上设有隔离材料制成的纱网。
11、一种箔片，包含图形化的电隔离载体层和图形化的导电层，这两层的图形不同。
12、权利要求11中所述的箔片，其特征在于隔离载体层为纱网。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11170072B2 (en) 2015-04-10 2021-11-09 ASML Netherands B.V. Method and apparatus for inspection and metrology

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1631137A4 (en) * 2004-03-30 2009-05-27 Panasonic Corp MODULAR COMPONENT AND METHOD FOR MANUFACTURING THE SAME
US7405476B2 (en) * 2005-10-27 2008-07-29 Lsi Logic Corporation Asymmetric alignment of substrate interconnect to semiconductor die
WO2008137511A1 (en) 2007-05-04 2008-11-13 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits
DE102007034949A1 (de) * 2007-07-26 2009-02-05 Siemens Ag Einheitlich normierte Leistungspackages
US8110912B2 (en) * 2008-07-31 2012-02-07 Infineon Technologies Ag Semiconductor device
JP5147677B2 (ja) 2008-12-24 2013-02-20 新光電気工業株式会社 樹脂封止パッケージの製造方法
JP5147678B2 (ja) * 2008-12-24 2013-02-20 新光電気工業株式会社 微細配線パッケージの製造方法
EP2242094A1 (en) 2009-04-17 2010-10-20 Nxp B.V. Foil and method for foil-based bonding and resulting package
US10083781B2 (en) 2015-10-30 2018-09-25 Vishay Dale Electronics, Llc Surface mount resistors and methods of manufacturing same
US10217690B2 (en) * 2015-11-30 2019-02-26 Kabushiki Kaisha Toshiba Semiconductor module that have multiple paths for heat dissipation
US10438729B2 (en) 2017-11-10 2019-10-08 Vishay Dale Electronics, Llc Resistor with upper surface heat dissipation
TWI704628B (zh) * 2019-04-23 2020-09-11 智威科技股份有限公司 半導體元件封裝結構與半導體元件封裝方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2104262A1 (en) * 1970-02-02 1971-08-26 Int Standard Electric Corp High resolution metal or plastic screen gauze - printing plate
US4897327A (en) * 1988-05-27 1990-01-30 E. I. Du Pont De Nemours And Company Correct-reading images from photopolymer electrographic master
US5350947A (en) * 1991-11-12 1994-09-27 Nec Corporation Film carrier semiconductor device
JPH06268020A (ja) * 1993-03-10 1994-09-22 Sumitomo Electric Ind Ltd 半導体装置
WO1998015005A1 (de) * 1996-09-30 1998-04-09 Siemens Aktiengesellschaft Mikroelektronisches bauteil in sandwich-bauweise
JP2000114413A (ja) * 1998-09-29 2000-04-21 Sony Corp 半導体装置、その製造方法および部品の実装方法
US6300161B1 (en) * 2000-02-15 2001-10-09 Alpine Microsystems, Inc. Module and method for interconnecting integrated circuits that facilitates high speed signal propagation with reduced noise
US6234072B1 (en) * 2000-03-06 2001-05-22 John C. Kooima Grain husk cracking plate
JP3467454B2 (ja) * 2000-06-05 2003-11-17 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11170072B2 (en) 2015-04-10 2021-11-09 ASML Netherands B.V. Method and apparatus for inspection and metrology

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