CN113166929A - 无空隙低应力填充 - Google Patents

无空隙低应力填充 Download PDF

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CN113166929A
CN113166929A CN201980081000.XA CN201980081000A CN113166929A CN 113166929 A CN113166929 A CN 113166929A CN 201980081000 A CN201980081000 A CN 201980081000A CN 113166929 A CN113166929 A CN 113166929A
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feature
metal
deposition
tungsten
substrate
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阿南德·查德拉什卡
杨宗翰
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Lam Research Corp
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Lam Research Corp
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Abstract

本文提供了在深特征和相关装置中沉积低应力且无空隙金属膜的方法。所述方法的实施方案包括处理孔的侧壁以抑制金属沉积,同时留下未处理的特征底部。在随后的沉积操作中,金属前体分子扩散到特征底部以进行沉积。该工艺重复对剩余暴露侧壁进行处理的后续抑制操作。通过重复抑制和沉积操作,可以实现高质量的无空隙填充。这使得能执行高温、低应力沉积。

Description

无空隙低应力填充
通过引用并入
PCT申请表作为本申请的一部分与本说明书同时提交。如在同时提交的PCT申请表中所标识的本申请要求享有其权益或优先权的每个申请均通过引用全文并入本文且用于所有目的。
背景技术
沉积导电材料(如钨膜)是许多半导体制造过程中重要的一部分。这些材料可被用作水平内连接件、介于相邻金属层之间的通孔、金属层与硅衬底上的设备之间的触点、以及高深宽比特征。随着设备缩小以及更复杂的图案化架构被运用于该产业中,薄膜的沉积成为一种挑战。这些挑战包括沉积无空隙且低应力的膜。
这里提供所包含的背景与情境描述仅为了一般性呈现本公开的背景的目的。本公开的大部分内容呈现了发明人的成果,且仅是因为该成果被描述于该背景技术部分或在本文其他地方作为背景呈现,这并不意味承认其为现有技术。
发明内容
本公开的一个方面涉及一种方法,该方法包括:提供3-D结构,所述3-D结构包括以阶梯状图案布置的金属线、覆盖所述阶梯状图案的介电材料、以及竖直定向特征,所述竖直定向特征提供通向金属线的流体通路;在所述竖直定向特征中沉积金属保形层;在第一抑制操作中以第一流率和第一暴露时间将所述金属保形层特征暴露于抑制物质;在所述第一抑制操作之后,在第一非保形沉积操作中优先在所述竖直定向特征的所述底部沉积金属,其中在所述第一非保形沉积操作期间所述衬底的温度至少为400℃;在所述第一非保形沉积操作之后,在第二抑制操作中以第二流率和第二暴露时间将所述特征暴露于抑制物质,其中所述第二流率低于第一流率和/或所述第二暴露时间短于所述第一暴露时间;并且在所述第二抑制操作之后,在第二非保形沉积操作中,在至少400℃的衬底温度下在所述特征中沉积金属。
在一些实施方案中,所述金属是钨、钴、钼和钌中的一种。在一些实施方案中,优先在所述竖直定向特征的所述底部沉积金属包括:将所述特征暴露于金属前体和还原剂,其中还原剂比金属前体的体积比至少为30:1。在一些实施方案中,优先在所述竖直定向特征的所述底部沉积金属包括:将所述特征以不超过100sccm的流率暴露于金属前体。在一些实施方案中,所述特征是3D NAND设备中的互连特征。在一些实施方案中,在沉积期间,所述金属是钨,并且所述衬底温度至少为430℃。在一些实施方案中,在沉积期间,所述金属是钼,并且所述衬底温度至少为600℃。
在一些实施方案中,所述抑制物质是含氮气体或等离子体物质。在一些实施方案中,所述第一禁止操作处理所述特征的大部分。在一些实施方案中,所述方法的所述第一抑制操作处理所述特征深度的至少70%。在一些实施方案中,在所述第一抑制操作期间的衬底温度不同于在所述第二抑制操作期间的衬底温度。
本公开内容的另一方面涉及一种用于处理衬底的装置,所述装置包括:(a)处理室,其包括至少一个站,所述站具有被配置为保持衬底的基座;(b)用于耦合至真空的至少一个出口;(c)耦合到一个或多个工艺气体源的一个或多个工艺气体入口;和(d)用于控制所述装置中的操作的控制器,其包括机器可读指令,所述机器可读指令用于执行以下方法:在第一抑制操作中以第一流率和第一暴露时间将抑制物质引入所述处理室;在所述第一抑制操作之后,在第一非保形沉积操作中,引入金属前体和还原剂以沉积金属,其中所述衬底在其上的所述基座的温度至少为400℃;在所述第一非保形沉积操作之后,在第二抑制操作中,以第二流率和第二暴露时间将抑制物质引入所述处理室,其中所述第二流率低于所述第一流率和/或所述第二暴露时间短于所述第一暴露时间;以及在所述第二抑制操作之后,引入金属前体和还原剂以沉积金属,其中所述衬底在其上的所述基座的温度为至少400℃。在一些实施方案中,在第二非保形沉积操作中,在沉积期间,所述金属是钨,并且所述衬底温度至少为430℃。在一些实施方案中,在所述第一和第二非保形沉积操作期间,还原剂比钨前体的体积比至少为30:1。
本公开内容的另一方面涉及一种方法,其包括:在衬底上的特征中沉积金属保形层;处理所述保形层的部分以抑制随后的钨成核;在处理所述保形层的所述部分后,优先在所述特征的所述底部沉积钨,其中在所述沉积过程中所述衬底的温度至少为400℃;以及重复所述处理和沉积操作一次或多次以用金属填充所述特征。
下面参考附图描述这些和其他方面。
附图说明
图1A示出了示意性示例3D结构结构,其可以使用本文所述的特征填充方法用导电材料填充。
图1B示出了在使用本文描述的方法进行特征填充处理之后的3D结构的互连的示意性示例。
图2是说明填充特征的方法中的某些操作的流程图。
图3示出了在使用本文描述的方法的填充处理的各个阶段的特征的示意性示例。
图4是根据本文描述的实施方案适合于进行沉积工艺的处理系统的框图。
图5是根据本文描述的实施方案适合于进行抑制和沉积工艺的站的图。
具体实施方式
在以下描述中,阐述了许多具体细节以提供对本发明的透彻理解。可以在没有这些特定细节中的一些或全部的情况下实践本发明。在其他情况下,没有详细描述众所周知的工艺操作,以免不必要地使本发明难以理解。虽然本发明将结合具体的实施方式进行描述,但是应当理解,其并不意在将本发明限制于这些实现方式。
这里描述的是特征填充的方法以及相关的系统和装置。应用的示例包括逻辑和存储器触点填充、DRAM埋入字线填充、竖直集成存储器栅极/字线填充以及利用硅通孔(TSV)的3-D集成。在一些实施方案中,所述方法可用于钨特征填充。这样的特征可以包括竖直特征,例如通孔,以及水平特征,例如竖直NAND(VNAND)字线。
在一些实施方案中,本文提供了在深特征和相关装置中沉积低应力且无空隙金属膜的方法。所述方法的实施方案包括处理孔的侧壁以抑制金属沉积,同时留下未处理的特征底部。在随后的沉积操作中,金属前体分子扩散到特征底部以进行沉积。该工艺重复对剩余暴露侧壁进行处理的后续抑制操作。通过重复抑制和沉积操作,可以实现高质量的无空隙填充。这使得能执行高温、低应力沉积。
图1A示出了可以使用本文所述的特征填充方法填充导电材料的示例性结构。在图1A的示例中,结构102是部分制造的3D NAND设备。衬底100上的交替氧化物层111和钨或其他金属字线140以阶梯结构示出。尽管为了便于说明而描绘了五条字线140,但是根据各种实施方案,结构102可以包括任何数量的字线,例如48条字线、256条字线、512条字线或1024条字线。在一些实施方式中,要填充的特征至少为10微米深,并且可以更深,例如30微米深。
氧化层122沉积在阶梯结构上,特征137蚀刻在氧化层122中。这些特征137可以使用本文描述的方法填充钨或其他金属以提供到字线140的互连件。图1B示出了填充处理之后的互连件142。
图2是说明填充特征的方法中的某些操作的流程图。该方法开始于操作202:在特征中沉积保形材料层。该层可以是成核层或主体层,其保形地内衬特征。在某些实现方式中,例如,如果下面的特征表面对随后的抑制化学物质敏感,则可以省略操作202。在钨的示例中,操作202会涉及将特征暴露于钨前体(例如六氟化钨(WF6))以及还原剂(例如氢(H2))。图3显示了保形沉积(标记为保形沉积1)后的特征的示例。返回到图2,然后将该特征暴露于抑制化学物质中,以对除特征底部之外的成核进行保形抑制(204)。操作204的示例在图3(标记为保形抑制)中示出,圆圈表示被抑制的表面。被抑制的表面是在其上的钨或其他材料的随后成核被抑制、在其上的沉积被延迟或防止的表面。从图3中可以看出,除了特征底部和从底部向上延伸的短长度的侧壁外,特征的大部分都被抑制。根据各种实施方案,抑制可以延伸至特征深度的99%、95%、90%、80%、70%或60%。
在一些实现方式中,操作204涉及在热(非等离子体)操作中将特征暴露于含氮化合物,例如氮(N2)或氨(NH3)。在替代的实施方案中,抑制化学物质可以作为在远程或直接等离子体产生器中产生的等离子体物质提供。
返回图2,在特征底部沉积低应力膜(206)。为了沉积低应力膜,该特征可以在高温下暴露于处于前体耗尽状态中的前体和还原剂。前体耗尽状态可以表征为具有至少30:1的体积还原剂:前体流率比。在一些实施方案中,使用至少400℃的衬底温度。
对于使用WF6进行的钨沉积,可以使用至少400℃或至少430℃的衬底温度,并且可以使用不超过100sccm的WF6。室压强可以介于5和200托(Torr)之间,包括端值。WF6与H2和载气(例如氩气(Ar))一起传送。H2和载气流量至少比前体流量大一个数量级。示例范围如下:
WF6流率小于100sccm;
H2流率介于3000到6000sccm之间;
Ar流率介于4000和8000sccm之间。
对于Mo沉积,温度可以是至少450℃,例如,介于450℃和800℃之间,例如,介于600℃和750℃之间。
操作204可以执行同时暴露两种反应物,使得两种反应物在沉积期间同时流动。例如,可以通过将衬底同时暴露于氢(H2)和六氟化钨(WF6)来沉积主体钨。氢和WF6(或其他金属前体)在暴露期间发生反应以将钨沉积到特征中。在脉冲式CVD工艺中,一种反应物连续流动,而另一种反应物则被脉冲式供给,但在沉积过程中,衬底暴露于两种反应物,以在每个脉冲期间沉积材料。例如,当WF6被脉冲式供给时,衬底可以暴露于连续的H2流中,并且WF6和H2在脉冲期间反应以沉积钨。在一些实施方案中,操作204可以涉及对每个反应物的单独暴露,使得反应物在沉积期间不会同时流入室。相反,每个反应物流以暂时分离的脉冲顺序被引入容纳衬底的室中,循环重复一次或多次。在这样的实施方案中,可以通过在脉冲期间使用更多的还原剂脉冲和/或体积流率来实现前体耗尽状态。
在前体耗尽状态和高温下的沉积导致低应力膜;然而,这些条件也使特征填充具有挑战性,因为可用于反应的少量前体将在最近的可用反应表面进行该特征填充。如果没有抑制,则前体将在特征顶部消耗,关闭特征以进一步扩散并产生空隙。因此,先前操作中的抑制防止了在侧壁表面上的反应,将前体引导至特征的底部以进行反应。这在图3(参见沉积2后的抑制)中说明,第二次沉积(沉积2)在特征底部沉积材料。返回到图2,重复操作204和206一次或多次(208)。这在图3(沉积2+抑制和沉积3)中进行了说明。如图3所示,抑制在沉积过程中消失。
相比于先前的沉积,每个连续的抑制都可以被认为是“不太保形”,因为其延伸到更浅的深度以适应特征底部的膜生长。为了控制抑制深度,温度和抑制气体流率可以用较高的温度和较低的流率进行调节,导致较浅的深度。然而,由于衬底温度通常由沉积的要求决定,因此可以修改抑制流率。
在一些实现方式中,重复操作204和206直到完全填充特征。在一些实施方案中,可以重复操作204和206以用自下而上填充来部分地填充特征,随后是用于最终特征填充的更长的CVD沉积。可以执行非保形抑制以抑制在内凹(re-entrant)特征的顶部处的沉积,如图3所示。
沉积和抑制操作可以在相同或不同的处理室中进行。此外,如果在多站室中进行,它们可以在相同或不同的站中进行。在一些实施方案中,一个或多个沉积和抑制循环在多站室的同一站中进行。例如,涉及六个沉积/抑制循环的特征填充操作和最终的CVD填充操作可以在四站式室中实施,如下所示:
第1站:2个沉积/抑制循环
第2站:2个沉积/抑制循环
第3站:2个沉积/抑制循环
第4站:CVD沉积
成核层沉积
在一些实现方式中,本文所述的方法涉及在沉积主体层之前沉积钨成核层。在本文所述的示例中,成核层可以被沉积为第一保形沉积或作为第一保形沉积的种子层。成核层是有助于随后在其上沉积主体含钨材料的薄保形层。根据各种实现方式,可以在特征的任何填充之前和/或在特征的填充期间的后续点处沉积成核层。在本文描述的方法的一些实现方式中,成核层仅在特征填充开始时沉积并且在随后的沉积中不是必需的。
在某些实现方式中,使用脉冲成核层(PNL)技术来沉积成核层。在PNL技术中,含钨前体、任选的吹扫气体和还原剂的脉冲依次注入反应室和从反应室吹扫。该处理以循环方式重复,直到达到所期望的厚度。PNL广泛地体现了顺序添加反应物以在半导体衬底上进行反应的任何循环处理,其包括原子层沉积(ALD)技术。成核层厚度可取决于成核层沉积方法以及主体沉积的所需质量。通常,成核层厚度足以支持高质量、均匀的主体沉积。示例的范围可以从
Figure BDA0003103831760000071
虽然上面提供了PNL沉积的示例,但本文所述的方法不限于钨成核层沉积的特定方法,而是包括在通过任何方法形成的钨成核层上沉积主体钨膜,所述方法包括PNL、ALD、CVD和物理气相沉积(PVD)。此外,在某些实现方式中,主体钨可以直接沉积在特征中而不使用成核层。例如,在一些实现方式中,特征表面和/或已经沉积的底层支持主体钨沉积。在一些实现方式中,可以执行不使用成核层的主体钨沉积工艺。
在多种实现方式中,钨成核层沉积可涉及暴露于含钨前体,例如六氟化钨(WF6)、六氯化钨(WCl6)和六羰基钨(W(CO)6)。在某些实现方式中,含钨前体是含卤素化合物,例如WF6。也可以使用有机金属前体和不含氟的前体,例如MDNOW(甲基环戊二烯基-二羰基亚硝酰基-钨)和EDNOW(乙基环戊二烯基-二羰基亚硝酰基-钨)。
还原剂的示例可以包括含硼还原剂(其包括乙硼烷(B2H6)和其他硼烷)、含硅还原剂(其包括硅烷(SiH4)和其他硅烷)、肼和锗烷。在一些实现方式中,含钨前体的脉冲可以与一种或多种还原剂的脉冲交替,例如S/W/S/W/B/W等,W表示含钨前体,S表示含硅前体,而B代表含硼前体。在一些实现方式中,可以不使用单独的还原剂,例如,含钨前体可以经历热分解或等离子体辅助分解。
根据不同的实现方式,氢气可能会或可能不会在背景中运行。此外,在一些实现方式中,钨成核层的沉积之后可以是一个或多个处理操作,然后才是钨主体沉积。处理沉积的钨成核层以降低电阻率可以包括:还原剂和/或钨前体的脉冲。
主体沉积
在许多实现方式中,钨主体沉积可以通过CVD工艺发生,其中还原剂和含钨前体流入沉积室以在特征中沉积主体填充层。惰性载气可用于输送一种或多种反应物流,其可以或可以不预先混合。与PNL或ALD工艺不同,该操作通常涉及使反应物连续流动,直到沉积所需的量。在某些实现方式中,CVD操作可以在多个阶段中进行,其中反应物的连续和同时流动的多个时期通过被转向的一种或多种反应物流动的时期分开。
包括但不限于WF6、WCl6和W(CO)6的各种含钨气体可用作含钨前体。在某些实现方式中,含钨前体是含卤素化合物,例如WF6。在某些实现方式中,还原剂是氢气,但也可以使用其他还原剂,包括使用硅烷(SiH4)、乙硅烷(Si2H6)、肼(N2H4)、乙硼烷(B2H6)和锗烷(GeH4)。在许多实现方式中,氢气被用作CVD工艺中的还原剂。在一些其他实现方式中,可以使用可以分解以形成主体钨层的钨前体。也可以使用其他类型的工艺(包括ALD工艺)进行主体沉积。
应当理解,本文所述的钨膜可以包括一定量的其他化合物、掺杂剂和/或杂质,例如氮、碳、氧、硼、磷、硫、硅、锗等,具体取决于使用的特定前体和工艺。膜中的钨含量可以在20%到100%(原子)钨的范围内。在许多实现方式中,膜是富含钨的,具有至少50%(原子)钨,或者甚至至少约60%、75%、90%或99%(原子)钨。
虽然以上描述集中于钨特征填充,但本公开内容的方面也可以在用其他材料填充特征中实现。例如,使用本文描述的一种或多种技术的特征填充可用于用其他材料填充特征,所述其他材料包括其他含钨材料(例如氮化钨(WN)和碳化钨(WC))、含钛材料(例如,钛(Ti)、氮化钛(TiN)、硅化钛(TiSi)、碳化钛(TiC)和铝化钛(TiAl))、含钽材料(例如,钽(Ta)和氮化钽(TaN))、含镍材料(例如镍(Ni)和硅化镍(NiSi)、含钴材料(例如钴(Co))、含钌材料(例如钌(Ru))和含钼材料(例如,钼(Mo))。
这些材料的CVD和ALD沉积可以包括使用任何合适的前体。例如,氮化钨的CVD和ALD沉积可以包括使用含钨和含氮化合物。含钛层的CVD和ALD沉积可以包括使用含钛的前体,示例包括四(二甲氨基)钛(TDMAT)和氯化钛(TiCl4),以及如果合适的话,一种或多种共反应物。含钽层的CVD和ALD沉积可以包括使用前体(例如五-二甲氨基钽(PDMAT)和TaF5)以及(如果合适的话)一种或多种共反应物。含钴层的CVD和ALD沉积可以包括使用前体,例如三(2,2,6,6-四甲基-3,5-庚二酮酸)钴(Tris(2,2,6,6-tetramethyl-3,5-heptanedionato)cobalt)、双(环戊二烯基)钴和六羰基丁乙炔二钴,以及一种或多种共反应物。
钴前体的示例有二羰基环戊二烯基钴、羰基钴、脒钴(cobalt amidinate)前体、二氮杂二烯钴络合物和脒钴/胍前体。
可用于氧化反应的钌前体的示例包括(乙基苄基)(1-乙基-1,4-环己二烯基)Ru(0)、2,3-二甲基-1,3-丁二烯基)Ru(0)三羰基、(1,3-环己二烯基)Ru(0)三羰基和(环戊二烯基)(乙基)Ru(II)二羰基。可以用于氧化反应的钌前体的示例包括(乙基苄基)(1-乙基-1,4-环己二烯基)Ru(0)、(1-异丙基-4-甲基苄基)(1,3-环己二烯基)Ru(0)、2,3-二甲基-1,3-丁二烯基)Ru(0)三羰基、(1,3-环己二烯基)Ru(0)三羰基和(环戊二烯基)(乙基)Ru(II)二羰基。与非氧化反应物反应的钌前体的示例是双(5-甲基-2,4-己二酮基)Ru(II)二羰基和双(乙基环戊二烯基)Ru(II)。
镍前体的示例包括环戊二烯基烯丙基镍(CpAllylNi)和MeCp2Ni。
可以使用的钼前体的示例包括六氟化钼(MoF6)、五氯化钼(MoCl5)、二氧化二氯化钼(MoO2Cl2)、四氯化氧化钼(MoOCl4)和六羰基钼(Mo(CO)6)。共反应物的示例可以包括N2、NH3、N2H4、N2H6、SiH4、Si3H6、B2H6、H2、和AlCl3
含金属的前体可以与如上所述的还原剂反应。在一些实施方案中,H2用作主体层沉积的还原剂以沉积高纯度膜。
抑制成核
抑制可能涉及暴露于钝化特征表面的活化物质。例如,在某些实现方式中,钨(W)表面可以通过暴露于基于氮或基于氢的等离子体而钝化。
在一些实现方式中,抑制可涉及活化物质与特征表面之间的化学反应以形成诸如氮化钨(WN)或碳化钨(WC)之类的复合材料薄层。在一些实现方式中,抑制可以涉及表面效应,例如在不形成复合材料层的情况下钝化表面的吸附。活化物质可以通过任何合适的方法形成,包括通过等离子体产生和/或暴露于紫外线(UV)辐射形成。在一些实现方式中,包括特征的衬底暴露于由一种或多种气体产生的等离子体,所述一种或多种气体被供给到衬底所在的室中。在一些实现方式中,一种或多种气体可以被供给到远程等离子体产生器中,在远程等离子体产生器中形成的活化物质被供给到衬底所在的室中。等离子体源可以是任何类型的源,包括射频(RF)等离子体源或微波源。等离子体可以电感耦合的和/或电容耦合的。活化物质可包括原子物质、自由基物质和离子物质。在某些实现方式中,暴露于远程产生的等离子体包括暴露于自由基和原子化物质,等离子体中基本上不存在离子物质,使得抑制过程不是离子介导的。在其他实现方式中,离子物质可以存在于远程产生的等离子体中。在某些实现方式中,暴露于原位等离子体涉及离子介导的抑制。
对于钨表面,暴露于氮基和/或氢基等离子体会抑制钨表面上随后的钨沉积。可用于抑制钨表面的其他化学物质包括基于氧的等离子体和基于碳氢化合物的等离子体。例如,分子氧或甲烷可被引入等离子体产生器。含氮化学物质还抑制本文所述的其他金属(包括Mo、Co和Al)的成核。如本文所使用的,氮基等离子体是其中主要非惰性组分为氮的等离子体。惰性成分例如氩气、氙气或氪气可以用作载气。在一些实现方式中,除痕量外,在产生等离子体的气体中不存在其他非惰性组分。在一些实现方式中,抑制化学物质可以是含氮、含氢、含氧和/或含碳的,其中在等离子体中存在一种或多种额外的反应性物质。
例如,使用NF3等离子体,在活化的氟自由基与特征开口处的钨反应并去除钨的情况下,由NF3等离子体产生的氮会导致钨表面氮化,从而形成氮化钨。与常规主体钨膜相比,钨在氮化表面上的后续沉积明显延迟。更长的延迟使得特征在夹断之前能保持开放更长时间,并促进填充改进,因为更多的WF6分子可以到达特征内部并沉积钨。除了NF3之外,还可以使用碳氟化合物,例如CF4或C2F8。然而,在某些实现方式中,抑制物质不含氟以防止在抑制过程中蚀刻。
在某些实现方式中,可以使用UV辐射和/或热能代替等离子体产生器或除等离子体产生器之外还使用UV辐射和/或热能以提供活化物质。除了钨表面,还可以抑制在衬里/阻挡层表面(例如TiN和/或WN表面)上的成核。可以使用钝化这些表面的任何化学物质。对于TiN和WN,这可以包括暴露于氮基或含氮化学品。在某些实现方式中,上文针对W描述的化学物质也可用于TiN、WN或其他衬里层表面。在一些实现方式中,抑制涉及在非等离子体操作中暴露于NH3
调节抑制轮廓可以涉及适当地控制抑制化学过程、衬底偏置功率、等离子体功率、处理压强、暴露时间和其他工艺参数。对于原位等离子体工艺(或其他存在离子物质的工艺),可以对衬底施加偏置。在一些实现方式中,衬底偏置会显著影响抑制轮廓,其中偏置功率的增加导致活性物质在特征内更深。对于需要横向方向(钨沉积优选在结构内部)但不是在竖直方向有选择性的3-D结构,增加的偏置功率可用于促进从上到下的沉积均匀性。
虽然偏置功率可在某些实现方式中用作主要或唯一旋钮来调整离子物质的抑制轮廓,但在某些情况下,调整抑制轮廓使用其他参数作为偏置功率的补充或替代偏置功率。这些包括远程生成的非离子等离子体工艺和非等离子体工艺。此外,在许多系统中,可以很容易地应用衬底偏置来调整竖直方向而非横向方向的选择性。
因此,对于需要横向选择性的3-D结构,可以控制除偏置之外的参数,如上所述。
抑制化学也可用于调整抑制轮廓,其中使用不同比例的活性抑制物质。例如,对于W表面的抑制,氮可能比氢具有更强的抑制作用;调整基于合成气体的等离子体中N2和H2气体的比例可用于调整轮廓。等离子体功率还可用于调节抑制轮廓,其中活性物质的不同比率由等离子体功率调节。例如,在本文所述的某些实现方式中,可以通过改变等离子体功率来调节氮自由基形成和所得W-N形成以及相关的钝化效应。改变等离子体功率还可以控制最终W膜的电阻率。
工艺压强可用于调整轮廓,因为压强会导致更多的复合(使活性物质失活)以及将活性物质进一步推入特征中。处理时间也可用于调整抑制轮廓,增加处置时间会导致抑制更深入到特征中。
在一些实现方式中,非保形抑制可以通过在质量传递受限状态中实现。在该状态中,特征内部的抑制率受扩散到特征中的不同抑制材料组分(例如,初始抑制物质、活化抑制物质和复合的抑制物质)的量和/或相对组成的限制。在某些示例中,抑制率取决于特征内不同位置的各种成分的浓度。
质量传递受限状态可以部分地通过总体抑制浓度变化来表征。在某些实现方式中,特征内部的浓度小于其开口附近的浓度,导致开口附近的抑制率高于内部。这进而导致特征开口附近的优先抑制。质量传递受限工艺条件可以通过以下方式来实现:将有限量的抑制物质供应到处理室中(例如,使用相对于腔轮廓和尺寸的低抑制气体流率),同时在特征开口附近保持相对高的抑制率以在一些活性物质扩散到特征中时将其消耗。在某些实现方式中,浓度梯度很大,这可能导致相对高的抑制动力学和相对低的抑制供给。在某些实现方式中,开口附近的抑制率也可能是质量传递受限的。
除了特征内部的总体抑制浓度变化外,抑制特征可能会受到整个特征中不同抑制物质的相对浓度的影响。这些相对浓度又可取决于抑制物质的解离和复合过程中的相对动力学。如上所述,初始抑制材料(例如分子氮)可以通过远程等离子体产生器和/或经受原位等离子体作用以产生活化物质(例如原子氮、氮离子)。然而,活化的物质会复合为活性较低的复合物质(例如,氮分子)和/或与W、WN、TiN或沿其扩散路径的其他特征表面反应。因此,特征的不同部分可以暴露于不同浓度的不同抑制材料,例如初始抑制气体、活化抑制物质和复合抑制物质。这为控制抑制轮廓提供了额外的机会。例如,活化物质通常比初始抑制气体和复合抑制物质更具反应性。此外,在某些情况下,活化物质对温度变化的敏感度可能低于复合物质。因此,可以以去除主要归因于活化物质的方式来控制工艺条件。如上所述,某些物质可能比其他物质更具反应性。此外,特定的工艺条件可能导致在特征开口附近的活化物质的浓度高于特征内部。例如,一些活化物质可能会被消耗(例如,与特征表面材料反应和/或吸附在表面上)和/或复合,同时更深地扩散到特征中,尤其是在小的高深宽比特征中。活化物质的复合也可以发生在特征之外,例如在喷头或处理室中,并且可以取决于室压强。因此,可以控制室压强以调节室和特征的各个点处的活化物质的浓度。
在某些实现方式中,可以在抑制之前加热或冷却衬底。可选择衬底的预定温度以诱导特征表面与抑制物质之间的化学反应和/或促进抑制物质的吸附,以及控制反应或吸附的速率。例如,可以选择温度以具有高反应速率,使得在开口附近比在特征内部发生更多的抑制。此外,还可以选择温度以控制活化物质的复合(例如,原子氮复合为分子氮)和/或控制哪些物质(例如,活化的或复合的物质)主要有助于抑制。在某些实现方式中,衬底保持在低于约300℃,或更具体地低于约250℃,或低于约150℃,或甚至低于约100℃。在其他实现方式中,衬底被加热至约300℃至450℃之间,或在更具体的实现方式中,加热至约350℃至400℃之间。其他温度范围可用于不同类型的化学抑制。在一些实施方案中,抑制温度可以与沉积温度相同,该温度可以相对高以沉积低应力膜。然而,在一些实施方案中,使用多站室,其中在不同站执行沉积和抑制。这可以促进操作之间的温差。
如上所述,在一些实施方案中,使用热抑制工艺。热抑制工艺可以包括将特征暴露于含氮化合物,例如氨(NH3)或肼(N2H4),以保形或非保形地抑制该特征。在一些实施方案中,热抑制工艺在250℃至450℃的温度范围内进行。在这些温度下,先前形成的钨成核层暴露于NH3会导致抑制效应。其他可能具有抑制作用的化学物质(例如氮气(N2)或氢气(H2))可用于在较高温度(例如900℃)下进行热抑制。然而,对于许多应用而言,这些高温超出了热预算。除氨外,其他含氢氮化剂(如肼)也可在适合生产线后端(BEOL)应用的较低温度下使用。
由于热抑制工艺不使用等离子体,因此不能使用衬底上的偏置功率来调整抑制轮廓。然而,通过适当调整室压强、流率、剂量时间和温度中的一项或多项,可以根据需要调整抑制轮廓。如上所述,在一些实施方案中,采用了质量传递受限状态。在一些实施方案中,室压强的范围可以从0.5托到40托。如上所述,抑制气体的流率可取决于室的尺寸、反应速率和其他参数。可以以这样的方式选择流率,使得相比于特征内部,在开口附近集中更多的抑制材料。在某些实施方案中,这些流率导致质量传递受限的选择性抑制。
增加的压强和减少的流率和剂量时间导致更多的非保形(即,对特征开口更具选择性)的抑制轮廓。较高的压强导致较低的平均自由程,而较低的流率和剂量时间限制了要消耗的分子数量。温度升高会导致更不保形的抑制轮廓,在特征顶部消耗更多抑制分子。
可以根据夹断点是否在特征内,如上所述来调整轮廓。示例性的配料时间范围从0.5秒到10秒。
在一些实施方案中,抑制会涉及热抑制剂物质和特征表面之间的化学反应以形成WN复合材料薄层。在一些实施方案中,抑制可以涉及表面效应,例如在不形成复合材料层的情况下钝化表面的吸附。
如果存在金属成核层,它可能会暴露于NH3或其他抑制蒸气中以抑制该特征。在一些实施方案中,如果存在主体钨或含钨层,则可采用还原剂/含钨前体/含氮抑制化学物质以在主体层上形成WN。这些反应物可以依次(例如B2H6/WF6/NH3脉冲)或同时引入。可以使用任何合适的还原剂(例如,乙硼烷或硅烷)和任何合适的含钨前体(例如,六氟化钨或六羰基钨)。可以使用热处理来避免可能因使用等离子体而引起的损坏。
在本文所述的方法中,抑制轮廓可以通过抑制气体的温度和/或流率来控制。用于沉积低应力膜的较高温度会导致在特征顶部消耗更多抑制物质。对于越深的抑制(例如在早期循环的抑制操作中使用的),可以使用越高的流率。抑制气体的流率可以取决于室的尺寸、反应速率和其他参数。可以以这样的方式选择流率,使得相比于在特征内部,在开口附近集中更多的抑制材料。也可以选择暴露时间以产生特定的抑制轮廓。示例性的暴露时间可以在大约10秒到500秒的范围内,具体取决于所需的选择性和特征深度。流率和/或暴露时间可能会随着连续循环增加而降低,从而导致较浅的抑制。
装置
任何合适的室均可用于实施所公开的实施方案。示例性沉积装置包括多种系统,例如
Figure BDA0003103831760000152
Figure BDA0003103831760000151
其可从加州弗里蒙特的Lam Research Corp.获得,或多种其他市售的处理系统中的任何一种。
图4是根据实施方案适合于进行沉积工艺的处理系统的框图。系统400包括传送模块403。传送模块403提供清洁、加压的环境以最小化在被处理的衬底在不同反应器模块之间移动时衬底的污染风险。根据实施方案,安装在转移模块403上的是能够执行ALD和CVD以及抑制工艺的多站反应器409。多站反应器409可以包括多个站411、413、415和417,它们可以根据公开的实施方案顺序地执行操作。例如,多站反应器409可以配置成使得站411执行ALD成核和抑制,站413和415各自执行多个CVD和抑制循环,并且站417执行CVD。在另一示例中,多站反应器409被配置成使得站411执行ALD成核,站413执行抑制,站415执行ALD或CVD沉积,并且站417执行CVD。
站可包括加热的基座或衬底支撑件、一个或多个气体入口或喷头或分散板。图5中描绘了沉积站500的示例,其包括衬底支撑件502和喷头503。可以在基座部分501中提供加热器。基座501可以包括用于夹持晶片的卡盘。在某些实施方案中,可以使用静电或机械卡盘而不是真空卡盘以促进提供低压环境。气体可以通过排放装置(未示出)排出沉积站500。
同样安装在转移模块403上的可以是一个或多个能够执行等离子体或化学(非等离子体)预清洁的单站或多站模块407。该模块还可用于各种处理,以例如,为沉积工艺准备衬底。系统400还包括一个或更多个晶片源模块401,在处理之前和之后晶片被存储在晶片源模块401。大气传送室419中的大气机械手(未示出)可以首先将晶片从源模块401移动到装载锁421。传送模块403中的晶片传送装置(通常为机械手臂单元)将晶片从装载锁421移动到安装在传送模块403上的模块上以及将晶片在这些模块之间移动。
在多种实施方案中,采用系统控制器429控制沉积过程中的工艺条件。所述控制器429将通常包括一个或更多个存储器器件和一个或更多个处理器。所述处理器可包括CPU或计算机、模拟和/或数字输入/输出连接、步进电机控制器板等。
所述控制器429可控制所有沉积装置的活动。所述系统控制器429运行系统控制软件,所述系统控制软件包括用于控制时序、气体混合、室压力、室温度、晶片温度、射频(RF)功率电平、晶片卡盘或基座位置和特定工艺的其他参数的指令集。在一些实施方案中,可以使用存储在与控制器429相关的存储器器件上的其他计算机程序。
通常,将有与控制器429相关联的用户界面。用户界面可包括显示屏,所述装置和/或工艺条件的图形软件显示器和用户输入装置,例如定点装置、键盘、触摸屏、麦克风等。
系统控制逻辑可以任何合适的方式进行配置。一般情况下,所述逻辑可被设计或配置在硬件和/或软件中。用于控制驱动电路的指令可被硬编码或作为软件提供。所述指令可通过“编程”提供。这样的编程被理解为包括任何形式的逻辑,该逻辑包括数字信号处理器、专用集成电路以及具有作为硬件实施的具体算法的其他装置中的硬编码逻辑。编程也被理解为包括可在通用处理器上执行的软件或固件指令。系统控制软件可以以任何合适的计算机可读编程语言编码。
用于控制工艺序列中的含锗还原剂脉冲、氢气流、和含钨前体脉冲以及其他工艺的计算机程序代码可以任何常规的计算机可读编程语言:例如,汇编语言、C、C++、Pascal、Fortran或其它写入。由处理器执行编译后的目标代码或脚本以进行程序中识别的任务。还如所指示的,程序代码可以是硬编码的。
控制器参数涉及工艺条件,诸如例如工艺气体组成和流率、温度、压力、冷却气体压强、衬底温度和室壁温度。这些参数以配方的形式提供给用户,并且可利用用户界面输入。
用于监控工艺的信号可以通过系统控制器429的模拟和/或数字输入连接来提供。用于控制工艺的信号通过系统400的模拟和数字输出连接件输出。
所述系统软件可以许多不同的方式进行设计或配置。例如,可以写入多个室组件子程序或控制目标以控制根据公开的实施方案执行沉积工艺所需要的室组件的操作。用于此目的的程序或程序段的示例包括衬底定位代码、工艺气体控制代码、压力控制代码、和加热器控制代码。
在一些实施方案中,控制器429是系统的一部分,该系统可以是上述实施例的一部分。这样的系统包括半导体处理装置,半导体处理装置包括一个或多个处理工具、一个或多个室、用于处理的一个或多个平台、和/或特定的处理部件(晶片基座、气体流系统等)。这些系统可以与电子器件集成,以便在半导体晶片或衬底的处理之前、期间或之后控制这些系统的操作。电子器件可以被称为“控制器”,其可以控制一个或多个系统的各种组件或子部分。根据处理要求和/或系统的类型的不同,控制器429可以被编程,以控制本发明所公开的工艺中的任何一些,包括控制工艺气体的输送、温度设置(例如,加热和/或冷却)、压强设置、真空设置、功率设置、流率设置、流体输送设置、位置和操作设置、晶片的进出工具和其他传送工具和/或连接到特定系统的或与该系统接口的加载锁的传送。
从广义上讲,控制器可以被定义为接收指令、发出指令、控制操作、使能清洁操作、使能终点测量等的具有各种集成电路、逻辑、存储器、和/或软件的电子器件。该集成电路可以包括固件形式的存储程序指令的芯片、数字信号处理器(DSP)、定义为专用集成电路(ASIC)的芯片、和/或执行程序指令(例如,软件)的一个或多个微处理器或微控制器。程序指令可以是以各种不同的设置(或程序文件)形式输送到控制器或系统的指令,不同的设置(或程序文件)定义用于在半导体晶片上或针对半导体晶片进行特定处理的操作参数。在一些实施方案中,所述操作参数可以是由工艺工程师定义的用以完成在晶片的一个或多个(种)层、材料、金属、氧化物、硅、二氧化硅、表面、电路和/或管芯的制造过程中的一个或多个处理步骤的配方的一部分。
在一些实施方案中,控制器429可以是与系统集成、耦接或者说是通过网络连接系统或它们的组合的计算机的一部分或者与该计算机耦接。例如,控制器429可以在“云端”或者是晶片厂(fab)主计算机系统的全部或一部分,它们可以允许远程访问晶片处理。计算机可以启用对系统的远程访问以监测制造操作的当前进程,检查过去的制造操作的历史,检查多个制造操作的趋势或性能标准,以改变当前处理的参数,设置处理步骤以跟随当前的处理或者开始新的工艺。在一些实施例中,远程计算机(例如,服务器)可以通过网络给系统提供工艺配方,网络可以包括本地网络或互联网。远程计算机可以包括允许输入或编程参数和/或设置的用户界面,这些参数和/或设置然后从远程计算机传输到系统。在一些示例中,控制器接收数据形式的指令,这些指令指明在一个或多个操作期间将要执行的每个处理步骤的参数。应当理解,这些参数可以针对将要执行的工艺类型以及工具类型,控制器被配置成连接或控制该工具类型。因此,如上所述,控制器可以例如通过包括一个或多个分立的控制器而分布,这些分立的控制器通过网络连接在一起并且朝着共同的目标(例如,本文所述的工艺和控制)工作。用于这些目的的分布式控制器的实例将是与一个或多个远程集成电路(例如,在平台水平或作为远程计算机的一部分)通信的在室内的一个或多个集成电路,它们结合以控制室内的工艺。
示例性系统可以包括但不限于等离子体蚀刻室或模块、沉积室或模块、旋转冲洗室或模块、金属电镀室或模块、清洁室或模块、倒角边缘蚀刻室或模块、PVD室或模块、CVD室或模块、ALD室或模块、原子层蚀刻(ALE)室或模块、离子注入室或模块、轨道室或模块、以及在半导体晶片的制备和/或制造中可以关联的或使用的任何其他的半导体处理系统。
如上所述,根据工具将要执行的一个或多个工艺步骤,控制器可以与一个或多个其他的工具电路或模块、其他工具组件、组合工具、其他工具界面、相邻的工具、邻接工具、位于整个工厂中的工具、主机、另一个控制器、或者将晶片的容器往来于半导体制造工厂中的工具位置和/或装载口搬运的材料搬运中使用的工具通信。
控制器429可以包括不同的程序。衬底定位程序可包括用于控制室组件的程序代码,所述室组件用于将衬底加载到基座或卡盘上并控制衬底和室的其他部件例如气体入口和/或靶之间的间隔。工艺气体控制程序可包括用于控制气体组成、流率、脉冲时间以及任选地用于在沉积之前使气体流入室以稳定室中的压力的代码。压力控制程序可包括用于通过调节例如室中的排气系统中的节流阀而控制室中的压力的代码。加热器控制程序可包括用于控制用于加热衬底的加热单元的电流的代码。或者,所述加热器控制程序可控制传热气体例如氦气向晶片卡盘的输送。
可在沉积过程中被监控的室传感器的示例包括质量流量控制器、压力传感器例如压力计和位于基座或卡盘中的热电偶。经适当编程的反馈和控制算法可与来自这些传感器的数据一起用于维持所需的工艺条件。
上述内容描述了在单室或多室半导体加工工具中实施的本发明的实施方案。本文描述的装置和工艺可以与光刻图案化工具或工艺结合使用,例如,用于制备或制造半导体器件、显示器、LED、光伏电池板等。通常,虽然不是必要地,这些工具/过程将在共同的制造设施中一起使用或操作。膜的光刻图案化通常包括以下步骤中的一些或所有,每个步骤启用多个可行的工具:(1)使用旋涂或喷涂工具在工件,即,衬底上涂覆光致抗蚀剂;(2)使用热板或加热炉或紫外线固化工具固化光致抗蚀剂;(3)使用例如晶片步进曝光机之类的工具使光致抗蚀剂暴露于可见光或紫外线或X射线;(4)使抗蚀剂显影以便选择性地去除抗蚀剂并且从而使用例如湿式清洗台之类的工具将其图案化;(5)通过使用干式或等离子体辅助蚀刻工具将抗蚀剂图案转印到下方的膜或工件上;并且(6)使用例如射频或微波等离子体抗蚀剂剥离器之类的工具去除抗蚀剂。

Claims (14)

1.一种方法,其包括:
在衬底上提供3-D结构,所述3-D结构包括以阶梯状图案布置的金属线、覆盖所述阶梯状图案的介电材料、以及竖直定向特征,所述竖直定向特征具有特征侧壁和特征底部并提供通向在所述特征底部的金属线的流体通路;
在所述竖直定向特征中沉积金属保形层;
在第一抑制操作中以第一流率和第一暴露时间将所述金属保形层暴露于抑制物质;
在所述第一抑制操作之后,在第一非保形沉积操作中优先在所述竖直定向特征的所述底部沉积金属,其中在所述第一非保形沉积操作期间所述衬底的温度至少为400℃;
在所述第一非保形沉积操作之后,在第二抑制操作中以第二流率和第二暴露时间将所述竖直定向特征暴露于抑制物质,其中所述第二流率低于所述第一流率和/或所述第二暴露时间短于所述第一暴露时间;
并且在所述第二抑制操作之后,在第二非保形沉积操作中,在至少400℃的衬底温度下在所述特征中沉积金属。
2.根据权利要求1所述的方法,其中所述金属是钨、钴、钼和钌中的一种。
3.根据权利要求1或2所述的方法,其中优先在所述竖直定向特征的所述底部沉积金属包括:将所述特征暴露于金属前体和还原剂,其中还原剂比金属前体的体积比至少为30:1。
4.根据权利要求1-3中任一项所述的方法,其中优先在所述竖直定向特征的所述底部沉积金属包括:将所述特征以不超过100sccm的流率暴露于金属前体。
5.根据上述权利要求中任一项所述的方法,其中所述特征是3D NAND设备中的互连特征。
6.根据上述权利要求中任一项所述的方法,其中,在沉积期间,所述金属是钨,并且所述衬底温度至少为430℃。
7.根据权利要求1-5中任一项所述的方法,其中,在沉积期间,所述金属是钼,并且所述衬底温度至少为600℃。
8.根据上述权利要求中任一项所述的方法,其中,所述抑制物质是含氮气体或等离子体物质。
9.根据上述权利要求中的任一项所述的方法,其中,所述第一禁止操作处理所述特征的大部分。
10.根据上述权利要求中任一项所述的方法,其中,所述第一抑制操作处理所述特征深度的至少70%。
11.根据上述权利要求中任一项所述的方法,其中在所述第一抑制操作期间的衬底温度不同于在所述第二抑制操作期间的衬底温度。
12.一种用于处理衬底的装置,所述装置包括:
(a)处理室,其包括至少一个站,所述站具有被配置为保持衬底的基座;
(b)用于耦合至真空的至少一个出口;
(c)耦合到一个或多个工艺气体源的一个或多个工艺气体入口;和
(d)用于控制所述装置中的操作的控制器,其包括机器可读指令,所述机器可读指令用于:
在第一抑制操作中以第一流率和第一暴露时间将抑制物质引入所述处理室;
在所述第一抑制操作之后,在第一非保形沉积操作中,引入金属前体和还原剂以沉积金属,其中所述衬底在其上的所述基座的温度至少为400℃;
在所述第一非保形沉积操作之后,在第二抑制操作中,以第二流率和第二暴露时间将抑制物质引入所述处理室,其中所述第二流率低于所述第一流率和/或所述第二暴露时间短于所述第一暴露时间;以及
在所述第二抑制操作之后,在第二非保形沉积操作中,引入金属前体和还原剂以沉积金属,其中所述衬底在其上的所述基座的温度为至少400℃。
13.根据权利要求12所述的装置,其中在所述第一和第二非保形沉积操作期间,还原剂比钨前体的体积比至少为30:1。
14.一种方法,其包括:
在衬底上的特征中沉积金属保形层;
处理所述金属保形层的部分以抑制随后的钨成核;
在处理所述保形层的所述部分后,优先在所述特征的所述底部沉积钨,其中在所述沉积过程中所述衬底的温度至少为400℃;以及
重复所述处理和沉积操作一次或多次以用金属填充所述特征。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115074693A (zh) * 2022-07-22 2022-09-20 海朴精密材料(苏州)有限责任公司 一种超高纯钼靶坯及其制备方法

Families Citing this family (165)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US20160376700A1 (en) 2013-02-01 2016-12-29 Asm Ip Holding B.V. System for treatment of deposition reactor
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
KR102546317B1 (ko) 2016-11-15 2023-06-21 에이에스엠 아이피 홀딩 비.브이. 기체 공급 유닛 및 이를 포함하는 기판 처리 장치
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
KR20190009245A (ko) 2017-07-18 2019-01-28 에이에스엠 아이피 홀딩 비.브이. 반도체 소자 구조물 형성 방법 및 관련된 반도체 소자 구조물
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
KR102597978B1 (ko) 2017-11-27 2023-11-06 에이에스엠 아이피 홀딩 비.브이. 배치 퍼니스와 함께 사용하기 위한 웨이퍼 카세트를 보관하기 위한 보관 장치
US11639811B2 (en) 2017-11-27 2023-05-02 Asm Ip Holding B.V. Apparatus including a clean mini environment
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
TW202325889A (zh) 2018-01-19 2023-07-01 荷蘭商Asm 智慧財產控股公司 沈積方法
KR20200108016A (ko) 2018-01-19 2020-09-16 에이에스엠 아이피 홀딩 비.브이. 플라즈마 보조 증착에 의해 갭 충진 층을 증착하는 방법
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
US11685991B2 (en) 2018-02-14 2023-06-27 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
KR102636427B1 (ko) 2018-02-20 2024-02-13 에이에스엠 아이피 홀딩 비.브이. 기판 처리 방법 및 장치
US10975470B2 (en) 2018-02-23 2021-04-13 Asm Ip Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
KR102646467B1 (ko) 2018-03-27 2024-03-11 에이에스엠 아이피 홀딩 비.브이. 기판 상에 전극을 형성하는 방법 및 전극을 포함하는 반도체 소자 구조
KR102596988B1 (ko) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. 기판 처리 방법 및 그에 의해 제조된 장치
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
KR102568797B1 (ko) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. 기판 처리 시스템
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
WO2020003000A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
WO2020002995A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
KR20200030162A (ko) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. 박막 증착 방법
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
CN110970344A (zh) 2018-10-01 2020-04-07 Asm Ip控股有限公司 衬底保持设备、包含所述设备的系统及其使用方法
KR102592699B1 (ko) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. 기판 지지 유닛 및 이를 포함하는 박막 증착 장치와 기판 처리 장치
KR102546322B1 (ko) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치 및 기판 처리 방법
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
KR20200051105A (ko) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. 기판 지지 유닛 및 이를 포함하는 기판 처리 장치
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
KR102636428B1 (ko) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치를 세정하는 방법
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
JP2020096183A (ja) 2018-12-14 2020-06-18 エーエスエム・アイピー・ホールディング・ベー・フェー 窒化ガリウムの選択的堆積を用いてデバイス構造体を形成する方法及びそのためのシステム
TWI819180B (zh) 2019-01-17 2023-10-21 荷蘭商Asm 智慧財產控股公司 藉由循環沈積製程於基板上形成含過渡金屬膜之方法
JP2020136677A (ja) 2019-02-20 2020-08-31 エーエスエム・アイピー・ホールディング・ベー・フェー 基材表面内に形成された凹部を充填するための周期的堆積方法および装置
TW202044325A (zh) 2019-02-20 2020-12-01 荷蘭商Asm Ip私人控股有限公司 填充一基板之一表面內所形成的一凹槽的方法、根據其所形成之半導體結構、及半導體處理設備
KR20200102357A (ko) 2019-02-20 2020-08-31 에이에스엠 아이피 홀딩 비.브이. 3-d nand 응용의 플러그 충진체 증착용 장치 및 방법
TW202100794A (zh) 2019-02-22 2021-01-01 荷蘭商Asm Ip私人控股有限公司 基材處理設備及處理基材之方法
KR20200108248A (ko) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. SiOCN 층을 포함한 구조체 및 이의 형성 방법
KR20200108242A (ko) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. 실리콘 질화물 층을 선택적으로 증착하는 방법, 및 선택적으로 증착된 실리콘 질화물 층을 포함하는 구조체
KR20200116033A (ko) 2019-03-28 2020-10-08 에이에스엠 아이피 홀딩 비.브이. 도어 개방기 및 이를 구비한 기판 처리 장치
KR20200116855A (ko) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. 반도체 소자를 제조하는 방법
KR20200123380A (ko) 2019-04-19 2020-10-29 에이에스엠 아이피 홀딩 비.브이. 층 형성 방법 및 장치
KR20200125453A (ko) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. 기상 반응기 시스템 및 이를 사용하는 방법
KR20200130121A (ko) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. 딥 튜브가 있는 화학물질 공급원 용기
KR20200130652A (ko) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. 표면 상에 재료를 증착하는 방법 및 본 방법에 따라 형성된 구조
JP2020188255A (ja) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー.ブイ. ウェハボートハンドリング装置、縦型バッチ炉および方法
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
KR20200141002A (ko) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. 배기 가스 분석을 포함한 기상 반응기 시스템을 사용하는 방법
KR20200143254A (ko) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. 개질 가스를 사용하여 전자 구조를 형성하는 방법, 상기 방법을 수행하기 위한 시스템, 및 상기 방법을 사용하여 형성되는 구조
KR20210005515A (ko) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치용 온도 제어 조립체 및 이를 사용하는 방법
JP2021015791A (ja) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー.ブイ. 同軸導波管を用いたプラズマ装置、基板処理方法
CN112216646A (zh) 2019-07-10 2021-01-12 Asm Ip私人控股有限公司 基板支撑组件及包括其的基板处理装置
KR20210010307A (ko) 2019-07-16 2021-01-27 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
KR20210010820A (ko) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. 실리콘 게르마늄 구조를 형성하는 방법
KR20210010816A (ko) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. 라디칼 보조 점화 플라즈마 시스템 및 방법
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
CN112309843A (zh) 2019-07-29 2021-02-02 Asm Ip私人控股有限公司 实现高掺杂剂掺入的选择性沉积方法
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US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
KR20210018759A (ko) 2019-08-05 2021-02-18 에이에스엠 아이피 홀딩 비.브이. 화학물질 공급원 용기를 위한 액체 레벨 센서
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
JP2021031769A (ja) 2019-08-21 2021-03-01 エーエスエム アイピー ホールディング ビー.ブイ. 成膜原料混合ガス生成装置及び成膜装置
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
KR20210024423A (ko) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. 홀을 구비한 구조체를 형성하기 위한 방법
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
KR20210029090A (ko) 2019-09-04 2021-03-15 에이에스엠 아이피 홀딩 비.브이. 희생 캡핑 층을 이용한 선택적 증착 방법
KR20210029663A (ko) 2019-09-05 2021-03-16 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
CN112593212B (zh) 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 通过循环等离子体增强沉积工艺形成拓扑选择性氧化硅膜的方法
TW202129060A (zh) 2019-10-08 2021-08-01 荷蘭商Asm Ip控股公司 基板處理裝置、及基板處理方法
KR20210043460A (ko) 2019-10-10 2021-04-21 에이에스엠 아이피 홀딩 비.브이. 포토레지스트 하부층을 형성하기 위한 방법 및 이를 포함한 구조체
KR20210045930A (ko) 2019-10-16 2021-04-27 에이에스엠 아이피 홀딩 비.브이. 실리콘 산화물의 토폴로지-선택적 막의 형성 방법
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
KR20210047808A (ko) 2019-10-21 2021-04-30 에이에스엠 아이피 홀딩 비.브이. 막을 선택적으로 에칭하기 위한 장치 및 방법
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
KR20210054983A (ko) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. 도핑된 반도체 층을 갖는 구조체 및 이를 형성하기 위한 방법 및 시스템
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
KR20210062561A (ko) 2019-11-20 2021-05-31 에이에스엠 아이피 홀딩 비.브이. 기판의 표면 상에 탄소 함유 물질을 증착하는 방법, 상기 방법을 사용하여 형성된 구조물, 및 상기 구조물을 형성하기 위한 시스템
KR20210065848A (ko) 2019-11-26 2021-06-04 에이에스엠 아이피 홀딩 비.브이. 제1 유전체 표면과 제2 금속성 표면을 포함한 기판 상에 타겟 막을 선택적으로 형성하기 위한 방법
CN112951697A (zh) 2019-11-26 2021-06-11 Asm Ip私人控股有限公司 基板处理设备
CN112885693A (zh) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 基板处理设备
CN112885692A (zh) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 基板处理设备
JP2021090042A (ja) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー.ブイ. 基板処理装置、基板処理方法
KR20210070898A (ko) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
JP2021097227A (ja) 2019-12-17 2021-06-24 エーエスエム・アイピー・ホールディング・ベー・フェー 窒化バナジウム層および窒化バナジウム層を含む構造体を形成する方法
US11527403B2 (en) 2019-12-19 2022-12-13 Asm Ip Holding B.V. Methods for filling a gap feature on a substrate surface and related semiconductor structures
KR20210089077A (ko) 2020-01-06 2021-07-15 에이에스엠 아이피 홀딩 비.브이. 가스 공급 어셈블리, 이의 구성 요소, 및 이를 포함하는 반응기 시스템
KR20210095050A (ko) 2020-01-20 2021-07-30 에이에스엠 아이피 홀딩 비.브이. 박막 형성 방법 및 박막 표면 개질 방법
TW202130846A (zh) 2020-02-03 2021-08-16 荷蘭商Asm Ip私人控股有限公司 形成包括釩或銦層的結構之方法
KR20210100010A (ko) 2020-02-04 2021-08-13 에이에스엠 아이피 홀딩 비.브이. 대형 물품의 투과율 측정을 위한 방법 및 장치
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
US11781243B2 (en) 2020-02-17 2023-10-10 Asm Ip Holding B.V. Method for depositing low temperature phosphorous-doped silicon
KR20210116240A (ko) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. 조절성 접합부를 갖는 기판 핸들링 장치
US11876356B2 (en) 2020-03-11 2024-01-16 Asm Ip Holding B.V. Lockout tagout assembly and system and method of using same
KR20210117157A (ko) 2020-03-12 2021-09-28 에이에스엠 아이피 홀딩 비.브이. 타겟 토폴로지 프로파일을 갖는 층 구조를 제조하기 위한 방법
KR20210124042A (ko) 2020-04-02 2021-10-14 에이에스엠 아이피 홀딩 비.브이. 박막 형성 방법
TW202146689A (zh) 2020-04-03 2021-12-16 荷蘭商Asm Ip控股公司 阻障層形成方法及半導體裝置的製造方法
TW202145344A (zh) 2020-04-08 2021-12-01 荷蘭商Asm Ip私人控股有限公司 用於選擇性蝕刻氧化矽膜之設備及方法
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
KR20210132600A (ko) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. 바나듐, 질소 및 추가 원소를 포함한 층을 증착하기 위한 방법 및 시스템
TW202146831A (zh) 2020-04-24 2021-12-16 荷蘭商Asm Ip私人控股有限公司 垂直批式熔爐總成、及用於冷卻垂直批式熔爐之方法
CN113555279A (zh) 2020-04-24 2021-10-26 Asm Ip私人控股有限公司 形成含氮化钒的层的方法及包含其的结构
KR20210134226A (ko) 2020-04-29 2021-11-09 에이에스엠 아이피 홀딩 비.브이. 고체 소스 전구체 용기
KR20210134869A (ko) 2020-05-01 2021-11-11 에이에스엠 아이피 홀딩 비.브이. Foup 핸들러를 이용한 foup의 빠른 교환
KR20210141379A (ko) 2020-05-13 2021-11-23 에이에스엠 아이피 홀딩 비.브이. 반응기 시스템용 레이저 정렬 고정구
TW202147383A (zh) 2020-05-19 2021-12-16 荷蘭商Asm Ip私人控股有限公司 基材處理設備
KR20210145078A (ko) 2020-05-21 2021-12-01 에이에스엠 아이피 홀딩 비.브이. 다수의 탄소 층을 포함한 구조체 및 이를 형성하고 사용하는 방법
TW202218133A (zh) 2020-06-24 2022-05-01 荷蘭商Asm Ip私人控股有限公司 形成含矽層之方法
TW202217953A (zh) 2020-06-30 2022-05-01 荷蘭商Asm Ip私人控股有限公司 基板處理方法
TW202219628A (zh) 2020-07-17 2022-05-16 荷蘭商Asm Ip私人控股有限公司 用於光微影之結構與方法
TW202204662A (zh) 2020-07-20 2022-02-01 荷蘭商Asm Ip私人控股有限公司 用於沉積鉬層之方法及系統
KR20220027026A (ko) 2020-08-26 2022-03-07 에이에스엠 아이피 홀딩 비.브이. 금속 실리콘 산화물 및 금속 실리콘 산질화물 층을 형성하기 위한 방법 및 시스템
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
TW202229613A (zh) 2020-10-14 2022-08-01 荷蘭商Asm Ip私人控股有限公司 於階梯式結構上沉積材料的方法
KR20220053482A (ko) 2020-10-22 2022-04-29 에이에스엠 아이피 홀딩 비.브이. 바나듐 금속을 증착하는 방법, 구조체, 소자 및 증착 어셈블리
TW202223136A (zh) 2020-10-28 2022-06-16 荷蘭商Asm Ip私人控股有限公司 用於在基板上形成層之方法、及半導體處理系統
TW202235675A (zh) 2020-11-30 2022-09-16 荷蘭商Asm Ip私人控股有限公司 注入器、及基板處理設備
CN114639631A (zh) 2020-12-16 2022-06-17 Asm Ip私人控股有限公司 跳动和摆动测量固定装置
TW202231903A (zh) 2020-12-22 2022-08-16 荷蘭商Asm Ip私人控股有限公司 過渡金屬沉積方法、過渡金屬層、用於沉積過渡金屬於基板上的沉積總成
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
USD1023959S1 (en) 2021-05-11 2024-04-23 Asm Ip Holding B.V. Electrode for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate
WO2023038905A1 (en) * 2021-09-10 2023-03-16 Lam Research Corporation Process gas ramp during semiconductor processing
WO2023136854A1 (en) * 2022-01-11 2023-07-20 Sandisk Technologies Llc Methods and apparatuses for forming semiconductor devices containing tungsten layers using a tungsten growth suppressant
US20230326744A1 (en) * 2022-04-06 2023-10-12 Applied Materials, Inc. Field suppressed metal gapfill
US20240047267A1 (en) * 2022-08-05 2024-02-08 Applied Materials, Inc. Tungsten gap fill with hydrogen plasma treatment
US20240088071A1 (en) * 2022-09-14 2024-03-14 Applied Materials, Inc. Methods for forming metal gapfill with low resistivity

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339023B1 (en) * 1998-04-10 2002-01-15 Applied Materials Inc. Method of reducing stress in blanket tungsten film formed by chemical vapor deposition process
EP1672687A1 (en) * 2004-12-17 2006-06-21 Interuniversitair Microelektronica Centrum ( Imec) Formation of deep airgap trenches and related applications
EP2779224A2 (en) * 2013-03-15 2014-09-17 Applied Materials, Inc. Methods for producing interconnects in semiconductor devices
JP2014183185A (ja) * 2013-03-19 2014-09-29 Toshiba Corp 半導体装置の製造方法および半導体装置
CN104081502A (zh) * 2012-02-17 2014-10-01 东京毅力科创株式会社 半导体器件的制造方法
CN104272440A (zh) * 2012-03-27 2015-01-07 诺发系统公司 用核化抑制的钨特征填充
US20150091175A1 (en) * 2013-09-27 2015-04-02 Manish Chandhok Interconnects with fully clad lines
CN104513973A (zh) * 2013-09-30 2015-04-15 朗姆研究公司 通过脉冲低频射频功率获得高选择性和低应力碳硬膜
CN104975268A (zh) * 2015-06-03 2015-10-14 武汉新芯集成电路制造有限公司 一种金属钨薄膜的制备方法
CN105405764A (zh) * 2014-07-25 2016-03-16 中国科学院微电子研究所 半导体器件制造方法
CN106169440A (zh) * 2015-05-18 2016-11-30 朗姆研究公司 用多阶段核化抑制填充特征

Family Cites Families (178)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4714520A (en) 1985-07-25 1987-12-22 Advanced Micro Devices, Inc. Method for filling a trench in an integrated circuit structure without producing voids
US4746375A (en) 1987-05-08 1988-05-24 General Electric Company Activation of refractory metal surfaces for electroless plating
JPH0794488B2 (ja) 1987-09-07 1995-10-11 ダイセル化学工業株式会社 光学活性な重合用触媒及び光学活性な高分子の合成方法
JPH0225568A (ja) 1988-07-15 1990-01-29 Hitachi Ltd 微細孔の金属穴埋め方法
US5112439A (en) 1988-11-30 1992-05-12 Mcnc Method for selectively depositing material on substrates
JPH02187031A (ja) 1989-01-14 1990-07-23 Sharp Corp 半導体装置
GB8907898D0 (en) 1989-04-07 1989-05-24 Inmos Ltd Semiconductor devices and fabrication thereof
SG59964A1 (en) 1989-09-26 1999-02-22 Canon Kk Process for forming deposited film and process for preparing semiconductor device
JPH03110840A (ja) 1989-09-26 1991-05-10 Canon Inc 堆積膜形成法
US5043299B1 (en) 1989-12-01 1997-02-25 Applied Materials Inc Process for selective deposition of tungsten on semiconductor wafer
EP1069207A3 (en) 1990-01-08 2003-05-14 Lsi Logic Corporation In-situ etch method for for cleaning a CVD chamber
JPH04142061A (ja) 1990-10-02 1992-05-15 Sony Corp タングステンプラグの形成方法
US5250467A (en) 1991-03-29 1993-10-05 Applied Materials, Inc. Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer
JPH05226280A (ja) 1992-02-14 1993-09-03 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
CA2067565C (en) 1992-04-29 1999-02-16 Ismail T. Emesh Deposition of tungsten
US5370739A (en) 1992-06-15 1994-12-06 Materials Research Corporation Rotating susceptor semiconductor wafer processing cluster tool module useful for tungsten CVD
JP3216345B2 (ja) 1993-04-06 2001-10-09 ソニー株式会社 半導体装置及びその作製方法
US5616208A (en) 1993-09-17 1997-04-01 Tokyo Electron Limited Vacuum processing apparatus, vacuum processing method, and method for cleaning the vacuum processing apparatus
JP3014019B2 (ja) 1993-11-26 2000-02-28 日本電気株式会社 半導体装置の製造方法
KR0179677B1 (ko) 1993-12-28 1999-04-15 사토 후미오 반도체장치 및 그 제조방법
JP3291889B2 (ja) 1994-02-15 2002-06-17 ソニー株式会社 ドライエッチング方法
US5489552A (en) 1994-12-30 1996-02-06 At&T Corp. Multiple layer tungsten deposition process
US6001729A (en) 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
US5504038A (en) 1995-05-25 1996-04-02 United Microelectronics Corporation Method for selective tungsten sidewall and bottom contact formation
JPH0922896A (ja) 1995-07-07 1997-01-21 Toshiba Corp 金属膜の選択的形成方法
US6017818A (en) 1996-01-22 2000-01-25 Texas Instruments Incorporated Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US5963833A (en) 1996-07-03 1999-10-05 Micron Technology, Inc. Method for cleaning semiconductor wafers and
JP3869089B2 (ja) 1996-11-14 2007-01-17 株式会社日立製作所 半導体集積回路装置の製造方法
US6184158B1 (en) 1996-12-23 2001-02-06 Lam Research Corporation Inductively coupled plasma CVD
US5804249A (en) 1997-02-07 1998-09-08 Lsi Logic Corporation Multistep tungsten CVD process with amorphization step
US5866483A (en) 1997-04-04 1999-02-02 Applied Materials, Inc. Method for anisotropically etching tungsten using SF6, CHF3, and N2
US6861356B2 (en) 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
JPH11260759A (ja) 1998-03-12 1999-09-24 Fujitsu Ltd 半導体装置の製造方法
US6432830B1 (en) 1998-05-15 2002-08-13 Applied Materials, Inc. Semiconductor fabrication process
US6066366A (en) 1998-07-22 2000-05-23 Applied Materials, Inc. Method for depositing uniform tungsten layers by CVD
US6143082A (en) 1998-10-08 2000-11-07 Novellus Systems, Inc. Isolation of incompatible processes in a multi-station processing chamber
US6037263A (en) 1998-11-05 2000-03-14 Vanguard International Semiconductor Corporation Plasma enhanced CVD deposition of tungsten and tungsten compounds
US6245654B1 (en) 1999-03-31 2001-06-12 Taiwan Semiconductor Manufacturing Company, Ltd Method for preventing tungsten contact/via plug loss after a backside pressure fault
US6355558B1 (en) 1999-06-10 2002-03-12 Texas Instruments Incorporated Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films
US6391785B1 (en) 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6503843B1 (en) 1999-09-21 2003-01-07 Applied Materials, Inc. Multistep chamber cleaning and film deposition process using a remote plasma that also enhances film gap fill
US6610151B1 (en) 1999-10-02 2003-08-26 Uri Cohen Seed layers for interconnects and methods and apparatus for their fabrication
US6924226B2 (en) 1999-10-02 2005-08-02 Uri Cohen Methods for making multiple seed layers for metallic interconnects
AU1208201A (en) 1999-10-15 2001-04-30 Asm America, Inc. Method for depositing nanolaminate thin films on sensitive surfaces
KR100338941B1 (ko) 1999-11-26 2002-05-31 박종섭 반도체소자의 컨택 형성방법
EP1290746B1 (en) 2000-05-18 2012-04-25 Corning Incorporated High performance solid electrolyte fuel cells
US7253076B1 (en) 2000-06-08 2007-08-07 Micron Technologies, Inc. Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
US6620723B1 (en) 2000-06-27 2003-09-16 Applied Materials, Inc. Formation of boride barrier layers using chemisorption techniques
JP2002016066A (ja) 2000-06-27 2002-01-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7405158B2 (en) 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US6740591B1 (en) 2000-11-16 2004-05-25 Intel Corporation Slurry and method for chemical mechanical polishing of copper
KR100399417B1 (ko) 2001-01-08 2003-09-26 삼성전자주식회사 반도체 집적 회로의 제조 방법
US6613656B2 (en) 2001-02-13 2003-09-02 Micron Technology, Inc. Sequential pulse deposition
KR20020072996A (ko) 2001-03-14 2002-09-19 주성엔지니어링(주) 금속 플러그 형성방법
JP2002343787A (ja) 2001-05-17 2002-11-29 Research Institute Of Innovative Technology For The Earth プラズマ処理装置およびそのクリーニング方法
US7141494B2 (en) 2001-05-22 2006-11-28 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US7955972B2 (en) 2001-05-22 2011-06-07 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US7005372B2 (en) 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US6686278B2 (en) 2001-06-19 2004-02-03 United Microelectronics Corp. Method for forming a plug metal layer
JP2003022985A (ja) 2001-07-10 2003-01-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法およびその製造装置
US9051641B2 (en) 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
JP2003142484A (ja) 2001-10-31 2003-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
US20030091870A1 (en) 2001-11-15 2003-05-15 Siddhartha Bhowmik Method of forming a liner for tungsten plugs
US6998014B2 (en) 2002-01-26 2006-02-14 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US6566250B1 (en) 2002-03-18 2003-05-20 Taiwant Semiconductor Manufacturing Co., Ltd Method for forming a self aligned capping layer
US6797620B2 (en) 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture
US20030203123A1 (en) 2002-04-26 2003-10-30 Applied Materials, Inc. System and method for metal induced crystallization of polycrystalline thin film transistors
KR100446300B1 (ko) 2002-05-30 2004-08-30 삼성전자주식회사 반도체 소자의 금속 배선 형성 방법
US6790773B1 (en) 2002-08-28 2004-09-14 Novellus Systems, Inc. Process for forming barrier/seed structures for integrated circuits
US6802944B2 (en) 2002-10-23 2004-10-12 Applied Materials, Inc. High density plasma CVD process for gapfill into high aspect ratio features
WO2005003033A2 (en) 2002-12-23 2005-01-13 Applied Thin Films, Inc. Aluminum phosphate coatings
US20040134427A1 (en) 2003-01-09 2004-07-15 Derderian Garo J. Deposition chamber surface enhancement and resulting deposition chambers
US7205240B2 (en) 2003-06-04 2007-04-17 Applied Materials, Inc. HDP-CVD multistep gapfill process
KR100539274B1 (ko) 2003-07-15 2005-12-27 삼성전자주식회사 코발트 막 증착 방법
JP4606006B2 (ja) 2003-09-11 2011-01-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4256763B2 (ja) 2003-11-19 2009-04-22 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
US20050147762A1 (en) 2003-12-30 2005-07-07 Dubin Valery M. Method to fabricate amorphous electroless metal layers
KR101108304B1 (ko) 2004-02-26 2012-01-25 노벨러스 시스템즈, 인코포레이티드 질화 텅스텐의 증착
US7879710B2 (en) 2005-05-18 2011-02-01 Intermolecular, Inc. Substrate processing including a masking layer
US20060145190A1 (en) 2004-12-31 2006-07-06 Salzman David B Surface passivation for III-V compound semiconductors
KR100642750B1 (ko) 2005-01-31 2006-11-10 삼성전자주식회사 반도체 소자 및 그 제조 방법
JP4945937B2 (ja) 2005-07-01 2012-06-06 東京エレクトロン株式会社 タングステン膜の形成方法、成膜装置及び記憶媒体
KR20080050403A (ko) 2005-08-02 2008-06-05 매사추세츠 인스티튜트 오브 테크놀로지 표면 침착물을 제거하고 화학 증착 챔버 내부의 내면을부동태화하는 방법
JP2009503270A (ja) 2005-08-02 2009-01-29 マサチューセッツ インスティテュート オブ テクノロジー 表面沈着物を除去するためのnf3の使用方法
US7517798B2 (en) 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US20070066060A1 (en) 2005-09-19 2007-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and fabrication methods thereof
US7524765B2 (en) 2005-11-02 2009-04-28 Intel Corporation Direct tailoring of the composition and density of ALD films
US20070117396A1 (en) 2005-11-22 2007-05-24 Dingjun Wu Selective etching of titanium nitride with xenon difluoride
JP4967354B2 (ja) 2006-01-31 2012-07-04 東京エレクトロン株式会社 シード膜の成膜方法、プラズマ成膜装置及び記憶媒体
US7368394B2 (en) 2006-02-27 2008-05-06 Applied Materials, Inc. Etch methods to form anisotropic features for high aspect ratio applications
US7276796B1 (en) 2006-03-15 2007-10-02 International Business Machines Corporation Formation of oxidation-resistant seed layer for interconnect applications
US8258057B2 (en) 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
US7828504B2 (en) 2006-05-12 2010-11-09 Axcellis Technologies, Inc. Combination load lock for handling workpieces
KR100884339B1 (ko) 2006-06-29 2009-02-18 주식회사 하이닉스반도체 반도체 소자의 텅스텐막 형성방법 및 이를 이용한 텅스텐배선층 형성방법
US7355254B2 (en) 2006-06-30 2008-04-08 Intel Corporation Pinning layer for low resistivity N-type source drain ohmic contacts
MY148605A (en) 2006-08-30 2013-05-15 Lam Res Corp Processes and integrated systems for engineering a substrate surface for metal deposition
KR100757418B1 (ko) 2006-09-05 2007-09-10 삼성전자주식회사 반도체 소자 및 그 형성 방법
KR100881391B1 (ko) 2006-09-29 2009-02-05 주식회사 하이닉스반도체 반도체 소자의 게이트 형성방법
US7939455B2 (en) 2006-09-29 2011-05-10 Tokyo Electron Limited Method for forming strained silicon nitride films and a device containing such films
US7569913B2 (en) 2006-10-26 2009-08-04 Atmel Corporation Boron etch-stop layer and methods related thereto
US10037905B2 (en) 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
KR20080061978A (ko) 2006-12-28 2008-07-03 주식회사 하이닉스반도체 반도체 소자의 배선 형성방법
US20080174021A1 (en) 2007-01-18 2008-07-24 Samsung Electronics Co., Ltd. Semiconductor devices having metal interconnections, semiconductor cluster tools used in fabrication thereof and methods of fabricating the same
KR20080101745A (ko) 2007-05-15 2008-11-21 어플라이드 머티어리얼스, 인코포레이티드 텅스텐 재료들의 원자층 증착
US7655567B1 (en) 2007-07-24 2010-02-02 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US20090086521A1 (en) 2007-09-28 2009-04-02 Herner S Brad Multiple antifuse memory cells and methods to form, program, and sense the same
CN101952944B (zh) 2007-11-21 2013-01-02 朗姆研究公司 控制对含钨层的蚀刻微负载的方法及其设备
KR100939777B1 (ko) 2007-11-30 2010-01-29 주식회사 하이닉스반도체 텅스텐막 형성방법 및 이를 이용한 반도체 소자의 배선형성방법
US7772114B2 (en) 2007-12-05 2010-08-10 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US8053365B2 (en) 2007-12-21 2011-11-08 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
KR100919808B1 (ko) 2008-01-02 2009-10-01 주식회사 하이닉스반도체 반도체소자의 텅스텐막 형성방법
US20090269507A1 (en) 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US8058170B2 (en) 2008-06-12 2011-11-15 Novellus Systems, Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US7968460B2 (en) 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US8551885B2 (en) 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US20100072623A1 (en) 2008-09-19 2010-03-25 Advanced Micro Devices, Inc. Semiconductor device with improved contact plugs, and related fabrication methods
US8293647B2 (en) 2008-11-24 2012-10-23 Applied Materials, Inc. Bottom up plating by organic surface passivation and differential plating retardation
US7964502B2 (en) 2008-11-25 2011-06-21 Freescale Semiconductor, Inc. Multilayered through via
US20100144140A1 (en) 2008-12-10 2010-06-10 Novellus Systems, Inc. Methods for depositing tungsten films having low resistivity for gapfill applications
US8129270B1 (en) 2008-12-10 2012-03-06 Novellus Systems, Inc. Method for depositing tungsten film having low resistivity, low roughness and high reflectivity
KR101263856B1 (ko) 2008-12-31 2013-05-13 어플라이드 머티어리얼스, 인코포레이티드 비저항이 감소되고 표면 형태가 개선된 텅스텐 필름을 증착하는 방법
US8236691B2 (en) 2008-12-31 2012-08-07 Micron Technology, Inc. Method of high aspect ratio plug fill
US8623733B2 (en) * 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US9548228B2 (en) 2009-08-04 2017-01-17 Lam Research Corporation Void free tungsten fill in different sized features
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8124531B2 (en) 2009-08-04 2012-02-28 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US20230041794A1 (en) 2009-08-04 2023-02-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8119527B1 (en) 2009-08-04 2012-02-21 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US9034768B2 (en) 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
JP5600351B2 (ja) 2009-08-07 2014-10-01 シグマ−アルドリッチ・カンパニー、エルエルシー 高分子量アルキル−アリルコバルトトリカルボニル錯体及び誘電体薄膜を作製するためのそれらの使用
US8747684B2 (en) 2009-08-20 2014-06-10 Applied Materials, Inc. Multi-film stack etching with polymer passivation of an overlying etched layer
KR20120046786A (ko) 2009-09-02 2012-05-10 가부시키가이샤 알박 Co 막의 형성 방법 및 Cu 배선막의 형성 방법
CN102812043A (zh) 2009-11-19 2012-12-05 新加坡国立大学 用于制备t细胞受体样单克隆抗体的方法及其用途
CN101789369A (zh) 2010-01-28 2010-07-28 上海宏力半导体制造有限公司 多金属钨栅极刻蚀方法
WO2011113177A1 (en) 2010-03-17 2011-09-22 Applied Materials, Inc. Method and apparatus for remote plasma source assisted silicon-containing film deposition
JP2011199021A (ja) 2010-03-19 2011-10-06 Renesas Electronics Corp 半導体装置及びその製造方法
US9129945B2 (en) 2010-03-24 2015-09-08 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US8741394B2 (en) 2010-03-25 2014-06-03 Novellus Systems, Inc. In-situ deposition of film stacks
US8355281B2 (en) 2010-04-20 2013-01-15 Micron Technology, Inc. Flash memory having multi-level architecture
KR101340793B1 (ko) 2010-07-09 2013-12-11 노벨러스 시스템즈, 인코포레이티드 고 종횡비 특징부 내부로 텅스텐 증착하기
US8778797B2 (en) 2010-09-27 2014-07-15 Novellus Systems, Inc. Systems and methods for selective tungsten deposition in vias
US20120149213A1 (en) 2010-12-09 2012-06-14 Lakshminarayana Nittala Bottom up fill in high aspect ratio trenches
US8969823B2 (en) 2011-01-21 2015-03-03 Uchicago Argonne, Llc Microchannel plate detector and methods for their fabrication
US8916435B2 (en) 2011-09-09 2014-12-23 International Business Machines Corporation Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
TWI602283B (zh) 2012-03-27 2017-10-11 諾發系統有限公司 鎢特徵部塡充
US9330939B2 (en) 2012-03-28 2016-05-03 Applied Materials, Inc. Method of enabling seamless cobalt gap-fill
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9169556B2 (en) 2012-10-11 2015-10-27 Applied Materials, Inc. Tungsten growth modulation by controlling surface composition
US9230815B2 (en) 2012-10-26 2016-01-05 Appled Materials, Inc. Methods for depositing fluorine/carbon-free conformal tungsten
US9514983B2 (en) 2012-12-28 2016-12-06 Intel Corporation Cobalt based interconnects and methods of fabrication thereof
JP2014160757A (ja) 2013-02-20 2014-09-04 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US9048299B2 (en) 2013-03-12 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning approach to reduce via to via minimum spacing
US9082826B2 (en) 2013-05-24 2015-07-14 Lam Research Corporation Methods and apparatuses for void-free tungsten fill in three-dimensional semiconductor features
KR102291990B1 (ko) 2013-08-16 2021-08-19 어플라이드 머티어리얼스, 인코포레이티드 텅스텐 육플루오르화물(wf6) 에치백을 이용하여 텅스텐 막을 증착하기 위한 방법
US9385033B2 (en) 2013-09-27 2016-07-05 Intel Corporation Method of forming a metal from a cobalt metal precursor
KR102316440B1 (ko) 2013-10-18 2021-10-22 브룩스 오토메이션 인코퍼레이티드 공정 장치
TW201525173A (zh) 2013-12-09 2015-07-01 Applied Materials Inc 選擇性層沉積之方法
TWI672737B (zh) 2013-12-27 2019-09-21 美商蘭姆研究公司 允許低電阻率鎢特徵物填充之鎢成核程序
US9653352B2 (en) 2014-04-11 2017-05-16 Applied Materials, Inc. Methods for forming metal organic tungsten for middle of the line (MOL) applications
US20150361547A1 (en) 2014-06-13 2015-12-17 Taiwan Semiconductor Manufacturing Co., Ltd Method and apparatus for cleaning chemical vapor deposition chamber
JP6290022B2 (ja) 2014-07-17 2018-03-07 東芝メモリ株式会社 半導体装置の製造方法
US9748137B2 (en) 2014-08-21 2017-08-29 Lam Research Corporation Method for void-free cobalt gap fill
US9349637B2 (en) 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9502263B2 (en) 2014-12-15 2016-11-22 Applied Materials, Inc. UV assisted CVD AlN film for BEOL etch stop application
US9617648B2 (en) 2015-03-04 2017-04-11 Lam Research Corporation Pretreatment of nickel and cobalt liners for electrodeposition of copper into through silicon vias
US9853123B2 (en) 2015-10-28 2017-12-26 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US10535558B2 (en) 2016-02-09 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trenches
TWI613845B (zh) 2016-08-04 2018-02-01 財團法人工業技術研究院 垂直磁化自旋軌道磁性元件
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
US10242879B2 (en) 2017-04-20 2019-03-26 Lam Research Corporation Methods and apparatus for forming smooth and conformal cobalt film by atomic layer deposition
KR20220149595A (ko) 2020-03-04 2022-11-08 램 리써치 코포레이션 반응 물질 가스 펄스 전달
JP2023520675A (ja) 2020-03-27 2023-05-18 ラム リサーチ コーポレーション 核形成阻害を伴うフィーチャ充填

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339023B1 (en) * 1998-04-10 2002-01-15 Applied Materials Inc. Method of reducing stress in blanket tungsten film formed by chemical vapor deposition process
EP1672687A1 (en) * 2004-12-17 2006-06-21 Interuniversitair Microelektronica Centrum ( Imec) Formation of deep airgap trenches and related applications
CN104081502A (zh) * 2012-02-17 2014-10-01 东京毅力科创株式会社 半导体器件的制造方法
CN104272440A (zh) * 2012-03-27 2015-01-07 诺发系统公司 用核化抑制的钨特征填充
EP2779224A2 (en) * 2013-03-15 2014-09-17 Applied Materials, Inc. Methods for producing interconnects in semiconductor devices
JP2014183185A (ja) * 2013-03-19 2014-09-29 Toshiba Corp 半導体装置の製造方法および半導体装置
US20150091175A1 (en) * 2013-09-27 2015-04-02 Manish Chandhok Interconnects with fully clad lines
CN104513973A (zh) * 2013-09-30 2015-04-15 朗姆研究公司 通过脉冲低频射频功率获得高选择性和低应力碳硬膜
CN105405764A (zh) * 2014-07-25 2016-03-16 中国科学院微电子研究所 半导体器件制造方法
CN106169440A (zh) * 2015-05-18 2016-11-30 朗姆研究公司 用多阶段核化抑制填充特征
CN104975268A (zh) * 2015-06-03 2015-10-14 武汉新芯集成电路制造有限公司 一种金属钨薄膜的制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115074693A (zh) * 2022-07-22 2022-09-20 海朴精密材料(苏州)有限责任公司 一种超高纯钼靶坯及其制备方法

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