MY148605A - Processes and integrated systems for engineering a substrate surface for metal deposition - Google Patents

Processes and integrated systems for engineering a substrate surface for metal deposition

Info

Publication number
MY148605A
MY148605A MYPI20090714A MY148605A MY 148605 A MY148605 A MY 148605A MY PI20090714 A MYPI20090714 A MY PI20090714A MY 148605 A MY148605 A MY 148605A
Authority
MY
Malaysia
Prior art keywords
metal
substrate surface
copper
integrated system
processes
Prior art date
Application number
Inventor
Thie William
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/513,446 external-priority patent/US8747960B2/en
Priority claimed from US11/513,634 external-priority patent/US8771804B2/en
Priority claimed from US11/514,038 external-priority patent/US8241701B2/en
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of MY148605A publication Critical patent/MY148605A/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

THE EMBODIMENTS PROVIDE PROCESSES AND INTEGRATED SYSTEMS THAT PRODUCE A METAL-TO-METAL OR A SILICON-TO-METAL INTERFACE TO ENHANCE ELECTRO-MIGRATION PERFORMANCE, TO PROVIDE LOWER METAL RESISTIVITY, AND TO IMPROVE METAL-TO-METAL OR SILICON-TO-METAL INTERFACIAL ADHESION FOR COPPER INTERCONNECTS. AN EXEMPLARY METHOD OF PREPARING A SUBSTRATE SURFACE TO SELECTIVELY DEPOSIT A THIN LAYER OF A COBALT-ALLOY MATERIAL ON A COPPER SURFACE OF IN AN INTEGRATED SYSTEM TO IMPROVE ELECTROMIGRATION PERFORMANCE OF A COPPER INTERCONNECT IS PROVIDED. THE METHOD INCLUDES REMOVING CONTAMINANTS AND METAL OXIDES FROM THE SUBSTRATE SURFACE IN THE INTEGRATED SYSTEM, AND RECONDITIONING THE SUBSTRATE SURFACE USING A REDUCING ENVIRONMENT AFTER REMOVING CONTAMINANTS AND METAL OXIDES IN THE INTEGRATED SYSTEM. THE METHOD ALSO INCLUDES SELECTIVELY DEPOSITING THE THIN LAYER OF COBALT-ALLOY MATERIAL ON THE COPPER SURFACE OF THE COPPER INTERCONNECT IN THE INTEGRATED SYSTEM AFTER RECONDITIONING THE SUBSTRATE SURFACE. SYSTEM TO PRACTICE THE EXEMPLARY METHOD DESCRIBED ABOVE ARE ALSO PROVIDED.
MYPI20090714 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition MY148605A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/513,446 US8747960B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide
US11/513,634 US8771804B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a copper surface for selective metal deposition
US11/514,038 US8241701B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a barrier surface for copper deposition

Publications (1)

Publication Number Publication Date
MY148605A true MY148605A (en) 2013-05-15

Family

ID=41202298

Family Applications (2)

Application Number Title Priority Date Filing Date
MYPI20090714 MY148605A (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition
MYPI2012004997A MY171542A (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition

Family Applications After (1)

Application Number Title Priority Date Filing Date
MYPI2012004997A MY171542A (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition

Country Status (5)

Country Link
JP (2) JP5489717B2 (en)
CN (2) CN103107120B (en)
MY (2) MY148605A (en)
SG (1) SG174752A1 (en)
TW (1) TWI393186B (en)

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JP6842159B2 (en) * 2016-12-13 2021-03-17 サムコ株式会社 Plasma processing method
US10438846B2 (en) 2017-11-28 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Physical vapor deposition process for semiconductor interconnection structures
JP2019192892A (en) 2018-04-18 2019-10-31 東京エレクトロン株式会社 Processing system and processing method
KR102301933B1 (en) * 2018-12-26 2021-09-15 한양대학교 에리카산학협력단 Fabricating method of Semiconductor device
US20220344205A1 (en) * 2019-09-25 2022-10-27 Tokyo Electron Limited Substrate liquid processing method and substate liquid processing apparatus

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US6144099A (en) * 1999-03-30 2000-11-07 Advanced Micro Devices, Inc. Semiconductor metalization barrier
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Also Published As

Publication number Publication date
CN101558186B (en) 2015-01-14
JP5489717B2 (en) 2014-05-14
TW200832556A (en) 2008-08-01
TWI393186B (en) 2013-04-11
JP2014099627A (en) 2014-05-29
JP5820870B2 (en) 2015-11-24
CN103107120B (en) 2016-06-08
MY171542A (en) 2019-10-17
SG174752A1 (en) 2011-10-28
CN101558186A (en) 2009-10-14
JP2010503205A (en) 2010-01-28
CN103107120A (en) 2013-05-15

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