WO2008011403A3 - New scheme for copper filling in vias and trenches - Google Patents

New scheme for copper filling in vias and trenches Download PDF

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Publication number
WO2008011403A3
WO2008011403A3 PCT/US2007/073676 US2007073676W WO2008011403A3 WO 2008011403 A3 WO2008011403 A3 WO 2008011403A3 US 2007073676 W US2007073676 W US 2007073676W WO 2008011403 A3 WO2008011403 A3 WO 2008011403A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
metal material
trenches
vias
metal
Prior art date
Application number
PCT/US2007/073676
Other languages
French (fr)
Other versions
WO2008011403A2 (en
Inventor
Mehul Naik
Original Assignee
Applied Materials Inc
Mehul Naik
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc, Mehul Naik filed Critical Applied Materials Inc
Publication of WO2008011403A2 publication Critical patent/WO2008011403A2/en
Publication of WO2008011403A3 publication Critical patent/WO2008011403A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
    • C23C18/08—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of metallic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Thermal Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemically Coating (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

Embodiments of the present invention generally relate to methods and apparatuses using supercritical fluids and/or dense fluids to deposit a metal material on the surface of a substrate. In one embodiment, a metal material layer is deposited by applying a supercritical fluid, a dense fluid, or combinations thereof and a metal-containing precursor to the surface of a substrate inside a substrate processing chamber. In another embodiment, a first metal material and a second metal material is sequentially deposited and annealing is performed to form a metal alloy material on the surface of a substrate. In still another embodiment, a copper material layer is deposited by applying a supercritical fluid, a dense fluid, or combinations thereof and a copper containing precursor to the surface of the substrate.
PCT/US2007/073676 2006-07-18 2007-07-17 New scheme for copper filling in vias and trenches WO2008011403A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/488,514 US20080124924A1 (en) 2006-07-18 2006-07-18 Scheme for copper filling in vias and trenches
US11/488,514 2006-07-18

Publications (2)

Publication Number Publication Date
WO2008011403A2 WO2008011403A2 (en) 2008-01-24
WO2008011403A3 true WO2008011403A3 (en) 2008-10-09

Family

ID=38957544

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/073676 WO2008011403A2 (en) 2006-07-18 2007-07-17 New scheme for copper filling in vias and trenches

Country Status (3)

Country Link
US (1) US20080124924A1 (en)
TW (1) TW200814199A (en)
WO (1) WO2008011403A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1909320A1 (en) * 2006-10-05 2008-04-09 ST Microelectronics Crolles 2 SAS Copper diffusion barrier
US8293647B2 (en) * 2008-11-24 2012-10-23 Applied Materials, Inc. Bottom up plating by organic surface passivation and differential plating retardation
US8173523B2 (en) * 2009-10-09 2012-05-08 Sumco Corporation Method of removing heavy metal in semiconductor substrate
US8658533B2 (en) 2011-03-10 2014-02-25 International Business Machines Corporation Semiconductor interconnect structure with multi-layered seed layer providing enhanced reliability and minimizing electromigration
US8648465B2 (en) 2011-09-28 2014-02-11 International Business Machines Corporation Semiconductor interconnect structure having enhanced performance and reliability
US8765602B2 (en) 2012-08-30 2014-07-01 International Business Machines Corporation Doping of copper wiring structures in back end of line processing
US20140061915A1 (en) * 2012-08-30 2014-03-06 International Business Machines Corporation Prevention of thru-substrate via pistoning using highly doped copper alloy seed layer
US9368448B2 (en) 2013-12-20 2016-06-14 Applied Materials, Inc. Metal-containing films as dielectric capping barrier for advanced interconnects
US9828673B2 (en) * 2014-09-22 2017-11-28 Svt Associates, Inc. Method of forming very reactive metal layers by a high vacuum plasma enhanced atomic layer deposition system
KR102492733B1 (en) 2017-09-29 2023-01-27 삼성디스플레이 주식회사 Copper plasma etching method and manufacturing method of display panel

Citations (3)

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US5913147A (en) * 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
US20060223312A1 (en) * 2005-03-31 2006-10-05 Battelle Memorial Institute Method and apparatus for selective deposition of materials to surfaces and substrates
US7341947B2 (en) * 2002-03-29 2008-03-11 Micron Technology, Inc. Methods of forming metal-containing films over surfaces of semiconductor substrates

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US5407524A (en) * 1993-08-13 1995-04-18 Lsi Logic Corporation End-point detection in plasma etching by monitoring radio frequency matching network
US5960108A (en) * 1997-06-12 1999-09-28 Apple Computer, Inc. Method and system for creating an image-based virtual reality environment utilizing a fisheye lens
US6140226A (en) * 1998-01-16 2000-10-31 International Business Machines Corporation Dual damascene processing for semiconductor chip interconnects
US6147009A (en) * 1998-06-29 2000-11-14 International Business Machines Corporation Hydrogenated oxidized silicon carbon material
US6127263A (en) * 1998-07-10 2000-10-03 Applied Materials, Inc. Misalignment tolerant techniques for dual damascene fabrication
US6391771B1 (en) * 1998-07-23 2002-05-21 Applied Materials, Inc. Integrated circuit interconnect lines having sidewall layers
TW437040B (en) * 1998-08-12 2001-05-28 Applied Materials Inc Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
US6225207B1 (en) * 1998-10-01 2001-05-01 Applied Materials, Inc. Techniques for triple and quadruple damascene fabrication
US6319821B1 (en) * 2000-04-24 2001-11-20 Taiwan Semiconductor Manufacturing Company Dual damascene approach for small geometry dimension
US6372631B1 (en) * 2001-02-07 2002-04-16 Advanced Micro Devices, Inc. Method of making a via filled dual damascene structure without middle stop layer
US6630407B2 (en) * 2001-03-30 2003-10-07 Lam Research Corporation Plasma etching of organic antireflective coating
US6638851B2 (en) * 2001-05-01 2003-10-28 Infineon Technologies North America Corp. Dual hardmask single damascene integration scheme in an organic low k ILD
US20020187627A1 (en) * 2001-06-06 2002-12-12 Yu-Shen Yuang Method of fabricating a dual damascene structure
US6842659B2 (en) * 2001-08-24 2005-01-11 Applied Materials Inc. Method and apparatus for providing intra-tool monitoring and control
US6759327B2 (en) * 2001-10-09 2004-07-06 Applied Materials Inc. Method of depositing low k barrier layers
KR100423752B1 (en) * 2001-11-12 2004-03-22 주식회사 실트론 A Semiconductor Silicon Wafer and a Method for making thereof
KR100805843B1 (en) * 2001-12-28 2008-02-21 에이에스엠지니텍코리아 주식회사 Method of forming copper interconnection, semiconductor device fabricated by the same and system for forming copper interconnection
JP4493254B2 (en) * 2002-01-21 2010-06-30 船井電機株式会社 Digital broadcast receiving apparatus having EPG screen display function
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KR100593446B1 (en) * 2004-05-19 2006-06-28 삼성전자주식회사 Methods of manufacturing semiconductor devices using organic fluoride buffer solutions
JP2008502150A (en) * 2004-06-03 2008-01-24 エピオン コーポレーション Improved dual damascene integrated structure and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5913147A (en) * 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
US7341947B2 (en) * 2002-03-29 2008-03-11 Micron Technology, Inc. Methods of forming metal-containing films over surfaces of semiconductor substrates
US20060223312A1 (en) * 2005-03-31 2006-10-05 Battelle Memorial Institute Method and apparatus for selective deposition of materials to surfaces and substrates

Also Published As

Publication number Publication date
US20080124924A1 (en) 2008-05-29
TW200814199A (en) 2008-03-16
WO2008011403A2 (en) 2008-01-24

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