KR102301933B1 - Fabricating method of Semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided. The method of manufacturing the semiconductor device includes: preparing a base substrate structure having a recess region; depositing a material film on the base substrate structure having the recess region to fill the recess region; The method may include ionizing a material of the material layer to remove the material layer other than the recess area, and leaving the material layer in the recess area to form a material layer pattern in the recess area.

Description

Method of manufacturing a semiconductor device {Fabricating method of Semiconductor device}

The present application relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including forming a material film pattern in a recess region.

When manufacturing semiconductor devices, deposition and selective removal of metal layers are important processes. A typical semiconductor wafer has several metal layers deposited or plated on the surface, each successive layer being polished or etched before further layers are added. In particular, the electroplating of copper on the wafer surface is widely practiced. Typically, a chemical-mechanical polishing (CMP) process is typically used to remove unwanted portions of the plating layer after plating of copper (which usually creates a copper capping layer on the wafer). have.

In a typical CMP process, a substrate (eg, a wafer) is placed in contact with a rotating polishing pad attached to a platen. A CMP slurry, typically a polishing and chemical reaction mixture, is supplied to the pad during the CMP process of the substrate. During the CMP process, the wafer carrier system or polishing head applies pressure (down force) against the substrate as the pad (fixed to the platen) and the substrate are rotated. The slurry undergoes a planarization (polishing) process by chemical mechanical interaction, and the substrate film is planarized due to the effect of the rotational motion of the pad relative to the substrate. Polishing is continued in this manner until any film on the substrate is removed, and the usual purpose of polishing is to effectively planarize the substrate.

However, the CMP process has a problem in that the process cost is high along with the problems of scratches, contamination and corrosion caused by particles contained in the slurry. Accordingly, in a semiconductor process, a method for solving a problem occurring in a CMP process and performing a planarization process is continuously being studied.

One technical problem to be solved by the present application is to provide a method of manufacturing a semiconductor device in which a manufacturing process is simplified.

Another technical problem to be solved by the present application is to provide a method of manufacturing a semiconductor device that can solve problems (scratches, contamination, corrosion, etc. due to particles included in the slurry) occurring in the CMP process by omitting the CMP process. there is

Another technical problem to be solved by the present application is to provide a method of manufacturing a semiconductor device with reduced manufacturing cost.

Another technical problem to be solved by the present application is to provide a method of manufacturing a semiconductor device with improved reliability.

The technical problem to be solved by the present application is not limited to the above.

In order to solve the above-described technical problems, the present application provides a method of manufacturing a semiconductor device.

According to an embodiment, the method of manufacturing the semiconductor device includes: preparing a base substrate structure having a recess region; depositing a material film on the base substrate structure having the recess region; filling a region, and ionizing the material of the material film to remove the material film other than the recess region, and leaving the material film in the recess region to form a material film pattern in the recess region can do.

According to an embodiment, the step of ionizing the material of the material layer includes immersing the base substrate structure having the material layer in an electrolyte, a first removal step of applying a first voltage to the material layer, and the material The method may include a second removal step of applying a second voltage of a lower level than the first voltage to the layer.

According to an embodiment, the method of manufacturing the semiconductor device may include applying the second voltage immediately after the first voltage is applied (directly after).

According to an embodiment, the rate at which the material of the material layer is ionized in the first removal step may include a speed greater than the rate at which the material of the material layer is ionized in the second removal step.

According to an embodiment, the second voltage may include more than 0.5V and less than 1.6V.

According to an embodiment, the electrolyte may include phosphoric acid (H ₃ PO ₄ ), and the concentration of the phosphoric acid may include 50 wt% or more.

According to an embodiment, as the concentration of the phosphoric acid decreases, the ionization rate of the material may increase.

According to an embodiment, before depositing the material layer, the method further includes forming a barrier layer along the inner surface of the recess region on the base substrate structure, wherein the electrolyte is used to etch the barrier layer. It may contain a barrier etchant.

According to an embodiment, the barrier layer may include any one of titanium (Ti) and tantalum (Ta).

According to an embodiment, it may include applying the first and second voltages to the material layer while the electrolyte is stirred.

According to an embodiment, the recess region may be a trench, and the material layer pattern may include a metal wiring.

According to an embodiment, the recess region may be a via-hole passing through the base substrate, and the material layer pattern may include a through silicon via (TSV).

According to an embodiment, the material layer may include a copper layer.

According to another embodiment, the method of manufacturing the semiconductor device includes preparing a base substrate, depositing a material film on the base substrate, immersing the base substrate on which the material film is deposited in an electrolyte, and the material and sequentially applying a first voltage and a second voltage lower than the first voltage to the film to ionize the material of the material film, thereby removing at least a portion of the material film.

According to another embodiment, in a first section in which the removal rate of the material layer decreases to a first slope according to an increase in voltage in the first voltage section, and in a second voltage section, the removal rate of the material layer decreases in a second slope according to an increase in voltage in the second voltage section is provided, a magnitude of the second slope of the second interval is greater than a magnitude of the first slope of the first interval, and the first voltage is selected in the second voltage interval; , the second voltage may include being selected in the first voltage period.

A method of manufacturing a semiconductor device according to an embodiment of the present application includes preparing a base substrate structure having a recess region, depositing a material film on the base substrate structure having the recess region, and filling the recess region and ionizing the material of the material layer to remove the material layer other than the recess area, and leaving the material layer in the recess area to form the material layer pattern in the recess area. have.

Accordingly, damage to the film quality (scratch, contamination, corrosion, etc. caused by particles included in the slurry) according to the process of forming the material film pattern in the recess region may be prevented. In addition, a highly reliable metal wiring or TSV (Through Silicon Via) can be manufactured simply and at low cost.

1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application.
2 to 7 are views illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present application.
8 to 11 are views illustrating a manufacturing process of a semiconductor device according to a modified example of the first embodiment of the present application.
12 to 16 are views illustrating a manufacturing process of a semiconductor device according to a second exemplary embodiment of the present application.
17 and 18 are photographs of results obtained by electrolytic polishing in the manufacturing process of the semiconductor device according to Example 1 of the present application.
19 is a photograph taken at different magnifications and angles of the semiconductor device according to Example 1 of the present application.
20 is a photograph showing EDS analysis of a semiconductor device according to Comparative Example 1 of the present application.
21 is a photograph showing EDS analysis of a semiconductor device according to Example 1 of the present application.
22 is a photograph of a semiconductor device according to Example 1 of the present application.
23 is a photograph taken before the electrolytic polishing process is performed in the manufacturing process of the semiconductor device according to Comparative Example 1 of the present application.
24 is a photograph taken after the electrolytic polishing process is performed in the manufacturing process of the semiconductor device according to Comparative Example 1 of the present application.
25 is a photograph comparing the removal effect of the barrier layer according to the concentration of ammonium fluoride (NH _{4 F) included in the electrolyte.}
26 is a photograph showing a state in which a copper film is deposited in a via hole during a manufacturing process of a semiconductor device according to Example 3 of the present application.
27 is a photograph of a semiconductor device according to Example 3 of the present application.
28 and 29 are graphs comparing the effect according to the concentration of phosphoric acid included in the electrolyte.
30 is a photograph comparing the effects of electrolyte stirring in the manufacturing process of the semiconductor device according to Example 1 of the present application.
31 and 32 are graphs comparing the effects of electrolyte stirring in the manufacturing process of the semiconductor device according to Example 1 of the present application.
33 and 34 are photographs comparing semiconductor devices according to Examples 1 and 2 of the present application.
35 is a graph comparing the effects of electrolyte stirring in the manufacturing process of the semiconductor device according to Example 2 of the present application.
36 is SEM photographs comparing the effect of electrolyte stirring and the effect of phosphoric acid concentration in the manufacturing process of the semiconductor device according to Example 1 of the present application.
37 is a graph comparing the effect according to the electrolyte stirring and the effect according to the concentration of phosphoric acid in the manufacturing process of the semiconductor device according to Example 1 of the present application.
38 is AFM photographs comparing the effect of electrolyte stirring and the effect of phosphoric acid concentration in the manufacturing process of the semiconductor device according to Example 1 of the present application.
39 and 40 are SEM photographs comparing the effect of stirring the electrolyte in the manufacturing process of the semiconductor device according to Example 2 of the present application.
41 is a graph showing the degree of ionization of copper according to a voltage applied during an electrolytic polishing process for removing a copper film.
42 is a photograph illustrating semiconductor devices photographed in each section shown in FIG. 41 .
43 and 44 are photographs comparing the effect according to the magnitude of the electric charge applied in the electrolytic polishing process for removing the copper film.
45 is a graph illustrating a change in the thickness of a copper film according to an amount of electric charge applied in an electrolytic polishing process for removing the copper film.

Hereinafter, preferred embodiments of the present application will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present application is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content may be thorough and complete, and the spirit of the present application may be sufficiently conveyed to those skilled in the art.

In this specification, when a component is referred to as being on another component, it may be directly formed on the other component or a third component may be interposed therebetween. In addition, in the drawings, thicknesses of films and regions are exaggerated for effective description of technical content.

In addition, in various embodiments of the present specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Accordingly, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes a complementary embodiment thereof. In addition, in the present specification, 'and/or' is used to mean including at least one of the elements listed before and after.

In the specification, the singular expression includes the plural expression unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to designate that a feature, number, step, element, or a combination thereof described in the specification is present, and one or more other features, numbers, steps, configuration It should not be construed as excluding the possibility of the presence or addition of elements or combinations thereof. Also, in the present specification, the term “connection” is used to include both indirectly connecting a plurality of components and directly connecting a plurality of components.

In addition, in the following description of the present application, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present application, the detailed description thereof will be omitted.

1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application, and FIGS. 2 to 7 are views illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present application.

1 and 2 , the base substrate structure 100 may be prepared (S100). According to an embodiment, the base substrate structure 100 may include a semiconductor substrate, a metal substrate, a plastic substrate, or a glass substrate. For example, the base substrate structure 100 may include a silicon (Si) semiconductor substrate.

The base substrate structure 100 may have a recess region 110 . According to an embodiment, the recess region 110 may be a trench. Accordingly, the base substrate structure 100 may be a semiconductor substrate in which a trench is formed. For example, the depth of the trench may be 3 μm. The recess region 110 may be formed directly on the semiconductor substrate or in a layer formed on the semiconductor substrate.

Referring to FIG. 3 , a barrier layer 200 may be formed on the base substrate structure 100 . The barrier layer 200 may be formed along an inner surface of the recess region 110 . In other words, the barrier layer 200 may be conformally formed along the surface profile of the base substrate structure 100 having the recess region 110 . The barrier layer 200 may prevent diffusion of a material of a material layer, which will be described later. In addition, the barrier layer 200 may improve adhesion between the material film and the base substrate structure 100 , which will be described later.

According to an embodiment, the barrier layer 200 may include titanium (Ti). Alternatively, according to another embodiment, the barrier layer 200 may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), or tantalum nitride (TaN). ) and tantalum silicon nitride (TaSiN). According to an embodiment, the barrier layer 200 may be formed to a thickness of 20 nm.

Referring to FIG. 4 , a seed layer 300 may be formed on the base substrate structure 100 on which the barrier layer 200 is formed. According to an embodiment, the seed layer 300 may include a metal. The seed layer 300 may be formed on the barrier layer 200 along the inner surface of the recess region 110 . For example, the metal may be copper (Cu). According to an embodiment, the seed layer 300 may be formed by an electroless plating method. According to an embodiment, the seed layer 300 may be formed to a thickness of 150 nm.

5 , which will be described later, an interface between the seed layer 300 and the material layer 400 may be substantially indistinguishable.

In addition, the seed layer 300 may be formed of the same material (eg, copper) as the material layer 400 , and in the process of removing the material layer 400 to be described later, the material layer 400 . In addition, a portion of the seed layer 300 disposed outside the recess region 110 may be removed.

1 and 5 , a material layer 400 may be deposited on the base substrate structure 100 on which the seed layer 300 is formed. The material layer 400 may fill the recess region 110 (S200).

According to an embodiment, the material layer 400 may be deposited by an electrolytic deposition method. As a specific example, the deposition of the material layer 400 _{may be performed in a solution containing 1000 mM copper sulfate (CuSO 4} ), 580 mM sulfuric acid (H ₂ SO ₄ ), and 1.9 mM hydrochloric acid (HCl). In addition, the deposition of the material layer 400 may be performed for a time of 300 s under conditions of a current density of ^{-30 mA/cm 2 and a temperature of 25°C.}

According to another embodiment, the material layer 400 may be formed by various methods such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

The material layer 400 may completely fill the recess region 110 . Also, the material layer 400 may be formed on the base substrate structure 100 outside the recess region 110 . In other words, the material layer 400 may fill the recess region 110 and cover the upper surface of the base substrate structure 100 .

1, 6, and 7 , the material layer 400 other than the recess region 110 may be removed, and the material layer 400 in the recess region 110 may remain. . Accordingly, a material layer pattern 500 may be formed in the recess region 110 ( S300 ). That is, the material layer pattern 500 may be the material layer 400 remaining in the recess region 110 , and may be formed between the upper surface of the material layer pattern 500 and the base substrate structure 100 . The upper surface may be coplanar. In other words, the material film 400, the barrier layer ( 200), and the seed layer 300 may be removed.

According to an embodiment, the material layer pattern 500 may be a metal wire. Specifically, for example, the material layer pattern 500 may be a copper (Cu) wiring.

The material layer 400 may be removed by ionizing the material of the material layer 400 . According to an embodiment, the step of ionizing the material of the material layer 400 includes immersing the base substrate structure 100 having the material layer 400 in an electrolyte, It may include a first removal step of applying a first voltage, and a second removal step of applying a second voltage to the material layer 400 . The second voltage may be at a level lower than the first voltage.

Immediately after the first voltage is applied (directly after), the second voltage may be applied. In other words, the first voltage and the second voltage may be sequentially applied. That is, in one process, after the first voltage is applied, the second voltage may be applied.

Alternatively, according to another embodiment, the step of stirring the electrolyte before the first voltage is applied and the second voltage is applied may be performed. In this case, as the first voltage of a relatively high level is applied, a pitting phenomenon in which a hole is formed in the surface of the material layer 400 may be prevented.

According to an embodiment, in the step of removing the material layer 400 , as the voltage applied to the material layer 400 increases, the removal rate of the material layer 400 is different in a first section and a second section. sections may appear.

Specifically, the first section may be a section in which the removal rate of the material layer 400 decreases with a first slope according to an increase in voltage in the first voltage section. For example, the first voltage section may be a section in which the voltage applied to the material layer 400 is greater than 0.5V and less than 1.6V. Alternatively, the second section may be a section in which the removal rate of the material layer 400 increases with a second slope according to an increase in voltage in the second voltage section. For example, the second voltage section may be a section in which the voltage applied to the material layer 400 is 1.6V or more.

A magnitude of the second slope of the second section may be greater than a magnitude of the first slope of the first section. Accordingly, the change amount of the removal rate of the material layer 400 may be smaller in the first section than in the second section. That is, when a voltage is applied within the first section, the material of the material layer 400 may be ionized stably and substantially uniformly.

Alternatively, in the second section, the amount of change in the removal rate of the material layer 400 may be greater than that of the first section. That is, the rate at which the material of the material layer 400 is ionized in the second section may be faster than the rate at which the material of the material layer 400 is ionized in the first section.

According to an embodiment, the first voltage in the above-described first removing step may be selected in the second voltage section. Alternatively, the second voltage in the second removing step may be selected in the first voltage section.

That is, in the first removal step, the material layer 400 may be removed at a relatively high speed, and in the second removal step, the material layer 400 may be removed relatively stably and uniformly. Accordingly, the process time for removing the material layer 400 can be shortened, and the etching uniformity of the material layer 400 is improved, and the material layer pattern ( 500) can be improved.

In a voltage range lower than the first voltage section, the material of the material layer 400 may not be substantially ionized. That is, in a voltage range lower than the first voltage section, the material layer 400 may not be substantially removed.

According to an embodiment, the first voltage and the second voltage may be sequentially applied to the material layer 400 while the electrolyte is stirred. Accordingly, the efficiency of forming the material layer pattern 500 may be improved. That is, the removal of the material layer 400 may be performed within a relatively short time, and the etching uniformity of the material layer 400 may also be improved.

According to an embodiment, the electrolyte may include an acidic solution. For example, the acidic solution may include a phosphoric acid (H ₃ PO ₄ ) solution. According to one embodiment, in the electrolyte, the concentration of the phosphoric acid may be 50 wt% or more. On the other hand, when the concentration of phosphoric acid in the electrolyte is less than 50 wt%, as described above, the first section in which the material of the material film 400 is uniformly and stably removed may not exist, Accordingly, it is not easy to form the material layer pattern 500 in the recess region 110 . In other words, it is not easy to set a process condition in which the upper surface of the base substrate structure 100 and the upper surface of the material layer pattern 500 are coplanar. In addition, since the material layer 400 is non-uniformly and unstablely removed, the film quality of the material layer pattern 500 in the release region 110 may be deteriorated. Accordingly, according to the embodiment of the present application, the concentration of the phosphoric acid in the electrolyte may be 50 wt% or more.

Also, according to an embodiment, the ionization rate of the material of the material layer 400 may be controlled according to the concentration of the phosphoric acid. Specifically, as the concentration of the phosphoric acid decreases, the ionization rate of the material may increase. As a result, the lower the concentration of the phosphoric acid in the electrolyte, the faster the removal rate of the material layer 400 may be.

Also, according to an embodiment, the first voltage section corresponding to the first section from which the material of the material layer 400 is uniformly and stably removed may be extended according to the concentration of the phosphoric acid. Therefore, when the concentration of the phosphoric acid is relatively high, the process conditions can be set relatively easily.

The electrolyte may further include a barrier etchant. The barrier etchant may etch the barrier layer 200 . At the same time that the material layer 400 is removed, the barrier layer 200 may also be removed. That is, the barrier layer 200 and the material layer 400 may be removed together. Specifically, in the process in which the material of the material layer 400 is ionized and removed, the material layer 400 and the seed layer 300 are removed to expose the barrier layer 200 . The barrier layer 200 may be removed by the barrier etchant. That is, a portion of the barrier layer 200 disposed outside the recess region 110 is removed, and the barrier layer 200 is disposed between the inner surface of the recess region 110 and the material layer pattern 500 . This can remain.

For example, the barrier etchant may _{include ammonium fluoride (NH 4} F). Specifically, ammonium fluoride may react with water in an aqueous solution to form hydrofluoric acid (HF). Accordingly, the barrier layer 200 may be etched by hydrofluoric acid.

According to an embodiment, the concentration of the barrier etchant may be controlled. Specifically, the barrier etchant may _{include ammonium fluoride (NH 4} F) at a concentration of 0.5 to 2M. When the concentration of ammonium fluoride is less than 0.5M, the barrier layer 200 outside the recess region 110 may not be completely removed. Films (eg, an interlayer insulating film) may be damaged. Accordingly, according to an embodiment of the present application, the concentration of ammonium fluoride may be 0.5 to 2M.

As described above, the method of manufacturing the semiconductor device according to the first embodiment of the present application has been described. Hereinafter, a method of manufacturing a semiconductor device according to a modified example of the first embodiment of the present application will be described with reference to FIGS. 8 to 11 .

8 to 11 are views illustrating a manufacturing process of a semiconductor device according to a modified example of the first embodiment of the present application.

A method of manufacturing a semiconductor device according to a modified example of the first embodiment of the present application is the same as the method of manufacturing a semiconductor device according to the first exemplary embodiment described with reference to FIGS. 1 to 7 , but a modification of the first embodiment In the semiconductor device according to the embodiment, the seed layer 300 may be omitted. That is, after the material layer 400 is deposited on the barrier layer 200 , the barrier layer 200 and the material layer 400 disposed outside the recess region 110 may be removed.

As described above, the manufacturing method of the semiconductor device according to the first embodiment of the present application and the modified example of the first embodiment has been described. Hereinafter, a method of manufacturing a semiconductor device according to a second embodiment of the present application will be described.

12 to 17 are views illustrating a manufacturing process of a semiconductor device according to a second exemplary embodiment of the present application.

Referring to FIG. 12 , the base substrate structure 100 may be prepared. According to an embodiment, the base substrate structure 100 may include a semiconductor substrate, a metal substrate, a plastic substrate, or a glass substrate. For example, the base substrate structure 100 may include a silicon (Si) semiconductor substrate.

The base substrate structure 100 may have a recess region 110 . That is, the base substrate structure 100 may include a semiconductor substrate in which a recess region is formed. According to an embodiment, the recess region 110 may be a via-hole. Accordingly, the base substrate structure 100 may be a semiconductor substrate in which a via hole is formed.

Referring to FIG. 13 , a barrier layer 200 may be formed on the base substrate structure 100 . The barrier layer 200 may be formed along an inner surface of the recess region 110 . The barrier layer 200 may prevent diffusion of a material of a material layer, which will be described later. In addition, the barrier layer 200 may improve adhesion between the material film and the base substrate structure 100 , which will be described later.

According to an embodiment, the barrier layer 200 may include tantalum (Ta). Alternatively, according to another embodiment, the barrier layer 200 may include titanium (Ti), titanium nitride (TiN), silicon titanium nitride (TiSiN), tungsten (W), tungsten nitride (WN), tantalum nitride ( TaN) and tantalum silicon nitride (TaSiN) may be included.

Referring to FIG. 14 , a material layer 400 may be deposited on the base substrate structure 100 on which the barrier layer 200 is formed. The material layer 400 may fill the recess region 110 . For example, the material layer 400 may be a copper layer.

According to an embodiment, the material layer 400 may be deposited by an electrolytic deposition method. In this case, a seed layer may be formed on the base substrate structure 100 before forming the material layer 400 . Alternatively, according to another embodiment, the material layer 400 may be formed by various methods such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

15 and 16 , the material layer 400 other than the recess region 110 may be removed, and the material layer 400 in the recess region 110 may remain. Accordingly, a material layer pattern 500 may be formed in the recess region 110 . That is, the material layer pattern 500 may be the material layer 400 remaining in the recess region 110 .

The material layer 400 may be removed by the method described with reference to FIGS. 1 to 7 .

According to an embodiment, the lower region of the base substrate structure 100 may be removed so that both ends of the material layer pattern 500 are exposed. Accordingly, the semiconductor substrate structure 700 may be manufactured. In this case, the material layer pattern 500 in the semiconductor substrate structure 700 may be a through silicon via (TSV). That is, when a plurality of the semiconductor substrate structures 700 are stacked, the material layer patterns 500 may be connected to each other to form an electrical path. For example, as described above, after the material layer pattern 500 is formed, a front end of line (FEOL) and a back end of line (BEOL) process is performed, and a lower region of the base substrate structure 100 is performed. is removed, or after the FEOL process is performed and the material layer pattern 500 is formed and the BEOL process is performed, the lower region of the base substrate structure 100 is removed, or the FEOL and BEOL processes are performed and the A material layer pattern 500 may be formed. That is, the process of forming the material layer pattern 500 according to the embodiment of the present application may be combined with the FEOL process and the BEOL process in various ways.

The method of manufacturing a semiconductor device according to an embodiment of the present application includes preparing the base substrate structure 100 having the recess region 110 , and the base substrate structure 100 having the recess region 110 . ) by depositing the material film 400 on the material film 400 to fill the recess region 110 , and ionizing the material in the material film 400 to form the material film other than the recess region 110 ( 400 ) and leaving the material layer 400 in the recess region 110 to form the material layer pattern 500 in the recess region 110 .

Accordingly, the conventional chemical mechanical polishing process for forming the material film pattern 500 can be omitted or simplified, and scratches, contamination, corrosion, etc. caused by particles included in the slurry input in the chemical mechanical polishing process can be removed. Problems can be minimized. Due to this, it is possible to provide a manufacturing process of a metal wiring or TSV of high quality and high reliability, in which the manufacturing process is simple and the manufacturing cost is reduced.

As described above, a method of manufacturing a semiconductor device according to an embodiment of the present application has been described. Hereinafter, specific experimental examples and characteristic evaluation results of the method for manufacturing a semiconductor device according to an embodiment of the present application will be described.

Fabrication of a semiconductor device according to Example 1

After preparing a silicon substrate having a trench having a depth of 3 μm, a titanium (Ti) layer was formed on the silicon substrate along the inner surface of the trench. Thereafter, a copper (Cu) seed layer was formed on the titanium layer, and a copper film was deposited on the silicon substrate on which the copper seed layer was formed by an electrolytic deposition method. Specifically, in a solution containing copper sulfate (CuSO ₄ ) 1000 mM, sulfuric acid (H ₂ SO ₄ ) 580 mM, hydrochloric acid (HCl) 1.9 mM, ^{a current density of -30 mA/cm 2} , at a temperature of 25° C. Electrolytic deposition was performed for 300 s to deposit a copper film.

Subsequently, by an electropolishing method in which a voltage is applied after a silicon substrate on which a copper film is deposited is immersed in an electrolyte, the copper film other than the trench is removed and the copper film remains in the trench, and the semiconductor device according to Example 1 was prepared. More specifically, in the electrolytic polishing process to remove the copper film, the silicon substrate on which the above-described copper film was deposited was used as a working electrode, a platinum sheet (Pt sheet) was used as a counter electrode, and Ag/AgCl was used as a reference electrode. . In addition, as an electrolyte, a _{mixed solution of phosphoric acid (H 3} PO ₄ ) and ammonium fluoride (NH 4 F) was used.

Fabrication of a semiconductor device according to Example 2

A semiconductor device is manufactured by the method for manufacturing a semiconductor device according to the above-described embodiment 1, but in an electrolytic polishing process of removing a copper layer, a first voltage is applied to a silicon substrate on which a copper layer is deposited, and then a level lower than the first voltage is applied. A second voltage was applied.

Fabrication of a semiconductor device according to Example 3

After preparing a silicon substrate having a via-hole, a tantalum (Ta) layer was formed on the silicon substrate along the inner surface of the via hole. Thereafter, the semiconductor device according to Example 3 was manufactured by performing the method of manufacturing the semiconductor device according to Example 1 described above.

Fabrication of a semiconductor device according to Example 4

After preparing a silicon substrate having a via-hole, a tantalum (Ta) layer was formed on the silicon substrate along the inner surface of the via hole. Thereafter, the semiconductor device according to Example 4 was manufactured by performing the method of manufacturing the semiconductor device according to Example 2 described above.

Fabrication of a semiconductor device according to Comparative Example 1

A semiconductor device is manufactured by the method of manufacturing a semiconductor device according to Example 1 described above, but in the electrolytic polishing process of removing the copper film, ammonium fluoride (NH ₄ F) is not included, and phosphoric acid (H ₃ PO ₄ ) is included. An electrolyte was used to prepare a semiconductor device according to Comparative Example 1.

Methods of manufacturing the semiconductor device according to Examples 1 to 4 and Comparative Example 1 are summarized in Table 1 below.

division recess structure Number of times of voltage application in electropolishing step electrolyte Example 1 Trench One H ₃ PO ₄ +NH ₄ F Example 2 Trench 2 H ₃ PO ₄ +NH ₄ F Example 3 Via-hole One H ₃ PO ₄ +NH ₄ F Example 4 Via-hole 2 H ₃ PO ₄ +NH ₄ F Comparative Example 1 Trench One H ₃ PO ₄

17 and 18 are photographs of results obtained by electrolytic polishing in the manufacturing process of the semiconductor device according to Example 1 of the present application. Referring to FIG. 17 , in the manufacturing process of the semiconductor device according to Example 1, SEM (Scanning Electron Microscope) for before electropolishing and after electropolishing (After Electropolishing), respectively photographed, and the results are shown. Fig. 17 (a) shows a state in which a copper film is filled in a trench having a line width of 5 μm and a pitch of 1 μm, and Fig. 17 (b) shows a state in which a trench having a line width of 1 μm and a pitch of 2 μm is filled with a copper film, and Fig. 17 (c) shows a state in which a copper film is filled in a trench with a 2 μm line width and a 2 μm pitch. As can be seen from (a) to (c) of Figure 17, as the electrolytic polishing was performed, it was confirmed that the copper film other than the trench was easily removed.

Referring to FIG. 18 , a top view of the semiconductor device according to Example 1 was photographed and shown. As can be seen in FIG. 19 , in the case of the electropolished semiconductor device, it was confirmed that the copper film other than the trench was easily removed.

19 is a photograph taken at different magnifications and angles of the semiconductor device according to Example 1 of the present application.

Specific manufacturing process conditions of the semiconductor device according to Example 1 photographed in FIG. 19 are as follows. The copper film deposition process was ^{performed under a current of -30 mA/cm 2} and 9 C/cm ² conditions, and the copper film removal process was performed with _{an electrolyte of 70 wt% H 3} PO ₄ +1.0M NH4F, a potential of 1.3V ( Potential), 7.5C/cm ^{2 It} was performed under conditions.

19 (a) to (c), the top view of the semiconductor device according to the first embodiment is shown by SEM imaging at different magnifications. Referring to FIG. 19 (d), the A side view of the semiconductor device according to Example 1 was shown by SEM imaging. As can be seen from (a) to (d) of Figure 19, it was confirmed that the copper film other than the trench was easily removed.

20 is a photograph illustrating EDS analysis of a semiconductor device according to Comparative Example 1 of the present application, FIG. 21 is a photograph illustrating EDS analysis of a semiconductor device according to Example 1 of the present application, and FIG. 22 is an embodiment of the present application It is a photograph taken of the semiconductor device according to 1.

Referring to FIGS. 20 and 21 , Energy Dispersive X-ray Spectroscopy (EDS) analysis of the semiconductor device according to Comparative Example 1 and the semiconductor device according to Comparative Example 2 were taken and shown. Referring to FIG. 22, the implementation The semiconductor device according to Example 1 was shown by SEM imaging from a side view.

20 to 22 , in the case of the semiconductor device according to Comparative Example 1, the titanium layer was not removed, but in the case of the semiconductor device according to Example 1, it was confirmed that the titanium layer was also removed along with the copper film. there was. _{That is, it was confirmed that ammonium fluoride (NH 4} F) contained in the electrolyte during the electrolytic polishing of the copper film removed the titanium layer.

23 is a photograph taken before the electrolytic polishing process is performed in the manufacturing process of the semiconductor device according to Comparative Example 1 of the present application, and FIG. 24 is electrolytic polishing in the manufacturing process of the semiconductor device according to Comparative Example 1 of the present application. This is a picture taken after the process is performed.

Referring to FIG. 23 , a state before the electrolytic polishing process is performed in the manufacturing process of the semiconductor device according to Comparative Example 1 by SEM imaging. Specific process conditions for depositing the copper film are as follows. Copper film deposition was performed under the conditions of -30 mA/cm ² Current and 9 C/cm ^{2 .} As can be seen in FIG. 24 , it was confirmed that the deposition of the copper film in the trench was easily performed.

Referring to FIG. 24 , the state after the electrolytic polishing process is performed in the manufacturing process of the semiconductor device according to Comparative Example 1 is shown by SEM imaging. Specific process conditions for removing the copper film are as follows. Copper film removal was performed under the conditions of 70 wt% H ₃ PO ₄ electrolyte, 1.3V potential, and 7.5 C/cm ^{2 .}

As can be seen in FIG. 24 , in the case of the semiconductor device according to Comparative Example 1, although the copper film was removed, it was confirmed that the titanium (Ti) layer formed between the copper film and the silicon substrate structure was not removed.

25 is a photograph comparing the removal effect of the barrier layer according to the concentration of ammonium fluoride (NH _{4 F) included in the electrolyte.}

Referring to FIG. 25A , the semiconductor device according to Example 1 was photographed by SEM. In the manufacturing process of the semiconductor device photographed in (a) of FIG. 25 , specific process conditions for removing the copper film are as follows. Copper film removal was performed under conditions of 70 wt% H ₃ PO ₄ + 1.0M NH ₄ F electrolyte, 1.3V potential, 7.5 C/cm ^{2 .}

Referring to FIG. 25B , the semiconductor device according to Example 1 was photographed by SEM. In the manufacturing process of the semiconductor device photographed in (b) of FIG. 25 , specific process conditions for removing the copper film are as follows. Copper film removal was performed under the conditions of 70 wt% H ₃ PO ₄ + 2.0M NH ₄ F electrolyte, 1.3V potential, 7.5 C/cm ^{2 .}

Referring to FIG. 25C , the semiconductor device according to Example 1 was photographed by SEM. In the manufacturing process of the semiconductor device photographed in (c) of FIG. 25 , specific process conditions for removing the copper film are as follows. Copper film removal was performed under the conditions of 70 wt% H ₃ PO ₄ + 2.5M NH ₄ F electrolyte, 1.3V potential (Potential), 7.5 C/cm ^{2 .}

As can be seen from (a) to (c) of FIG. 25 , in the case of the semiconductor device according to Example 1, it was confirmed that the copper film except for the trench region was easily removed. In addition, it was confirmed that the titanium layer disposed between the copper film and the silicon substrate structure was easily removed regardless of the concentration of ammonium fluoride included in the electrolyte.

26 is a photograph showing a state in which a copper film is deposited in a via hole in a manufacturing process of a semiconductor device according to Example 3 of the present application, and FIG. 27 is a photograph taken of a semiconductor device according to Example 3 of the present application .

Referring to FIG. 26 , in the manufacturing process of the semiconductor device according to Example 3, after depositing a copper film in the via hole, a cross-section of the silicon substrate structure in which the copper film is deposited is photographed and shown. As can be seen in FIG. 26 , it was confirmed that the copper film was easily filled in the via hole.

Referring to FIG. 27 , the semiconductor device according to Example 3 was photographed by SEM. As can be seen in FIG. 27 , in the semiconductor device according to Example 3, it was confirmed that the copper film other than the via hole was easily removed. In addition, as the copper film was filled in the via hole, it was confirmed that it could be used as a through silicon via (TSV).

28 and 29 are graphs comparing the effect according to the concentration of phosphoric acid included in the electrolyte.

28 and 29, the semiconductor device according to the first embodiment manufactured using an electrolyte containing 50 wt% of H ₃ PO _{4 , 60 wt% of H 3} PO ₄ Manufactured using an electrolyte containing 60 wt% of H 3 PO 4 The semiconductor device according to the first embodiment, the semiconductor device according to the first embodiment manufactured using an electrolyte containing 70 wt% of H ₃ PO _{4 , 85 wt% of H 3} PO ₄ Manufactured using an electrolyte containing 85 wt% H 3 PO 4 The semiconductor device according to the first embodiment, the semiconductor device according to the first embodiment manufactured using the electrolyte containing _{30 wt% H 3} PO _{4, and the electrolyte containing 10 wt% H 3} PO ₄ Manufactured using For each of the semiconductor devices according to the first embodiment, the potential (Pontential(V) [vs. Ag/AgCl]) is changed over time in the copper film electrolytic polishing process, and the current density (mA) accordingly /cm ² ) The change was measured and shown.

As can be seen in FIGS. 28 and 29 , in _{the case of a semiconductor device manufactured using an electrolyte containing 30 wt% and 10 wt% of H 3} PO ₄ , it can be confirmed that the current density change according to the potential change occurs irregularly. could

However, in the case of a semiconductor device manufactured using an electrolyte containing 50 wt%, 60 wt%, 70 wt%, and 85 wt% of H ₃ PO ₄ , it was found that the current density change according to the potential change showed a constant trend. could check

In addition, in the case of a semiconductor device manufactured using an electrolyte containing 50 wt%, 60 wt%, 70 wt%, and 85 wt% of H ₃ PO _{4 , the lower the concentration of H 3} PO _4, the higher the current density. could be seen to appear.

As a result, in the electrolytic polishing process for removing the copper film, the concentration of phosphoric acid should be 50 wt% or more, and as the concentration of phosphoric acid decreased, it was confirmed that the ionization rate of copper increased.

30 is a photograph comparing the effects of electrolyte stirring in the manufacturing process of the semiconductor device according to Example 1 of the present application.

Referring to FIG. 30 , a semiconductor device is manufactured according to the manufacturing method of the semiconductor device according to the first embodiment, but the time for which the electrolyte is agitated during the copper film removal process is controlled, and thus manufactured according to the first embodiment The semiconductor device according to the method was photographed. The semiconductor device of the photo taken in FIG. 30 was subjected to electrolytic polishing to remove the copper film in an electrolyte containing _{85 wt% of H 3} PO _{4 .}

Figure 30 (a) shows a case in which stirring was performed for 300 s for an electrolytic polishing time of 300 s, and Fig. 30 (b) shows that electrolytic polishing was performed for 300 s, but stirring was performed for 240 s and then stirring was not performed for 60 s. 30 (c) shows a case where electrolytic polishing is performed for 300 s, but stirring is not performed for 120 s after 180 s, and FIG. 30 (d) shows agitation for 300 s of electrolytic polishing time. It shows the case where it is not performed, and (e) of FIG. 30 shows the speed of electrolyte stirring.

As can be seen from (a) to (d) of FIG. 30 , it was confirmed that, in the electrolytic polishing process, when the electrolyte was stirred, the copper film outside the trench was more easily removed.

31 and 32 are graphs comparing the effects of electrolyte stirring in the manufacturing process of the semiconductor device according to Example 1 of the present application.

Referring to FIGS. 31 and 32 , a plurality of semiconductor devices according to Example 1 are manufactured in which the time for which the electrolyte is agitated during the copper film removal process is controlled, and an electrolytic polishing process for removing the copper film for each Changes in Current and Charge were measured with time. Specifically, when electrolytic polishing is performed for 300 s, but stirring is not performed for 60 s after 240 s, electrolytic polishing is performed for 300 s, but stirring is performed for 180 s and stirring is not performed for 120 s. When agitation was not performed during the polishing time, the change in current and change in electric charge with time were measured for each. Figure 31 was measured based on the condition of 1.3V, Figure 32 was measured based on the condition of 3.6 C/cm ² .

As can be seen in FIGS. 31 and 32 , when stirring was not performed during the electropolishing time, it took 600 s to remove the copper film, but it was confirmed that it took 300 s when stirring was performed.

33 and 34 are photographs comparing semiconductor devices according to Examples 1 and 2 of the present application.

Referring to FIGS. 33 and 34 , after semiconductor devices were manufactured according to the manufacturing methods of the semiconductor devices according to Examples 1 and 2, SEM images were taken to show them. The semiconductor device of the photos taken in FIGS. 33 and 34 was subjected to electrolytic polishing to remove the copper film in an electrolyte containing _{85 wt% of H 3} PO _{4 .}

Specifically, (a) of FIG. 33 is a photograph showing the semiconductor device according to Example 1 manufactured by applying a voltage of 2.3V for 300s, and (b) of FIG. 33 is a voltage of 2.3V applied for 240s It is a photograph showing the semiconductor device according to Example 2 manufactured by applying a voltage of 1.3V for 60s after being applied, and FIG. It is a photograph showing the semiconductor device according to Example 2 which was applied and manufactured during the period.

In addition, (a) of FIG. 34 is a photograph showing the semiconductor device according to Example 1 manufactured by applying a voltage of 2.3V for 300s, and (b) of FIG. After that, a voltage of 1.3V is applied for 60s and is a photograph showing the semiconductor device according to Example 2, which is manufactured, and FIG. It is a photograph showing the semiconductor device according to Example 2 manufactured by being applied, and FIG. 34 (e) is a photograph showing the semiconductor device according to Example 1 manufactured by applying a voltage of 1.3V for 300s.

33 and 34 , in the semiconductor device according to Example 2, it was confirmed that the copper film other than the trench was easily removed. In addition, it was confirmed that the semiconductor device according to Example 2 has improved efficiency of removing the copper film other than the trench as compared to the semiconductor device according to Example 1.

35 is a graph comparing the effects of electrolyte stirring in the manufacturing process of the semiconductor device according to Example 2 of the present application.

Referring to FIG. 35 , a plurality of semiconductor devices according to Example 2 are manufactured in which the time for which the electrolyte is agitated during the copper film removal process is controlled, but for each, in the electrolytic polishing process for removing the copper film, time A change in Current and a change in Charge were measured. Specifically, when stirring is performed at a voltage of 2.3V for a time of 240s and then stirring at a voltage of 1.3V for a time of 60s, after stirring at a voltage of 2.3V for a time of 180s, a voltage of 1.3V When the stirring was performed for a time of 120 s and when the stirring was performed for a time of 300 s at a voltage of 2.3V, the change in current and the change in charge with time were measured, respectively. The change in charge was measured based on the condition of ^{3.6 C/cm 2 .}

As can be seen in FIG. 35 , when stirring was not performed during the electropolishing time, it was confirmed that more time was required for the removal of the copper film than when stirring was performed during the electrolytic polishing time.

36 is SEM photographs comparing the effect of electrolyte stirring and the effect of phosphoric acid concentration in the manufacturing process of the semiconductor device according to Example 1 of the present application.

Referring to FIG. 36 , a plurality of semiconductor devices according to Example 1 were manufactured in which the electrolyte agitation time and phosphoric acid concentration were controlled during the copper film removal process, and SEM imaging was performed for each. Specifically, (a) of _{FIG. 36 shows a semiconductor device manufactured under the conditions of 85 wt% H 3} PO ₄ electrolyte, 4.5 C/cm ² , and 400 rpm stirring, and (b) of FIG. 36 is 70 wt% H ₃ PO ₄ Electrolyte, 4.5 C/cm ² , shows a semiconductor device manufactured under the conditions of 400 rpm stirring, (c) of FIG. 36 is 50 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , 400 rpm stirring conditions shows a semiconductor device manufactured in , (d) of FIG. 36 shows a semiconductor device manufactured under the conditions of 85 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , without agitation, and FIG. 36 ( e) is 70 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , shows a semiconductor device manufactured under conditions of without agitation, (f) of FIG. 37 is 50 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , It represents a semiconductor device manufactured under conditions of non-agitation (without agitation).

As can be seen from (a) to (f) of FIG. 36 , it was confirmed that the copper film removal efficiency was higher when the copper film was removed while the electrolyte was stirred, compared to the case where the electrolyte was not stirred. In addition, as _{the concentration of H 3} PO ₄ decreased, it was confirmed that the copper film removal efficiency was higher.

37 is a graph comparing the effect according to the electrolyte stirring and the effect according to the concentration of phosphoric acid in the manufacturing process of the semiconductor device according to Example 1 of the present application.

Referring to FIG. 37 , a plurality of semiconductor devices according to Example 1 were manufactured in which the electrolyte agitation time and the phosphoric acid concentration were controlled in the copper film removal process, and electrolytic polishing for removing the copper film for each In the process, the change in charge over time was measured. Specifically, when it is stirred with H ₃ PO _4, and 400rpm for 50 wt%, in the case 50 is not wt% of H ₃ PO ₄ and stirring, if a stirred with H ₃ PO _4, and 400rpm for 70 wt%, 70 wt% of H ₃ PO ₄ and if not stirred, 85 wt % of H ₃ PO ₄ and if stirred at 400 rpm, 85 wt % of H ₃ PO ₄ and not stirred, respectively, measure the change in charge with time did. 38 was measured based on a condition of 3.6 C/cm ^{2 .}

As can be seen in FIG. 37 , it was confirmed that the highest copper film removal efficiency was obtained when the mixture was stirred at _{50 wt% of H 3} PO _{4 and 400 rpm.} On the other hand, in the case of 85 wt% of H ₃ PO ₄ and not stirring, it was confirmed that the copper film removal efficiency was the lowest.

38 is AFM photographs comparing the effect of electrolyte stirring and the effect of phosphoric acid concentration in the manufacturing process of the semiconductor device according to Example 1 of the present application.

Referring to FIG. 38 , a plurality of semiconductor devices according to Example 1 were manufactured in which the electrolyte agitation time and phosphoric acid concentration were controlled during the copper film removal process, and atomic force microscopy (AFM) imaging was performed for each. was shown.

Specifically, (a) of _{FIG. 38 shows a semiconductor device manufactured under the conditions of 85 wt% H 3} PO ₄ electrolyte, 4.5 C/cm ² , and 400 rpm stirring, and (b) of FIG. 38 is 70 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , shows a semiconductor device manufactured under the conditions of 400 rpm stirring, (c) of FIG. 38 is 50 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , 400 rpm stirring conditions shows a semiconductor device manufactured in , (d) of FIG. 38 shows a semiconductor device manufactured under the conditions of 85 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , without agitation, and (d) of FIG. e) is 70 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , and represents a semiconductor device manufactured under conditions of without agitation, (f) of FIG. 38 is 50 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , It represents a semiconductor device manufactured under conditions of non-agitation (without agitation).

As can be seen from (a) to (f) of FIG. 38 , it was confirmed that the copper film removal efficiency was higher when the copper film was removed while the electrolyte was stirred, compared to the case where the electrolyte was not stirred. In addition, as _{the concentration of H 3} PO ₄ decreased, it was confirmed that the copper film removal efficiency was higher.

39 and 40 are SEM photographs comparing the effect of stirring the electrolyte in the manufacturing process of the semiconductor device according to Example 2 of the present application.

Referring to FIG. 39 , a semiconductor device was manufactured according to the manufacturing process of the semiconductor device according to Example 2, but was manufactured according to the following specific conditions. The copper film deposition process was ^{performed under a current of -30 mA/cm 2} , 9 C/cm ² conditions, and the copper film removal process was performed under 70 wt% H ₃ PO ₄ electrolyte, 1.3V potential, 6.5C/cm ^It was carried out under conditions of primary removal in which stirring at ^{2 and 400 rpm is performed, 1.0 C/cm 2} and secondary removal in which stirring is not performed.

Referring to FIG. 40 , a semiconductor device was manufactured according to the manufacturing process of the semiconductor device according to Example 2, but was manufactured according to the following specific conditions. The copper film deposition process was ^{performed under a current of -30 mA/cm 2} , 9 C/cm ² conditions, and the copper film removal process was performed under 70 wt% H ₃ PO ₄ electrolyte, 1.3V potential, 6.5C/cm ^It was carried out under conditions of primary removal in which stirring at ^{2 and 400 rpm is performed, 0.5 C/cm 2} and secondary removal in which stirring is not performed.

As can be seen in FIGS. 39 and 40 , it was confirmed that the copper film other than the trench was easily removed despite the change in the secondary removal conditions. In addition, it was confirmed that the copper film was easily filled in the trenches having line widths and line spaces of various sizes.

41 is a graph showing the degree of copper ionization according to a voltage applied during an electrolytic polishing process for removing a copper film, and FIG. 42 is a photograph showing semiconductor devices taken in each section shown in FIG. 41 .

Referring to FIG. 41, a semiconductor device is prepared according to the manufacturing method of the semiconductor device according to the first embodiment, but a potential (Potential V vs. Ag/AgCl) applied during an electrolytic polishing process for removing a copper film is controlled, Accordingly, the current density (Current density, mA/cm ² ) was measured and shown.

Referring to FIG. 42 , the semiconductor device described above in FIG. 41 is illustrated by SEM imaging. Specifically, (a) of FIG. 41 shows a state before electropolishing is performed, (b) of FIG. 41 shows a state where 0.25V is applied, and (c) of FIG. 41 shows that 0.375V is applied. The applied state is photographed and shown, FIG. 41 (d) shows a photographed state in which 0.5V is applied, and FIG. 41 (e) is a photographed state in which 1.3V is applied.

As can be seen in FIGS. 41 and 42 , it was confirmed that the slope of the current density increased with an increase in the applied voltage in the section of more than 0V and less than 0.5V and the section of 1.6V to 2.5V. On the other hand, in the section of more than 0.5 V and less than 1.5 V, it was confirmed that the slope of the current density slightly decreased as the applied voltage increased.

In addition, it was confirmed that the copper film was not removed in the section of more than 0V and less than 0.5V, and that the copper film was removed in the section of 0.375V or more. In addition, in the section of 1.6V or more and 2.5V or less, compared with the section of more than 0.5V and less than 1.5V, the slope of the measured current density was significantly higher, confirming that the etch rate was remarkably fast, Although the etching rate was relatively low in the section exceeding 1.5V, it was confirmed that the surface state of the etched copper film was the best.

As a result, in the electropolishing process for removing the copper film, a first voltage of a relatively high level is applied to remove the copper film at a high speed, and then, a second voltage of a relatively low level is applied to improve the etching uniformity of the copper film. It can be seen that this is a method that can efficiently perform the planarization process.

43 and 44 are photographs comparing the effect according to the magnitude of the electric charge applied in the electrolytic polishing process for removing the copper film, and FIG. 45 is a change in the thickness of the copper film according to the amount of charge applied in the electrolytic polishing process for removing the copper film. is a graph representing

Referring to FIGS. 43 and 44 , the magnitude of the charge applied during the copper film removal process is 0C/cm ² , 0.5 C/cm ² , 1.5 C/cm ² , and 2.5 C/cm ² A plurality of the above-described implementations are controlled. After manufacturing the semiconductor device according to Example 1, each was shown by SEM imaging. 43 shows a Top image and FIG. 44 shows a Vertical image.

^{Referring to FIG. 45 , in the semiconductor device according to Example 1 manufactured according to each C/cm 2} size after controlling the amount of charge applied during the copper film removal process, the thickness (Thickness, um) of the copper film other than the trench ) was measured and shown.

As can be seen in FIGS. 43 to 45 , as the magnitude of the charge (or the magnitude of the voltage) applied during the copper layer removal process increased, it was confirmed that the copper layer was easily removed.

As mentioned above, although the present application has been described in detail using preferred embodiments, the scope of the present application is not limited to specific embodiments and should be construed according to the appended claims. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present application.

100: base structure
110: recess area
200: barrier layer
300: seed layer
400: material film
500: material film pattern
600: pad
700: semiconductor substrate structure

Claims (15)

preparing a base substrate structure having a recess region;
forming a barrier layer on the base substrate structure along an inner surface of the recess region;
depositing a material film on the barrier layer of the base substrate structure having the recess region to fill the recess region; and
ionizing the material of the material film to remove the material film other than the recess region, and leaving the material film in the recess region to form a material film pattern in the recess region,
The step of ionizing the material of the material film,
immersing the base substrate structure having the material film in an electrolyte;
a first removal step of ionizing the material of the material layer at a relatively high speed by applying a first voltage of 1.6V or higher to the material layer; and
A second removal step of ionizing the material of the material film at a relatively slow rate by applying a second voltage of more than 0.5V and less than 1.6V to the material film,
The electrolyte includes 50 wt% or more of phosphoric acid (H ₃ PO ₄ ) to remove the material film, and ammonium fluoride (NH ₄ F) to remove the barrier layer,
and removing the barrier layer other than the recess region together with the material layer other than the recess region in the forming of the material layer pattern.
delete According to claim 1,
Immediately after the first voltage is applied (directly after), the method of manufacturing a semiconductor device comprising the step of applying the second voltage.
delete delete delete According to claim 1,
and as the concentration of the phosphoric acid decreases, the ionization rate of the material increases.
delete According to claim 1,
The barrier layer is selected from among titanium (Ti), tantalum (Ta), titanium nitride (TiN), silicon titanium nitride (TiSiN), tungsten (W), tungsten nitride (WN), tantalum nitride (TaN), and silicon tantalum nitride (TaSiN). A method of manufacturing a semiconductor device comprising any one.
According to claim 1,
and at the same time the electrolyte is stirred, the first and second voltages are applied to the material layer.
According to claim 1,
and wherein the recess region is a trench, and the material layer pattern is a metal wiring.
According to claim 1,
and wherein the recess region is a via hole passing through the base substrate structure, and the material layer pattern is a through silicon via (TSV).
According to claim 1,
The material layer is a method of manufacturing a semiconductor device including a copper layer.
preparing a base substrate;
forming a barrier layer on the base substrate;
depositing a material film on the barrier layer;
immersing the base substrate on which the material film is deposited in an electrolyte; and
and sequentially applying a first voltage of 1.6V or more and a second voltage of more than 0.5V and less than 1.6V to the material layer to ionize the material of the material layer, thereby removing at least a portion of the material layer but,
When the first voltage is applied, the material ionization rate of the material layer is faster than the material ionization rate of the material layer when the second voltage is applied,
The electrolyte includes 50 wt% or more of phosphoric acid (H ₃ PO ₄ ) to remove the material film, and ammonium fluoride (NH ₄ F) to remove the barrier layer,
In the step of removing at least a portion of the material layer, at least a portion of the barrier layer together with the material layer is removed.
15. The method of claim 14,
A first section in which the removal rate of the material layer decreases with a first slope according to an increase in voltage in a first voltage section, and a second section in which the removal rate of the material layer increases at a second slope according to an increase in voltage in a second voltage section is provided,
The magnitude of the second slope of the second section is greater than the magnitude of the first slope of the first section,
and wherein the first voltage is selected in the second voltage range, and the second voltage is selected in the first voltage range.

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