US20070151860A1

US20070151860A1 - Method for forming a copper metal interconnection of a semiconductor device

Info

Publication number: US20070151860A1
Application number: US11/617,153
Authority: US
Inventors: Ji Ho Hong
Original assignee: Dongbu Electronics Co Ltd
Current assignee: DB HiTek Co Ltd
Priority date: 2005-12-29
Filing date: 2006-12-28
Publication date: 2007-07-05
Also published as: KR100731107B1

Abstract

Embodiments relate to a method for forming a copper metal interconnection of a semiconductor device. In embodiments, a copper metal interconnection may be formed through a damascene process. The method may include forming a first copper plating layer on an interlayer dielectric layer of the semiconductor substrate by performing an electrical-chemical plating scheme with a first plating distance, measuring surface uniformity of the first copper plating layer, and forming a second copper plating layer on the first copper plating layer by adjusting a plating distance according to the surface uniformity of the first copper plating layer.

Description

The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0134077 (filed on Dec. 29, 2005), which is hereby incorporated by reference in its entirety.

BACKGROUND

Semiconductor manufacturing processes may be classified into a front end of the line (FEOL) process, which may be used to form a transistor on a silicon substrate, and a back end of the line (BEOL) process, which may be used to form metal interconnections. The BEOL process may refer to a process of forming power supply and signal transfer paths on a silicon substrate to connect transistors to each other to constitute an integrated circuit.
Copper (Cu), which is a material that may have high EM (Electro-migration) tolerance, may be used for such a BEOL process. However, since copper may not be easily etched, and may be oxidized during an interconnection process, it may be difficult to pattern copper using a typical photo process technology.
To form a copper metal interconnection, a dual damascene process technology may be used as an alternative to photo technology.
The dual damascene process may form a via and a trench in an interlayer dielectric layer formed on a semiconductor substrate. The via and trench may be filled with copper through an electro-chemical plating (ECP) scheme Finally, the upper surface of the semiconductor substrate may be planarized through a CMP (Chemical Mechanical Polishing) process.
When manufacturing a copper metal interconnection using the damascene process, defects may occur due to copper residue after the CMP process.
FIG. 1 shows an image of copper residue observed through a scan electro microscope, which may remain after the CMP process.
FIG. 1 shows that lattice pattern 40 may be formed on a wafer, and copper residue 42 may be formed on lattice pattern 40.
In addition, referring to FIG. 1, a stripe pattern 41 may be formed The stripe pattern may be irregular due to copper residue 42 formed on the stripe pattern. Since such copper residue 42 may disconnect the patterns from each other, the copper residue may be a factor that reduce a performance and yield rate of a semiconductor device.
Copper residue may be generated by various factors. In particular, copper residue may be generated due to non-uniformity of a copper plating layer formed through a copper ECP process. In addition, during the copper ECP process, since bubbles may accumulate in a plating solution, an unexpected current may be induced into the wafer.
Since the current induced by the bubbles may interrupt an electric field that may normally form in a plating tank, the uniformity of the copper plating layer may be degraded. In particular, since the ECP process may be performed while rotating the wafer, the bubbles of the plating solution may be centralized at a center part of the wafer. Accordingly, the center part of the wafer may be plated more thinly than an edge part of the wafer.
Hereinafter, processes for forming copper residue due to the irregularity of the copper plating layer according to the related art will be briefly described with reference to FIGS. 2A to 2G.
Referring to FIG. 2A, barrier metal layer 12 may be formed on first interlayer dielectric layer 10 to prevent diffusion of copper atoms, and a prescribed damascene pattern (e.g., a via hole or a trench) may be formed on the resultant structure. Thereafter, a copper seed layer (not shown) may be formed on barrier metal layer 12. An ECP process may then be performed such that copper plating layer 14 may be formed on interlayer dielectric layer 10.
FIG. 2A shows a state in which bulk plating may be performed up to a prescribed height from interlayer dielectric layer 10 after sufficiently filling the damascene pattern with copper during the ECP process. Since a plating rate may vary depending on the size of a damascene pattern, the bulk plating may be performed to form a copper layer such that the entire damascene pattern may be sufficiently gap filled.
As shown in FIG. 2A, if bubbles are centralized at center part 30 of the wafer in plating solution, a thickness of a plating layer formed at center part 30 of the wafer may be thinner than the thickness of the plating layer formed at edge part 31 of the wafer.
The following copper CMP process may be divided into a main CMP process for removing the bulk plating layer and a final CMP process for removing barrier metal layer 12 formed on first interlayer dielectric layer 10.
FIG. 2B is a schematic view showing the surface of the wafer after performing the main CMP process, in which concave part 14 a may be formed at center part 30 of the wafer. Since a similar removal rate may be applied to center part 30 and edge part 31 of the wafer during the main CMP process, center part 30, which may be formed with a relatively thin plating layer, may be excessively polished. The profile of such concave part 14 a remains as the profile of a concave part on first interlayer dielectric layer 10, which may be a lower layer, even in the final CMP process as shown in FIG. 2C.
To form an upper metal interconnection, a damascene process may be performed again. Accordingly, second interlayer dielectric layer 20 may be formed on first interlayer dielectric layer 10. At this time, barrier insulating layer 18, which may be used as an etch stop layer when the damascene pattern is formed, may be interposed between first interlayer dielectric layer 10 and second interlayer dielectric layer 20.
Referring to FIG. 2D, since first interlayer dielectric layer 10 may have a profile of a concave part formed at the center part thereof, the same profile may be shown in the surface of second interlayer dielectric layer 20 formed on first interlayer dielectric layer 10. Accordingly, barrier metal layer 22 may be formed.
Upper copper plating layer 24 may be formed through the copper ECP process as shown in FIG. 2E. If upper copper plating layer 24 is subject to the main CMP process, copper residue 42 may remain as shown in FIG. 2F. However, even after the final CMP process has been performed to remove barrier metal layer 22, copper residue 42 are not removed, but remain on second interlayer dielectric layer 20 as shown in FIG. 2G.

SUMMARY OF THE INVENTION

Embodiments relate to a method for forming a copper metal interconnection of a semiconductor device.
Embodiments relate to a method for forming a copper metal interconnection through a damascene process that may be capable of minimizing the creation of copper residue.
In embodiments, a method for forming a copper metal interconnection of a semiconductor device through a damascene process may include forming a first copper plating layer on an interlayer dielectric layer of a semiconductor substrate in a plating tank through an electrical-chemical plating scheme for copper while maintaining a first plating distance, determining existence of a concave part by measuring surface uniformity of the first copper plating layer, and forming a second copper plating layer on the first copper plating layer by adjusting a plating distance in the plating tank if the concave part exists in the first copper plating layer.
According to embodiments, a method for forming a copper metal interconnection of a semiconductor device through a damascene process may include forming a first copper plating layer on an interlayer dielectric layer of the semiconductor substrate by performing an electrical-chemical plating scheme with a first plating distance, measuring surface uniformity of the first copper plating layer, and forming a second copper plating layer on the first copper plating layer by adjusting a plating distance according to the surface uniformity of the first copper plating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. is an example illustration of state in which copper residue is generated in a copper metal interconnection created through a dual damascene process according to a related art;
FIGS. 2A to 2G are example sectional diagrams illustrating a generation of copper residue illustrated in FIG. 1;
FIGS. 3A and 3B are example sectional diagrams illustrating a method for forming a copper metal interconnection according to embodiments; and
FIGS. 4A and 4B are example diagram illustrating a profile variation of a copper plating layer according to a plating distance in the method for forming the copper metal interconnection according to embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

Referring to FIG. 3A, after forming barrier metal layer 12 for preventing the diffusion of copper atoms on interlayer dielectric layer 10, a copper seed layer (not shown) may be formed on barrier metal layer 12. Copper plating layer 14 may be formed on interlayer dielectric layer 10, for example by performing an ECP process. If bubbles are centralized at center part 30 of a wafer in a plating tank, a thickness of the plating layer at center part 30 of the wafer may be thinner than a thickness of the plating layer at an edge part of the wafer. Accordingly, concave part 14 a may be formed in copper plating layer 14.
In embodiments, the copper ECP process may be performed in the plating tank in which a plating solution is contained.
FIGS. 4A and 4B show states in which the wafer is arranged in plating tank 100 in which plating solution 110 is contained.
As shown in FIG. 4A, if a distance (that is, a plating distance) between copper anode electrode 120 and the wafer, which are arranged in plating tank 100, is short, an electric field may be formed between anode electrode 120 and the wafer as indicated by arrow 130 a. When the plating distance is short as described above, since a stronger electric field may be formed at the center part of the wafer, copper atoms may be mainly plated at the center part of the wafer.
Accordingly, copper plating layer 140 a formed on the wafer may have a greater thickness in a center part of the wafer than at an edge part of the wafer.
Referring to FIG. 4B, if the plating distance is relatively long, since a stronger electric field may be formed at the edge part of the wafer, copper atoms may be mainly plated at the edge part of the wafer. Accordingly, copper plating layer 140 b formed on the wafer may have a greater thickness in the edge part of the wafer than in the center part of the wafer.
The ECP process may be performed by measuring the optimized plating distance. In embodiments, plating solution 110 may be circulated in plating tank 100, and an electric field may be abnormally formed due to bubbles created during the ECP process. Accordingly, the copper plating layer may not always be uniformly formed on the wafer even if a specific plating distance is maintained.
Referring to FIG. 3A, it may be difficult to completely prevent concave part 14 a from being formed on copper plating layer 14.
However, if concave part 14 a exists at center part 30 of the wafer, a variation of a profile of the copper plating layer according to a plating distance may be used such that a uniformity of the copper plating layer may be improved. If copper plating layer 14 shown in FIG. 3A is formed with a specific plating distance, second copper plating layer 15 may be formed on first copper plating layer 14 by performing the ECP process while adjusting the plating distance as shown in FIG. 3B.
In more detail, after forming first copper plating layer 14, a surface uniformity of the first copper plating layer may be measured so as to determine whether concave part 14 a exists. In embodiments, the existence of concave part 14 a may be predicted by measuring the flow rate of the plating solution in the plating tank or measuring an electric field formed between the copper anode and the wafer. If the initially formed first copper plating layer is formed while maintaining a first plating distance, second plating may be performed by adjusting the plating distance to a distance shorter than the first plating distance. In embodiments, as shown in FIG. 4A, since many more copper atoms may be plated at the center part of the wafer, the concave part exiting in the first copper plating layer may be compensated.
Accordingly, since a copper plating layer may be formed with improved uniformity, copper residue described with reference to FIGS. 2A to 2G may not remain. In contrast, if the first plating distance is relatively long, a concave part may be created at an edge part of the wafer. In this case, second plating may be performed by adjusting a plating distance to a plating distance longer than the first plating distance.
According to embodiments, it may be possible to minimize defects caused by copper residue generated in the process of forming a copper metal interconnection. Accordingly, the yield rate of a semiconductor device may be improved, and manufacturing costs of the semiconductor device may be reduced. The method for forming a copper metal interconnection according to embodiments may be adaptable for a single damascene process as well as a dual damascene process.
It will be apparent to those skilled in the art that various modifications and variations may be made to embodiments. Thus, it is intended that embodiments cover modifications and variations thereof within the scope of the appended claims. It is also understood that when a layer is referred to as being “on” or “over” another layer or substrate, it may be directly on the other layer or substrate, or intervening layers may also be present.

Claims

1. A method comprising:

forming a first copper plating layer on an interlayer dielectric layer of a semiconductor substrate in a plating tank through an electrical-chemical plating process while maintaining a plating distance at a first plating distance;

determining existence of a concave part by measuring surface uniformity of the first copper plating layer; and

forming a second copper plating layer on the first copper plating layer by adjusting the plating distance to a second plating distance in the plating tank if the concave part exists in the first copper plating layer.

2. The method of claim 1, wherein the second plating distance is less than the first plating distance if the concave part exists at a center part of the semiconductor substrate.

3. The method of claim 1, wherein the second plating distance is less than the first plating distance if a thickness of a center part of the semiconductor substrate is less than a thickness at an edge of the semiconductor substrate after forming only the first copper plating layer.

4. The method of claim 1, wherein the second plating distance is greater than the first plating distance if the concave part exists at an edge part of the semiconductor substrate.

5. The method of claim 1, wherein the second plating distance is greater than the first plating distance if a thickness of a center part of the semiconductor substrate is greater than a thickness at an edge of the semiconductor substrate after forming only the first copper plating layer.

6. The method of claim 1, wherein the plating distance comprises a distance between an anode and the semiconductor substrate arranged in the plating tank.

7. A method comprising:

forming a first copper plating layer on an interlayer dielectric layer of a semiconductor substrate by performing an electrical-chemical plating process at a first plating distance;

forming a second copper plating layer on the first copper plating layer by performing the electrical-chemical plating process at a second plating distance according to a surface uniformity of the first copper plating layer.

8. The method of claim 7, further comprising measuring the surface uniformity of the first copper plating layer.

9. The method of claim 7, wherein the second plating distance is shorter than the first plating distance if a concave part exists at a center part of the first copper plating layer.

10. The method of claim 7, wherein the second plating distance is less than the first plating distance if a thickness of a center part of the first copper plating layer is less than a thickness at an edge of the first copper plating layer.

11. The method of claim 7, wherein the second plating distance is longer than the first plating distance if a concave part exists at an edge part of the first copper plating layer.

12. The method of claim 7, wherein the second plating distance is greater than the first plating distance if a thickness of a center part of the first copper plating layer is greater than a thickness at an edge of the first copper plating layer.

13. The method of claim 7, wherein the plating distance comprises a distance between an anode and the semiconductor substrate arranged in the plating tank.

14. A device, comprising:

an interlayer dielectric layer formed over a semiconductor substrate; and

a copper layer formed over the interlayer dielectric layer,

wherein the copper layer is formed by forming a first copper plating layer over the interlayer dielectric layer by performing an electrical-chemical plating process at a first plating distance and forming a second copper plating layer on the first copper plating layer by performing the electrical-chemical plating process at a second plating distance according to a surface uniformity of the first copper plating layer.

15. The device of claim 14, wherein the second plating distance is less than the first plating distance if a thickness of a center part of the first copper plating layer is less than a thickness at an edge of the first copper plating layer.

16. The method of claim 15, wherein a surface of the copper layer formed over the interlayer dielectric layer is substantially uniform in thickness.

17. The method of claim 14, wherein the second plating distance is greater than the first plating distance if a thickness of a center part of the first copper plating layer is greater than a thickness at an edge of the first copper plating layer.

18. The method of claim 17, wherein a surface of the copper layer formed over the interlayer dielectric layer is substantially uniform in thickness.