WO2020138976A1

WO2020138976A1 - Method for manufacturing semiconductor device

Info

Publication number: WO2020138976A1
Application number: PCT/KR2019/018520
Authority: WO
Inventors: 유봉영; 박기문; 이진현
Original assignee: 한양대학교에리카산학협력단
Priority date: 2018-12-26
Filing date: 2019-12-26
Publication date: 2020-07-02

Abstract

A method for manufacturing a semiconductor device is provided. The method for manufacturing the semiconductor device comprises the steps of: preparing a base substrate structure having recessed regions; depositing a material film on the base substrate structure having the recessed regions so as to fill the recessed regions with same; and forming a material film pattern in the recessed regions by removing the material film in exclusion of the recessed regions by ionizing the material of the material film, leaving behind the material film in the recessed regions.

Description

Method for manufacturing semiconductor device

The present application relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including forming a material film pattern in a recess region.

When manufacturing a semiconductor device, deposition and selective removal of a metal layer are important processes. A typical semiconductor wafer has multiple metal layers deposited or plated on the surface, each successive layer being polished or etched before another layer is added. In particular, it is widely practiced to electroplate copper on the wafer surface. Typically, after plating of copper (which usually makes a copper overlay on the wafer), a chemical-mechanical polishing (CMP) process is generally used to remove unwanted portions of the plating layer. have.

In a typical CMP process, the substrate (eg, wafer) is placed in contact with a rotating polishing pad attached to a platen. CMP slurry, typically a polishing and chemical reaction mixture, is supplied to the pad during the CMP process of the substrate. During the CMP process, the pads (fixed to the platen) and the substrate rotate, while the wafer carrier system or polishing head exerts pressure (downward force) against the substrate. The slurry undergoes a planarization (polishing) process by chemical mechanical interaction, and the substrate film is planarized due to the effect of the rotational motion of the pad relative to the substrate. Polishing continues in this way until a given film on the substrate is removed, and the usual purpose of polishing is to effectively planarize the substrate.

However, in the CMP process, there is a problem that the process cost is high along with the problem of scratches, contamination and corrosion by particles contained in the slurry. Accordingly, in the semiconductor process, a problem occurring in the CMP process is solved, and a method for performing a planarization process has been continuously studied.

One technical problem to be solved by the present application is to provide a method for manufacturing a semiconductor device with a simplified manufacturing process.

Another technical problem to be solved by the present application is to provide a method of manufacturing a semiconductor device capable of solving a problem (scratch, contamination, corrosion, etc. caused by particles contained in the slurry) generated in the CMP process by omitting the CMP process. Having

Another technical problem to be solved by the present application is to provide a method for manufacturing a semiconductor device with reduced manufacturing cost.

Another technical problem to be solved by the present application is to provide a method for manufacturing a semiconductor device with improved reliability.

The technical problem to be solved by the present application is not limited to the above.

In order to solve the above technical problems, the present application provides a method for manufacturing a semiconductor device.

According to one embodiment, the method of manufacturing the semiconductor device comprises: preparing a base substrate structure having a recess region, depositing a material film on the base substrate structure having the recess region, and thereby forming the recess Filling a region, and ionizing a material of the material film to remove the material film outside the recess area, and remaining the material film in the recess area to form a material film pattern in the recess area can do.

According to one embodiment, the step of ionizing the material of the material film includes: immersing the base substrate structure having the material film in an electrolyte, a first removing step of applying a first voltage to the material film, and the material A second removing step of applying a second voltage having a lower level than the first voltage to the film may be included.

According to an embodiment, the method of manufacturing the semiconductor device may include applying the second voltage immediately after the first voltage is applied (directly after).

According to an embodiment, the rate at which the material of the material film is ionized in the first removal step may include a rate faster than the rate at which the material of the material film is ionized in the second removal step.

According to one embodiment, the second voltage may include more than 0.5V and less than 1.6V.

According to an embodiment, the electrolyte may include phosphoric acid (H ₃ PO ₄ ), and the concentration of the phosphoric acid may be 50 wt% or more.

According to an embodiment, as the concentration of the phosphoric acid decreases, the ionization rate of the material may be increased.

According to an embodiment, before depositing the material layer, further comprising forming a barrier layer on the base substrate structure along an inner surface of the recess region, wherein the electrolyte etches the barrier layer. It may include a barrier etchant.

According to an embodiment, the barrier layer may include any one of titanium (Ti) and tantalum (Ta).

According to an embodiment, while the electrolyte is stirred, the first and second voltages may be applied to the material layer.

According to an embodiment, the recess region may be a trench, and the material layer pattern may include metal wiring.

According to an embodiment, the recess region may be a via-hole penetrating the base substrate, and the material layer pattern may include a through silicon via (TSV).

According to one embodiment, the material film may include a copper film.

According to another embodiment, a method of manufacturing the semiconductor device includes: preparing a base substrate, depositing a material film on the base substrate, immersing the base substrate on which the material film is deposited, in an electrolyte, and the material And sequentially applying a first voltage to the film and a second voltage at a level lower than the first voltage to ionize the material of the material film to remove at least a portion of the material film.

According to another embodiment, the removal rate of the material layer decreases to a first slope according to an increase in voltage in the first voltage section, and the removal rate of the material layer decreases according to an increase in voltage in the second voltage section. A second section increasing to is provided, and the size of the second slope of the second section is greater than the size of the first slope of the first section, and the first voltage is selected from the second voltage section. , The second voltage may include selected from the first voltage section.

A method of manufacturing a semiconductor device according to an embodiment of the present application includes preparing a base substrate structure having a recess region, depositing a material film on the base substrate structure having the recess region, and filling the recess region And forming a material film pattern in the recessed area by ionizing a material of the material film, removing the material film outside the recessed area, and remaining the material film in the recessed area. have.

Accordingly, damage to the film quality (scratch, contamination, corrosion, etc. by particles contained in the slurry) according to the process of forming the material film pattern in the recess region can be prevented. In addition, at a simple and low cost, a highly reliable metal wiring or through silicon via (TSV) can be manufactured.

1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application.

2 to 7 are views showing a manufacturing process of a semiconductor device according to the first embodiment of the present application.

8 to 11 are views showing a manufacturing process of a semiconductor device according to a modification of the first embodiment of the present application.

12 to 16 are views showing a manufacturing process of a semiconductor device according to a second embodiment of the present application.

17 and 18 are photographs of results obtained by electropolishing in the process of manufacturing a semiconductor device according to Example 1 of the present application.

19 is a photograph of a semiconductor device according to Example 1 of the present application taken at different magnifications and angles.

20 is a photograph showing EDS analysis of a semiconductor device according to Comparative Example 1 of the present application.

21 is a photograph showing EDS analysis of a semiconductor device according to Example 1 of the present application.

22 is a photograph of a semiconductor device according to Example 1 of the present application.

23 is a photograph of a state before the electropolishing process is performed in the manufacturing process of the semiconductor device according to Comparative Example 1 of the present application.

24 is a photograph of a state after an electropolishing process is performed in the process of manufacturing a semiconductor device according to Comparative Example 1 of the present application.

25 is a photograph comparing the effect of removing the barrier layer according to the concentration of ammonium fluoride (NH ₄ F) contained in the electrolyte.

26 is a photograph showing a state in which a copper film is deposited in a via hole in a process of manufacturing a semiconductor device according to Example 3 of the present application.

27 is a photograph of a semiconductor device according to Example 3 of the present application.

28 and 29 are graphs comparing the effect of the concentration of phosphoric acid contained in the electrolyte.

30 is a photograph comparing the effect of stirring the electrolyte in the manufacturing process of the semiconductor device according to Example 1 of the present application.

31 and 32 are graphs comparing the effect of stirring the electrolyte in the manufacturing process of the semiconductor device according to Example 1 of the present application.

33 and 34 are pictures comparing semiconductor devices according to Examples 1 and 2 of the present application.

35 are graphs comparing the effects of electrolyte agitation in the manufacturing process of a semiconductor device according to Example 2 of the present application.

FIG. 36 are SEM photographs comparing the effect of stirring the electrolyte and the effect of concentration of phosphoric acid in the manufacturing process of the semiconductor device according to Example 1 of the present application.

37 is a graph for comparing the effect of stirring the electrolyte and the effect of concentration of phosphoric acid in the manufacturing process of the semiconductor device according to Example 1 of the present application.

FIG. 38 are AFM photographs comparing the effect of stirring the electrolyte and the effect of concentration of phosphoric acid in the manufacturing process of the semiconductor device according to Example 1 of the present application.

39 and 40 are SEM photographs comparing the effect of electrolyte agitation in the manufacturing process of the semiconductor device according to Example 2 of the present application.

41 is a graph showing the degree of ionization of copper according to a voltage applied in an electropolishing process for removing a copper film.

42 is a photograph showing semiconductor elements photographed in each section shown in FIG. 41.

43 and 44 are pictures comparing the effect of the amount of charge applied in the electropolishing process for the removal of the copper film.

45 is a graph showing a change in the thickness of the copper film according to the amount of charge applied in the electropolishing process for removing the copper film.

Hereinafter, preferred embodiments of the present application will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present application is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete and that the spirit of the present application is sufficiently conveyed to those skilled in the art.

In this specification, when a component is referred to as being on another component, it means that it may be formed directly on another component, or a third component may be interposed between them. In addition, in the drawings, the thickness of the films and regions are exaggerated for effective description of the technical content.

In addition, in various embodiments of the present specification, terms such as first, second, and third are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Therefore, what is referred to as the first component in one embodiment may be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Also, in this specification,'and/or' is used to mean including at least one of the components listed before and after.

In the specification, a singular expression includes a plural expression unless the context clearly indicates otherwise. Also, terms such as “include” or “have” are intended to indicate the presence of features, numbers, steps, elements, or combinations thereof described in the specification, and one or more other features, numbers, steps, or configurations. It should not be understood as excluding the possibility or presence of elements or combinations thereof. In addition, in this specification, "connecting" is used in a sense to include both indirectly connecting a plurality of components, and directly connecting.

In addition, in the following description of the present application, when it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the subject matter of the present application, the detailed description will be omitted.

1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application, and FIGS. 2 to 7 are views showing a manufacturing process of the semiconductor device according to the first embodiment of the present application.

1 and 2, the base substrate structure 100 may be prepared (S100). According to one embodiment, the base substrate structure 100 may include a semiconductor substrate, a metal substrate, a plastic substrate, or a glass substrate. For example, the base substrate structure 100 may include a silicon (Si) semiconductor substrate.

The base substrate structure 100 may have a recess region 110. According to an embodiment, the recess region 110 may be a trench. Accordingly, the base substrate structure 100 may be a semiconductor substrate with trenches. For example, the depth of the trench may be 3 μm. The recess region 110 may be formed directly on the semiconductor substrate, or may be formed on a film formed on the semiconductor substrate.

Referring to FIG. 3, a barrier layer 200 may be formed on the base substrate structure 100. The barrier layer 200 may be formed along the inner surface of the recess region 110. In other words, the barrier layer 200 may be conformally formed along the surface profile of the base substrate structure 100 having the recess region 110. The barrier layer 200 can prevent the material of the material film to be described later from being diffused. In addition, the barrier layer 200 may improve adhesion between a material film, which will be described later, and the base substrate structure 100.

According to one embodiment, the barrier layer 200 may include titanium (Ti). Or, alternatively, according to another embodiment, the barrier layer 200 is titanium nitride (TiN), silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN) ), tantalum silicon nitride (TaSiN). According to one embodiment, the barrier layer 200 may be formed to a thickness of 20 nm.

Referring to FIG. 4, a seed layer 300 may be formed on the base substrate structure 100 on which the barrier layer 200 is formed. According to one embodiment, the seed layer 300 may include a metal. The seed layer 300 may be formed on the barrier layer 200 along the inner surface of the recess region 110. For example, the metal may be copper (Cu). According to one embodiment, the seed layer 300 may be formed by an electroless plating method. According to one embodiment, the seed layer 300 may be formed to a thickness of 150 nm.

5, a boundary surface between the seed layer 300 and the material layer 400 may not be substantially distinguished.

In addition, the seed layer 300 may be formed of the same material (for example, copper) as the material film 400, and in the removal process of the material film 400 described later, the material film 400 In addition, a portion of the seed layer 300 disposed outside the recess region 110 may be removed.

1 and 5, a material film 400 may be deposited on the base substrate structure 100 on which the seed layer 300 is formed. The material layer 400 may fill the recess region 110 (S200).

According to one embodiment, the material film 400 may be deposited by an electrolytic deposition method. For a specific example, the deposition of the material film 400 may be performed in a solution containing 1000 mM copper sulfate (CuSO ₄ ), 580 mM sulfuric acid (H ₂ SO ₄ ), and 1.9 mM hydrochloric acid (HCl). In addition, the deposition of the material film 400 may be performed for 300 s under conditions of a current density of -30 mA/cm ² and a temperature of 25°C.

According to another embodiment, the material film 400 may be formed by various methods such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

The material layer 400 may completely fill the recess region 110. In addition, the material layer 400 may be formed on the base substrate structure 100 outside the recess region 110. In other words, the material layer 400 may fill the recess region 110 and cover the upper surface of the base substrate structure 100.

1, 6, and 7, the material layer 400 other than the recess region 110 is removed, and the material layer 400 in the recess region 110 may remain. . Accordingly, a material film pattern 500 may be formed in the recess region 110 (S300). That is, the material film pattern 500 may be the material film 400 remaining in the recess region 110, and the upper surface of the material film pattern 500 and the base substrate structure 100 The upper surface can form a coplanar surface. In other words, until the upper surface of the base substrate structure 100 and the upper surface of the material film 400 remaining in the recess region 110 form a coplanar surface, the material film 400 and the barrier layer ( 200), and the seed layer 300 may be removed.

According to one embodiment, the material layer pattern 500 may be a metal wiring. Specifically, for example, the material film pattern 500 may be copper (Cu) wiring.

The material film 400 may be removed by ionizing the material of the material film 400. According to one embodiment, the step of ionizing the material of the material film 400 is a step of immersing the base substrate structure 100 having the material film 400 in an electrolyte, the material film 400 A first removing step of applying a first voltage, and a second removing step of applying a second voltage to the material layer 400 may be included. The second voltage may be lower than the first voltage.

After the first voltage is applied (directly after), the second voltage may be applied. In other words, the first voltage and the second voltage may be applied sequentially. That is, in one process, after the first voltage is applied, the second voltage may be applied.

Alternatively, according to another embodiment, before the first voltage is applied and the second voltage is applied, a step of stirring the electrolyte may be performed. In this case, as the first voltage of a relatively high level is applied, a pitting phenomenon in which a hole is formed in the surface of the material film 400 can be prevented.

According to an embodiment, in the removing step of the material layer 400, as the voltage applied to the material layer 400 increases, the removal period of the material layer 400 is different from each other in a first section and a second section. Sections may appear.

Specifically, the first section may be a section in which the removal rate of the material layer 400 decreases with a first slope according to an increase in voltage in the first voltage section. For example, the first voltage section may be a section in which a voltage applied to the material layer 400 is greater than 0.5V and less than 1.6V. Alternatively, the second section may be a section in which the removal rate of the material layer 400 increases at a second slope according to an increase in voltage in the second voltage section. For example, the second voltage section may be a section in which a voltage applied to the material layer 400 is 1.6 V or more.

The size of the second slope of the second section may be greater than the size of the first slope of the first section. Accordingly, in the first section, the amount of change in the removal rate of the material layer 400 may be smaller than the second section. That is, when a voltage is applied within the first section, the material of the material film 400 may be ionized stably and substantially uniformly.

Alternatively, in the second section, the amount of change in the removal rate of the material layer 400 may be greater than the first section. That is, the rate at which the material of the material film 400 is ionized in the second section may be faster than the rate at which the material of the material film 400 is ionized in the first section.

According to an embodiment, the first voltage in the first removal step described above may be selected in the second voltage section. Alternatively, the second voltage in the second removal step may be selected in the first voltage section.

That is, in the first removal step, the material film 400 may be removed at a relatively high speed, and in the second removal step, the material film 400 may be removed relatively stably and uniformly. Accordingly, not only can the process time for removing the material film 400 be shortened, but also the etching uniformity of the material film 400 is improved, and the material film pattern in the recess region 110 ( 500) can be improved.

In a voltage range lower than the first voltage period, the material of the material film 400 may not be substantially ionized. That is, in a voltage range lower than the first voltage section, the material layer 400 may not be substantially removed.

According to an embodiment, while the electrolyte is stirred, the first voltage and the second voltage may be sequentially provided to the material layer 400. Accordingly, the formation efficiency of the material film pattern 500 may be improved. That is, the removal of the material layer 400 can be performed within a relatively fast time, and the etching uniformity of the material layer 400 can also be improved.

According to one embodiment, the electrolyte may include an acidic solution. For example, the acidic solution may include a phosphoric acid (H ₃ PO ₄ ) solution. According to one embodiment, in the electrolyte, the concentration of the phosphoric acid may be 50 wt% or more. Alternatively, when the concentration of the phosphoric acid in the electrolyte is less than 50 wt%, as described above, the first section in which the material of the material film 400 is uniformly and stably removed may not exist, Accordingly, it is not easy to form the material layer pattern 500 in the recess region 110. In other words, it is not easy to set process conditions in which the upper surface of the base substrate structure 100 and the upper surface of the material film pattern 500 form a coplanar surface. In addition, the material film 400 is removed unevenly and unstablely, so that the film quality of the material film pattern 500 in the recess region 110 may be deteriorated. Accordingly, according to an embodiment of the present application, the concentration of the phosphoric acid in the electrolyte may be 50 wt% or more.

Further, according to an embodiment, according to the concentration of the phosphoric acid, the ionization rate of the material of the material film 400 may be controlled. Specifically, as the concentration of the phosphoric acid is lowered, the ionization rate of the material may be increased. As a result, the lower the concentration of the phosphoric acid in the electrolyte, the faster the removal rate of the material film 400 can be.

Further, according to an embodiment, according to the concentration of the phosphoric acid, the first voltage section corresponding to the first section in which the material of the material film 400 is uniformly and stably removed may be extended. Therefore, when the concentration of the phosphoric acid is relatively high, the process conditions can be set relatively easily.

The electrolyte may further include a barrier etchant. The barrier etchant may etch the barrier layer 200. At the same time that the material film 400 is removed, the barrier layer 200 may also be removed. That is, the barrier layer 200 and the material layer 400 may be removed together. Specifically, when the material of the material film 400 is ionized and removed, when the material film 400 and the seed layer 300 are removed, the barrier layer 200 is exposed, The barrier layer 200 may be removed by the barrier etchant. That is, a portion of the barrier layer 200 disposed outside the recess region 110 is removed, and between the inner surface of the recess region 110 and the material layer pattern 500, the barrier layer 200 This can remain.

For example, the barrier etchant may include ammonium fluoride (NH ₄ F). Specifically, ammonium fluoride may react with water in an aqueous solution to form hydrofluoric acid (HF). Accordingly, the barrier layer 200 may be etched by hydrofluoric acid.

According to one embodiment, the concentration of the barrier etchant may be controlled. Specifically, the barrier etchant may include ammonium fluoride (NH ₄ F) at a concentration of 0.5 to 2M. When the concentration of ammonium fluoride is less than 0.5M, the barrier layer 200 outside the recess region 110 may not be completely removed, and when the concentration of ammonium fluoride exceeds 2M, hydrofluoric acid by ammonium fluoride may cause Films (eg, interlayer insulating films) may be damaged. Accordingly, according to an embodiment of the present application, the concentration of ammonium fluoride may be 0.5 ~ 2M.

The method for manufacturing a semiconductor device according to the first embodiment of the present application has been described above. Hereinafter, a method of manufacturing a semiconductor device according to a modification of the first embodiment of the present application will be described with reference to FIGS. 8 to 11.

The manufacturing method of the semiconductor device according to the modification of the first embodiment of the present application is the same as the manufacturing method of the semiconductor device according to the first embodiment described with reference to FIGS. 1 to 7, but the modification of the first embodiment In the semiconductor device according to an example, the seed layer 300 may be omitted. That is, after the material layer 400 is deposited on the barrier layer 200, the barrier layer 200 and the material layer 400 disposed outside the recess region 110 may be removed.

In the above, the manufacturing method of the semiconductor device according to the first embodiment and the modification of the first embodiment of the present application has been described. Hereinafter, a method of manufacturing a semiconductor device according to a second embodiment of the present application will be described.

12 to 17 are views showing a manufacturing process of a semiconductor device according to a second embodiment of the present application.

Referring to FIG. 12, the base substrate structure 100 may be prepared. According to one embodiment, the base substrate structure 100 may include a semiconductor substrate, a metal substrate, a plastic substrate, or a glass substrate. For example, the base substrate structure 100 may include a silicon (Si) semiconductor substrate.

The base substrate structure 100 may have a recess region 110. That is, the base substrate structure 100 may include a semiconductor substrate on which a recess region is formed. According to an embodiment, the recess region 110 may be a via-hole. Accordingly, the base substrate structure 100 may be a semiconductor substrate on which via holes are formed.

Referring to FIG. 13, a barrier layer 200 may be formed on the base substrate structure 100. The barrier layer 200 may be formed along the inner surface of the recess region 110. The barrier layer 200 can prevent the material of the material film to be described later from being diffused. In addition, the barrier layer 200 may improve adhesion between a material film, which will be described later, and the base substrate structure 100.

According to an embodiment, the barrier layer 200 may include tantalum (Ta). Alternatively, according to another embodiment, the barrier layer 200 may include titanium (Ti), titanium nitride (TiN), silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tantalum nitride ( TaN) and tantalum silicon nitride (TaSiN).

Referring to FIG. 14, a material layer 400 may be deposited on the base substrate structure 100 on which the barrier layer 200 is formed. The material layer 400 may fill the recess region 110. For example, the material film 400 may be a copper film.

According to one embodiment, the material film 400 may be deposited by an electrolytic deposition method. In this case, a seed layer may be formed on the base substrate structure 100 before forming the material layer 400. Alternatively, according to another embodiment, the material film 400 may be formed by various methods such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

15 and 16, the material layer 400 other than the recess region 110 may be removed, and the material layer 400 in the recess region 110 may remain. Accordingly, a material film pattern 500 may be formed in the recess region 110. That is, the material layer pattern 500 may be the material layer 400 remaining in the recess region 110.

The material film 400 may be removed by the method described with reference to FIGS. 1 to 7.

According to an embodiment, the lower region of the base substrate structure 100 may be removed so that both ends of the material layer pattern 500 are exposed. Accordingly, the semiconductor substrate structure 700 can be manufactured. In this case, the material layer pattern 500 in the semiconductor substrate structure 700 may be a through silicon via (TSV). That is, when a plurality of the semiconductor substrate structures 700 are stacked, the material film pattern 500 may be connected to form an electrical passage. For example, as described above, after the material layer pattern 500 is formed, a front end of line (FEOL) and a back end of line (BEOL) process are performed, and a lower region of the base substrate structure 100 After this is removed, or the FEOL process is performed and the material film pattern 500 is formed and the BEOL process is performed, the lower region of the base substrate structure 100 is removed, or the FEOL and BEOL processes are performed and the The material film pattern 500 may be formed. That is, the process of forming the material layer pattern 500 according to the embodiment of the present application may be combined in various ways with the FEOL process and the BEOL process.

A method of manufacturing a semiconductor device according to an embodiment of the present application includes preparing the base substrate structure 100 having the recess region 110 and the base substrate structure 100 having the recess region 110. ) Depositing the material film 400 on the substrate, filling the recess region 110, and ionizing the material of the material film 400, so that the material film other than the recess region 110 ( 400) may be removed, and the material layer 400 in the recess region 110 may remain, thereby forming the material layer pattern 500 in the recess region 110.

Accordingly, the conventional chemical mechanical polishing process for forming the material film pattern 500 may be omitted or simplified, and scratches, contamination, and corrosion due to particles contained in the slurry input in the chemical mechanical polishing process may be performed. The problem can be minimized. In addition, a dipping phenomenon in which a top surface of the material layer pattern 500 is concave (dent) by a chemical mechanical polishing process may be minimized. Due to this, the upper surface of the base substrate structure 100 and the upper surface of the material film pattern 500 can be substantially flat and coplanar, and the manufacturing process is simple and the manufacturing cost is high. This reduced, high-quality and highly reliable metal wiring or manufacturing process of TSV can be provided.

In the above, a method of manufacturing a semiconductor device according to an embodiment of the present application has been described. Hereinafter, specific experimental examples and characteristic evaluation results of a method for manufacturing a semiconductor device according to an embodiment of the present application will be described.

Semiconductor device fabrication according to Example 1

After preparing a silicon substrate having a trench having a depth of 3 μm, a titanium (Ti) layer was formed on the silicon substrate along the inner surface of the trench. Thereafter, a copper (Cu) seed layer was formed on the titanium layer, and a copper film was deposited on the silicon substrate on which the copper seed layer was formed by electrolytic deposition. Specifically, in a solution containing 1000 mM copper sulfate (CuSO ₄ ), 580 mM sulfuric acid (H ₂ SO ₄ ), and 1.9 mM hydrochloric acid (HCl), at a current density of −30 mA/cm ² , at a temperature of 25° C. Electrolytic deposition was performed for a time of 300 s to deposit a copper film.

Subsequently, an electropolishing method of applying a voltage after immersing the silicon substrate on which the copper film is deposited in the electrolyte, removes the copper film other than the trench, and retains the copper film in the trench, the semiconductor device according to Example 1 Was prepared. More specifically, in the electrolytic polishing process for removing the copper film, the silicon substrate on which the above-described copper film was deposited was used as a working electrode, a platinum sheet (Pt sheet) was used as a counter electrode, and Ag/AgCl was used as a reference electrode. . Further, as an electrolyte, a solution in which phosphoric acid (H ₃ PO ₄ ) and ammonium fluoride (NH ₄ F) were mixed was used.

Semiconductor device fabrication according to Example 2

A semiconductor device is manufactured by the method for manufacturing a semiconductor device according to the first embodiment described above, but in an electropolishing process of removing the copper film, after applying a first voltage to a silicon substrate on which the copper film is deposited, a level lower than the first voltage A second voltage was applied.

Semiconductor device fabrication according to Example 3

After preparing a silicon substrate having a via-hole, a tantalum (Ta) layer was formed on the silicon substrate along the inner surface of the via hole. Subsequently, a method for manufacturing the semiconductor device according to Example 1 described above was performed to manufacture a semiconductor device according to Example 3.

Semiconductor device fabrication according to Example 4

After preparing a silicon substrate having a via-hole, a tantalum (Ta) layer was formed on the silicon substrate along the inner surface of the via hole. Subsequently, a method of manufacturing the semiconductor device according to Example 2 described above was performed to manufacture a semiconductor device according to Example 4.

Semiconductor device fabrication according to Comparative Example 1

A semiconductor device is manufactured by the method for manufacturing a semiconductor device according to Example 1 described above, but in the electropolishing process of removing the copper film, ammonium fluoride (NH ₄ F) is not included, and phosphoric acid (H ₃ PO ₄ ) is included. An electrolyte was used to manufacture a semiconductor device according to Comparative Example 1.

The manufacturing method of the semiconductor device according to Examples 1 to 4 and Comparative Example 1 is summarized through <Table 1> below.

구분division	리세스 구조Recess structure	전해연마 단계 전압인가 횟수Electrolytic polishing step voltage application count	전해질Electrolyte
실시 예 1Example 1	트렌치(Trench)Trench	1One	H₃PO₄+NH₄FH ₃ PO ₄ +NH ₄ F
실시 예 2Example 2	트렌치(Trench)Trench	22	H₃PO₄+NH₄FH ₃ PO ₄ +NH ₄ F
실시 예 3Example 3	비아-홀(Via-hole)Via-hole	1One	H₃PO₄+NH₄FH ₃ PO ₄ +NH ₄ F
실시 예 4Example 4	비아-홀(Via-hole)Via-hole	22	H₃PO₄+NH₄FH ₃ PO ₄ +NH ₄ F
비교 예 1Comparative Example 1	트렌치(Trench)Trench	1One	H₃PO₄ H ₃ PO ₄

17 and 18 are photographs of results obtained by electropolishing in the process of manufacturing a semiconductor device according to Example 1 of the present application. Referring to FIG. 17, in the manufacturing process of the semiconductor device according to Example 1, before performing electropolishing (Before Electropolishing) and after performing electropolishing (After Electropolishing), SEM (Scanning Electron Microscope), respectively, Photographs were taken, and the results were shown. FIG. 17(a) shows a state in which a trench is filled with 5 μm line width and 1 μm pitch, and FIG. 17(b) shows a state where a trench is filled with 1 μm line width and 2 μm pitch, and FIG. 17 (C) shows a state in which a copper film is filled in a trench having a 2 μm line width and a 2 μm pitch. As can be seen from (a) to (c) of FIG. 17, as electropolishing was performed, it was confirmed that copper films other than the trench were easily removed. Referring to FIG. 18, a top view of a semiconductor device according to Example 1 is photographed and illustrated. As can be seen in Figure 19, in the case of a semiconductor device in which electropolishing was performed, it was confirmed that the copper film other than the trench was easily removed.

The specific manufacturing process conditions of the semiconductor device according to Example 1 photographed in FIG. 19 are as follows. The copper film deposition process was performed at -30 mA/cm ² current and 9 C/cm ² conditions, and the copper film removal process was 70 wt% H ₃ PO ₄ +1.0M NH4F electrolyte, 1.3 V potential ( Potential), 7.5C/cm ² .

Referring to (a) to (c) of FIG. 19, the top view of the semiconductor device according to Example 1 is shown by SEM photographing at different magnifications. Referring to FIG. 19(d), the The side view of the semiconductor device according to Example 1 is shown by SEM photographing. 19(a) to (d), it was confirmed that copper films other than the trench were easily removed.

20 is a photograph showing EDS analysis of a semiconductor device according to Comparative Example 1 of the present application, FIG. 21 is a photograph showing EDS analysis of a semiconductor device according to Example 1 of the present application, and FIG. 22 is an embodiment of the present application This is a picture of a semiconductor device according to 1.

20 and 21, EDS (Energy Dispersive X-ray Spectroscopy) analysis of the semiconductor device according to Comparative Example 1 and the semiconductor device according to Comparative Example 2 was photographed and shown, and referring to FIG. 22, the implementation The semiconductor device according to Example 1 is shown by SEM photographing in a side view.

20 to 22, in the case of the semiconductor device according to Comparative Example 1, the titanium layer was not removed, but in the case of the semiconductor device according to Example 1, it was confirmed that the titanium layer was also removed together with the copper film. there was. That is, it was confirmed that ammonium fluoride (NH ₄ F) contained in the electrolyte is removed from the titanium layer during the electropolishing process of the copper film.

23 is a photograph of a state before an electropolishing process is performed in the process of manufacturing a semiconductor device according to Comparative Example 1 of the present application, and FIG. 24 is an electropolishing in the process of manufacturing a semiconductor device according to Comparative Example 1 of the present application This is a photograph of the state after the process has been performed.

Referring to FIG. 23, the state before the electropolishing process is performed in the manufacturing process of the semiconductor device according to Comparative Example 1 is shown by SEM photographing. The specific process conditions for the copper film deposition are as follows. Copper film deposition was performed under the conditions of -30 mA/cm ² (Current) and 9 C/cm ² . As can be seen in FIG. 24, it was confirmed that deposition of the copper film in the trench was easily performed.

Referring to FIG. 24, a state after an electropolishing process is performed in the manufacturing process of the semiconductor device according to Comparative Example 1 is shown by SEM photographing. The specific process conditions for copper film removal are as follows. Copper film removal was performed at 70 wt% H ₃ PO ₄ electrolyte, 1.3V Potential, 7.5 C/cm ² .

As can be seen in FIG. 24, in the case of the semiconductor device according to Comparative Example 1, although the removal of the copper film occurred, it was confirmed that the titanium (Ti) layer formed between the copper film and the silicon substrate structure was not removed.

Referring to (a) of FIG. 25, the semiconductor device according to Example 1 was photographed by SEM. In the manufacturing process of the semiconductor device photographed in FIG. 25A, specific process conditions for removing the copper film are as follows. Copper film removal was performed under the conditions of 70 wt% H ₃ PO ₄ + 1.0M NH ₄ F electrolyte, 1.3V potential, 7.5 C/cm ² .

Referring to FIG. 25B, the semiconductor device according to Example 1 was photographed by SEM. In the manufacturing process of the semiconductor device photographed in FIG. 25B, specific process conditions for removing the copper film are as follows. Copper film removal was performed under conditions of 70 wt% H ₃ PO ₄ + 2.0M NH ₄ F electrolyte, 1.3V Potential, 7.5 C/cm ² .

Referring to (c) of FIG. 25, a semiconductor device according to Example 1 is photographed by SEM. In the manufacturing process of the semiconductor device photographed in FIG. 25C, specific process conditions for removing the copper film are as follows. Copper film removal was performed under conditions of 70 wt% H ₃ PO ₄ + 2.5M NH ₄ F electrolyte, 1.3V potential, 7.5 C/cm ² .

As can be seen from (a) to (c) of FIG. 25, in the case of the semiconductor device according to Example 1, it was confirmed that copper film removal outside the trench region was easily performed. In addition, it was confirmed that regardless of the concentration of ammonium fluoride contained in the electrolyte, the titanium layer disposed between the copper film and the silicon substrate structure was easily removed.

26 is a photograph showing a state in which a copper film is deposited in a via hole in the process of manufacturing a semiconductor device according to Example 3 of the present application, and FIG. 27 is a photograph of a semiconductor device according to Example 3 of the present application .

Referring to FIG. 26, in the process of manufacturing the semiconductor device according to Example 3, after depositing a copper film in a via hole, a cross-section of a silicon substrate structure in which the copper film is deposited is photographed and illustrated. 26, it was confirmed that the copper film was easily filled in the via hole.

Referring to FIG. 27, a semiconductor device according to Example 3 is photographed by SEM. As can be seen in FIG. 27, it was confirmed that the semiconductor device according to the third embodiment, the copper film other than the via hole was easily removed. In addition, as the copper film was filled in the via hole, it was confirmed that it can be used as a through silicon via (TSV).

28 and 29, the semiconductor device according to the first embodiment, which is manufactured using an electrolyte containing 50 wt% of H ₃ PO _4, is prepared using an electrolyte containing 60 wt% of H ₃ PO ₄ The semiconductor device according to the first embodiment, manufactured using an electrolyte containing 70 wt% of H ₃ PO _{4 The} semiconductor device according to the first embodiment, manufactured using an electrolyte containing 85 wt% of H ₃ PO ₄ Preparation using a semiconductor device according to the first embodiment, an electrolyte containing 30 wt% of H ₃ PO ₄ and an electrolyte comprising 10 wt% of H ₃ PO ₄ according to the first embodiment For each of the semiconductor devices according to the first embodiment, in the copper film electropolishing process, the potential (Pontential(V) [vs. Ag/AgCl]) is changed with time, and thus the current density (mA) /cm ² ) The change was measured.

As can be seen in FIGS. 28 and 29, in the case of a semiconductor device manufactured using an electrolyte containing 30 wt% and 10 wt% of H ₃ PO ₄ , it was confirmed that the current density change according to the potential change is irregularly generated. Could.

However, in the case of a semiconductor device manufactured using an electrolyte containing 50 wt%, 60 wt%, 70 wt%, and 85 wt% of H ₃ PO ₄ , the change in current density according to the potential change shows a constant trend. I could confirm.

In addition, in the case of a semiconductor device manufactured using an electrolyte containing 50 wt%, 60 wt%, 70 wt%, and 85 wt% of H ₃ PO ₄ , the lower the concentration of H ₃ PO _4, the higher the current density. It was confirmed that it appeared.

As a result, in the electropolishing process for removing the copper film, the concentration of phosphoric acid should be used at least 50 wt%, it was confirmed that as the concentration of phosphoric acid is lowered, the ionization rate of copper is increased.

Referring to FIG. 30, the semiconductor device is manufactured according to the method of manufacturing the semiconductor device according to the first embodiment, but the time during which the electrolyte is stirred during the copper film removal process is controlled, and thus the manufactured embodiment 1 The semiconductor device according to was photographed. In the semiconductor device of the picture taken in FIG. 30, electrolytic polishing for removing the copper film was performed in an electrolyte containing 85 wt% of H ₃ PO ₄ .

30 (a) shows a case in which stirring was performed for 300 s for an electropolishing time of 300 s, and FIG. 30 (b) performed electropolishing for 300 s, but did not perform stirring for 60 s after performing stirring for 240 s. FIG. 30(c) shows a case in which electrolytic polishing was performed for 300 s, but stirring was performed for 180 s and then stirring was not performed for 120 s, and FIG. 30 (d) was stirred for 300 s of electropolishing time. Fig. 30(e) shows the rate of electrolyte agitation.

As can be seen from (a) to (d) of FIG. 30, it was confirmed that in the electropolishing process, when stirring of the electrolyte is performed, copper film removal outside the trench is more easily performed.

Referring to FIGS. 31 and 32, a plurality of semiconductor devices according to Example 1 in which the time during which the electrolyte is agitated in the copper film removal process is controlled, but the electrolytic polishing process for removing the copper films for each The changes in the current (Current) and the charge (Charge) with time were measured. Specifically, if electropolishing was performed for 300 s, but stirring (400 rpm) was performed for 240 s and then stirring was not performed for 60 s (a in FIGS. 31 and 32 ), electropolishing was performed for 300 s, but stirring (400 rpm) was 180 s. After the agitation was not performed for 120 s (b in FIGS. 31 and 32), the agitation was not performed during the electrolytic polishing time of 300 s (c in FIGS. 31 and 32), respectively, Changes and changes in charge were measured. FIG. 31 was measured based on the condition of 1.3 V, and FIG. 32 was measured based on the condition of 3.6 C/cm ² .

As can be seen in FIGS. 31 and 32, when stirring was not performed during the electropolishing time, 600 s was required to remove the copper film, but when stirring was performed, it was confirmed that 300 s was required.

33 and 34, after manufacturing the semiconductor device according to the method of manufacturing the semiconductor device according to Example 1 and Example 2, each of them is shown by SEM photographing. In the semiconductor device of the photographs taken in FIGS. 33 and 34, electrolytic polishing for removing the copper film was performed in an electrolyte containing 85 wt% of H ₃ PO ₄ .

Specifically, FIG. 33(a) is a photograph showing a semiconductor device according to Example 1 manufactured by applying a voltage of 2.3V for 300s, and FIG. 33(b) shows a voltage of 2.3V for 240s After a voltage of 1.3V was applied for 60s, the semiconductor device according to Example 2 was photographed, and FIG. 33(c) shows that the voltage of 1.3V is 120s after the voltage of 2.3V is applied for 180s. This is a photograph showing a semiconductor device according to Example 2, which has been manufactured during the application.

In addition, FIG. 34(a) is a photograph showing a semiconductor device according to Example 1 manufactured by applying a voltage of 2.3V for 300s, and FIG. 34(b) shows a voltage of 2.3V applied for 240s. After photographing a semiconductor device according to Example 2 manufactured by applying a voltage of 1.3V for 60s, FIG. 34(d) shows that a voltage of 1.3V is applied for 120s after a voltage of 2.3V is applied for 180s. It is a photograph showing a semiconductor device according to Example 2 manufactured by being applied, and FIG. 34(e) is a photograph showing a semiconductor device according to Example 1 manufactured by applying a voltage of 1.3V for 300s.

As can be seen from FIGS. 33 and 34, it was confirmed that the semiconductor device according to Example 2 was easily removed from the copper film other than the trench. In addition, the semiconductor device according to the second embodiment, it can be seen that compared to the semiconductor device according to the first embodiment, the copper film removal efficiency out of the trench was improved.

Referring to FIG. 35, a plurality of semiconductor devices according to Example 2 in which the time during which the electrolyte is agitated in the copper film removal process is controlled, but for each time in the electrolytic polishing process for removing the copper film The changes in the current (Current) and the charge (Charge) were measured. Specifically, after performing electrolytic etching for a period of 240 s with a voltage of 2.3 V, and performing electrolytic etching for a period of 60 s with a voltage of 1.3 V (a in FIG. 35 ), electrolysis for a period of 180 s with a voltage of 2.3 V After performing etching, electrolytic etching was performed for 120 s for a voltage of 1.3 V (b in FIG. 35 ), and when stirring (400 rpm) was performed for 300 s for a voltage of 2.3 V (c in FIG. 35 c) ) For each, changes in current and changes in charge over time were measured. The change in charge was measured based on the condition of 3.6 C/cm ² .

Referring to FIG. 36, a plurality of semiconductor devices according to Example 1 in which the electrolyte was stirred and the concentration of phosphoric acid was controlled during the copper film removal process were prepared, and SEM images were taken for each. Specifically, FIG. 36 (a) shows a semiconductor device prepared under the conditions of 85 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , 400 rpm stirring, and FIG. 36 (b) shows 70 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , shows a semiconductor device prepared under conditions of 400 rpm stirring, and FIG. 36(c) shows 50 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , conditions of stirring at 400 rpm. The semiconductor device manufactured in Figure 36 (d) is 85 wt% H ₃ PO ₄ electrolyte, 4.5 C / cm ² , shows the semiconductor device manufactured under the conditions of agitation (without agitation), Figure 36 ( e) represents a 70 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , a semiconductor device manufactured under conditions of agitation, and FIG. 37(f) shows 50 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , a semiconductor device manufactured under conditions of agitation (without agitation).

As can be seen from (a) to (f) of FIG. 36, when the copper film was removed while the electrolyte was agitated as compared to the case where the electrolyte was not stirred, it was confirmed that the copper film removal efficiency was higher. In addition, it was confirmed that the lower the concentration of H ₃ PO _4, the higher the removal efficiency of the copper film.

Referring to FIG. 37, a plurality of semiconductor devices according to Example 1 in which the electrolyte is stirred and the concentration of phosphoric acid is controlled during the copper film removal process, but electrolytic polishing for copper film removal for each In the process, changes in charge over time were measured. Specifically, when it is stirred with H ₃ PO _4, and 400rpm for 50 wt%, in the case 50 is not wt% of H ₃ PO ₄ and stirring, if a stirred with H ₃ PO _4, and 400rpm for 70 wt%, 70 wt% of H ₃ PO _4, and if they are not stirred, if it is stirred with H ₃ PO _4, and 400rpm for 85 wt%, when 85 wt% of H ₃ PO ₄ and a non-stirring measuring a change in electric charge with time, for each Did. 38 was measured based on the condition of 3.6 C/cm ² .

As can be seen in Figure 37, it was confirmed that the highest copper film removal efficiency when stirred at 50 wt% of H ₃ PO ₄ and 400 rpm. On the other hand, when 85 wt% of H ₃ PO ₄ and not stirred, it was confirmed that the copper film removal efficiency was the lowest.

Referring to FIG. 38, a plurality of semiconductor devices according to Example 1 are manufactured in which the electrolyte is stirred and the concentration of phosphoric acid is controlled during the copper film removal process, and atomic force microscopy (AFM) is photographed for each. It was shown by.

Specifically, Figure 38 (a) shows a semiconductor device prepared under the conditions of 85 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , 400 rpm stirring, Figure 38 (b) is 70 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , shows a semiconductor device prepared under the conditions of 400 rpm stirring, and FIG. 38(c) shows 50 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , 400 rpm stirring conditions A semiconductor device manufactured in FIG. 38(d) shows a semiconductor device manufactured under the condition of 85 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , without agitation, and FIG. 38 ( e) represents a 70 wt% H ₃ PO ₄ electrolyte, 4.5 C/cm ² , a semiconductor device manufactured under conditions of agitation, and FIG. 38(f) shows 50 wt% H ₃ PO ₄ electrolyte, It shows a semiconductor device manufactured under the condition of 4.5 C/cm ² and without agitation.

As can be seen from (a) to (f) of FIG. 38, when the copper film was removed while the electrolyte was agitated compared to the case where the electrolyte was not stirred, it was confirmed that the copper film removal efficiency was higher. In addition, it was confirmed that the lower the concentration of H ₃ PO _4, the higher the removal efficiency of the copper film.

Referring to FIG. 39, a semiconductor device was manufactured according to the manufacturing process of the semiconductor device according to Example 2, but was manufactured according to the following specific conditions. The copper film deposition process was performed at -30 mA/cm ² current, 9 C/cm ² condition, and the copper film removal process was 70 wt% H ₃ PO ₄ electrolyte, 1.3V potential, 6.5C/cm Stirring at ² and 400 rpm was performed under conditions of primary removal, 1.0 C/cm ² and secondary removal where stirring was not performed.

Referring to FIG. 40, a semiconductor device was manufactured according to the manufacturing process of the semiconductor device according to Example 2, but was manufactured according to the following specific conditions. The copper film deposition process was performed at -30 mA/cm ² current, 9 C/cm ² condition, and the copper film removal process was 70 wt% H ₃ PO ₄ electrolyte, 1.3V potential, 6.5C/cm Agitation at ² and 400 rpm was performed under conditions of primary removal, 0.5 C/cm ² and secondary removal without stirring.

As can be seen in FIGS. 39 and 40, it was confirmed that despite the change in the secondary removal condition, the copper film other than the trench was easily removed. In addition, it was confirmed that the copper film was easily filled in trenches having line widths and line spaces of various sizes.

41 is a graph showing the degree of ionization of copper according to a voltage applied in the electropolishing process for removing a copper film, and FIG. 42 is a photograph showing semiconductor elements photographed in each section shown in FIG. 41.

Referring to FIG. 41, a semiconductor device is prepared according to the method of manufacturing a semiconductor device according to Example 1, but a potential (Potential V vs. Ag/AgCl) applied in an electropolishing process for removing a copper film is controlled, Accordingly, the current density (Current density, mA/cm ² ) was measured and shown.

Referring to FIG. 42, the semiconductor device described in FIG. 41 is photographed by SEM. Specifically, FIG. 41(a) shows the state before electropolishing is performed, and FIG. 41(b) shows the state where 0.25V is applied, and FIG. 41(c) shows 0.375V. The applied state is photographed and shown, and FIG. 41(d) is shown by photographing a state in which 0.5V is applied, and FIG. 41(e) is shown by photographing a state in which 1.3V is applied.

As can be seen from FIGS. 41 and 42, it was confirmed that in the section of 0V to 0.5V and the section of 1.6V to 2.5V, the slope of the current density increased as the applied voltage increased. On the other hand, in the section of more than 0.5 V and less than 1.5 V, it was confirmed that the slope of the current density decreased slightly with increasing voltage applied.

In addition, it was confirmed that the copper film was not removed in the section of more than 0 V and 0.5 V or less, and the copper film was removed in the section of 0.375 V or more. In addition, in the section of 1.6V or more and 2.5V or less, compared with the section of 0.5 V or more and less than 1.5 V, it was confirmed that the slope of the measured current density was remarkably high, so that the etching rate was remarkably fast, and 0.5 V Although the etching rate was relatively low in the section of more than 1.5V, it was confirmed that the surface condition of the etched copper film was best.

As a result, in the electrolytic polishing process for removing the copper film, the copper film is removed at a high speed by applying the first voltage at a relatively high level, and then the second voltage at the relatively low level is applied to improve the etching uniformity of the copper film. It can be seen that it is a method capable of efficiently performing the planarization process.

43 and 44 are photographs comparing the effect of the amount of charge applied in the electropolishing process for the removal of the copper film, and FIG. 45 is the thickness change of the copper film according to the amount of charge applied in the electropolishing process for the removal of the copper film It is a graph showing.

43 and referring to Figure 44, is the size of the charge 0C / cm ^2, which in a copper film removal process ^{0.5 C / cm 2, 1.5 C} / cm 2, and 2.5 C / cm ² the embodiment of the controlled Multi with After manufacturing the semiconductor device according to Example 1, each was shown by SEM photographing. FIG. 43 shows a top image and FIG. 44 shows a vertical image.

Referring to Figure 45, after controlling the size of the charge applied in the process of removing the copper film, in the semiconductor device according to Example 1 manufactured according to the size of each C / cm ² , the thickness of the copper film other than the trench (Thickness, um ) The change was measured.

As can be seen in FIGS. 43 to 45, it was confirmed that the removal of the copper film was easily generated as the size of the electric charge (or the size of the voltage) applied during the copper film removal process increased.

As described above, the present application has been described in detail using a preferred embodiment, but the scope of the present application is not limited to a specific embodiment, and should be interpreted by the appended claims. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present application.

The method for manufacturing a semiconductor device according to an embodiment of the present invention may be applied to various components of a semiconductor device such as metal wiring and TSV.

Claims

Preparing a base substrate structure having a recess area;

Depositing a material film on the base substrate structure having the recess region to fill the recess region; And

A method of manufacturing a semiconductor device comprising ionizing a material of the material film, removing the material film outside the recess area, and remaining the material film in the recess area to form a material film pattern in the recess area. .
According to claim 1,

The step of ionizing the material of the material film,

Immersing the base substrate structure having the material film in an electrolyte;

A first removing step of applying a first voltage to the material film; And

And a second removing step of applying a second voltage having a level lower than the first voltage to the material film.
According to claim 2,

A method of manufacturing a semiconductor device comprising applying the second voltage immediately after the first voltage is applied (directly after).
According to claim 2,

A method of manufacturing a semiconductor device, wherein a rate at which the material of the material film is ionized in the first removal step is faster than a rate at which the material of the material film is ionized in the second removal step.
According to claim 2,

The second voltage is a method of manufacturing a semiconductor device comprising more than 0.5V less than 1.6V.
According to claim 2,

The electrolyte comprises phosphoric acid (H 3 PO 4 ), the concentration of the phosphoric acid is 50 wt% or more of the semiconductor device manufacturing method.
According to claim 2,

As the concentration of the phosphoric acid is lowered, the method of manufacturing a semiconductor device comprising a faster ionization rate of the material.
According to claim 2,

Before depositing the material film,

On the base substrate structure, along the inner surface of the recess region, further comprising the step of forming a barrier layer,

The electrolyte is a method of manufacturing a semiconductor device including a barrier etchant for etching the barrier layer.
The method of claim 8,

The barrier layer is one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tantalum nitride (TaN), and silicon tantalum nitride (TaSiN) A method for manufacturing a semiconductor device including any one.
According to claim 2,

A method of manufacturing a semiconductor device including the first and second voltages being applied to the material layer while the electrolyte is stirred.
According to claim 1,

The recess region is a trench, and the material layer pattern is a metal wiring.
According to claim 1,

The recess region is a via-hole passing through the base substrate, and the material layer pattern is a through silicon via (TSV) manufacturing method.
According to claim 1,

The material film is a method of manufacturing a semiconductor device including a copper film.
Preparing a base substrate;

Depositing a material film on the base substrate;

Immersing the base substrate on which the material film is deposited in an electrolyte; And

And sequentially applying a first voltage to the material film and a second voltage at a level lower than the first voltage to ionize the material of the material film to remove at least a portion of the material film. Device manufacturing method.
The method of claim 14,

In a first voltage section, a first section in which the removal rate of the material film decreases to a first slope according to an increase in voltage, and a second section in which a removal rate of the material film increases in a second slope according to an increase in voltage in the second voltage section. Is provided,

The size of the second slope of the second section is greater than the size of the first slope of the first section,

The first voltage is selected in the second voltage section, the second voltage is a method of manufacturing a semiconductor device comprising the first voltage section.