CN110620117A - 使用晶片到晶片接合的具有共享控制电路的三维(3d)闪存存储器 - Google Patents
使用晶片到晶片接合的具有共享控制电路的三维(3d)闪存存储器 Download PDFInfo
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- CN110620117A CN110620117A CN201910410297.1A CN201910410297A CN110620117A CN 110620117 A CN110620117 A CN 110620117A CN 201910410297 A CN201910410297 A CN 201910410297A CN 110620117 A CN110620117 A CN 110620117A
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Abstract
本文公开了使用晶片到晶片接合的具有共享CMOS电路的三维(3D)闪存存储器。晶片到晶片接合用于形成三维(3D)存储器部件,例如在一个管芯上具有共享控制电路以访问多个管芯上的阵列的3D NAND闪存存储器。在一个示例中,非易失性存储装置包括第一管芯,该第一管芯包括非易失性存储单元的3D阵列和CMOS(互补金属氧化物半导体)电路。第二管芯与第一管芯垂直堆叠并接合,该第二管芯包括非易失性存储单元的第二3D阵列。第一管芯的CMOS电路的至少一部分用于访问第一管芯的非易失性存储单元的第一3D阵列和第二管芯的非易失性存储单元的第二3D阵列。
Description
技术领域
本描述总体上涉及三维(3D)存储器和存储装置,并且更具体而言,本描述涉及形成使用晶片到晶片接合的具有共享CMOS电路的3D闪存存储器。
背景技术
诸如NAND闪存存储器的闪存储存器是非易失性存储介质。非易失性储存器是指即使装置的电力中断也具有确定的状态的储存器。闪存存储器可以用作存储器(例如,系统存储器)或用作存储装置。跨移动端、客户端和企业部门的系统存在使用闪存存储器进行存储的趋势(例如,诸如固态驱动器(SSD))。一种类型的NAND闪存存储器是三维(3D)NAND闪存存储器,其中垂直NAND串组成存储阵列。尽管3D NAND闪存阵列在给定区域中可以存储比二维(2D)NAND更多的位,但是一直以为都存在对更密集、更快速且更节能的数据储存器的兴趣。
附图说明
以下描述包括对具有本发明的实施例的实施方式的通过示例的方式给出的例示的附图的讨论。应当通过示例的方式而不是限制的方式来理解附图。如本文所使用的,对一个或多个“实施例”或“示例”的引用应当被理解为描述包括在本发明的至少一个实施方式中的特定特征、结构和/或特性。因此,本文中出现的诸如“在一个实施例中”或“在一个示例中”的短语描述了本发明的各种实施例和实施方式,并且不一定都指代相同的实施例。然而,它们也不一定是互相排斥的。
图1A示出了使用晶片接合形成的具有共享CMOS电路的3D闪存存储部件的示例的截面。
图1B示出了使用晶片接合形成的具有共享CMOS电路的3D闪存存储部件的示例的截面。
图2A示出了具有衬底到衬底接合的两个晶片的3D闪存存储部件的示例的截面。
图2B示出了具有顶部金属到顶部金属接合的两个晶片的3D闪存存储部件的示例的截面。
图3A示出了用于在封装中堆叠接合的3D闪存存储管芯的技术的示例。
图3B示出了用于在封装中堆叠接合的3D闪存存储管芯的技术的示例。
图4A示出了芯片平面图的俯视视图,该平面图示出了用于访问3D闪存存储阵列的CMOS电路。
图4B示出了芯片平面图的俯视视图,该平面图示出了用于使用晶片到晶片接合来访问3D闪存存储阵列的共享CMOS电路。
图5是形成具有共享CMOS电路和经由晶片到晶片接合而接合在一起的多个管芯的3D闪存存储部件的方法的示例的流程图。
图6A、6B、6C和6D示出了在各种处理阶段中的具有共享CMOS电路的3D闪存部件的示例。
图7示出了其中可以实施晶片接合和共享CMOS电路的闪存存储装置的方框图的示例。
图8提供了其中可以实施晶片接合和共享CMOS电路的计算系统的示例性描述。
以下对某些细节和实施方式的描述,包括对可以描绘下述的一些或全部实施例的附图的描述,以及讨论本文提出的发明构思的其它可能的实施例或实施方式。
具体实施方式
本文描述了用于形成使用晶片到晶片接合的具有共享控制电路的三维(3D)存储器部件的技术。
一种类型的3D存储器是3D闪存存储器,其也可以被称为3D闪存储存器。3D闪存存储器的一个示例是3D NAND(非AND)闪存存储器。3D存储器包括存储单元的一个或多个阵列和用于访问存储单元的控制电路。典型地,用于访问3D闪存存储阵列的控制电路包括CMOS(互补金属氧化物半导体)电路。控制或CMOS电路也可以被称为“外围”。典型的3D闪存存储器装置包括一个或多个阵列和用于控制每个阵列的独立CMOS电路。CMOS电路通常被认为是开销,其减小了可用于存储单元的面积。
与常规3D闪存存储器相反,本文描述的3D闪存存储部件包括共享CMOS电路。共享CMOS电路控制或使得能够访问多个管芯上的存储器阵列。在一个示例中,多个晶片被单独处理。晶片中的至少一个包括共享CMOS电路。晶片被垂直堆叠并接合在一起。互连将共享CMOS电路与两个或更多个晶片上的阵列耦合。堆叠体中的仅一个晶片或堆叠体中的多个晶片可以包括用于访问多个晶片上的阵列的共享CMOS电路。在一个示例中,多个晶片均包括共享CMOS电路。在两个晶片均包括共享CMOS电路的一个示例中,字符串驱动器电路的一部分(例如,一半)位于一个晶片的CMOS电路中,并且字符串驱动器电路的剩余部分位于另一个晶片的CMOS电路中。在一个这样的示例中,位于两个管芯上的字符串驱动器电路用于访问两个管芯上的阵列。其它类型的CMOS电路可以分开并在多个晶片之间共享,或者被共享并且仅位于所述晶片之一上。
因此,晶片到晶片接合用于将两个或更多个管芯的外围区域连接在一起,以使得相同的外围面积和功率可以在多于一个管芯上被分摊。在多个管芯上共享相同的外围电路产生减小的管芯面积和减小的功率。这意味着每千兆字节(GB)的更低成本和针对相同性能的更低功率。
图1A示出了使用晶片接合形成的具有共享CMOS电路的3D闪存存储部件的示例的截面。图1A中的部件包括接合在一起的两个管芯200A和200B。将两个管芯200A和200B接合在一起可以通过将包括管芯的晶片接合在一起并且然后切割晶片来实现。两个管芯200A和200B中的每一个包括闪存存储阵列和用于控制和访问阵列的CMOS电路。
参考管芯200B,存储阵列包括存储单元(例如,在柱256B处形成的存储单元)和导电访问线路,该导电访问线路使得能够访问存储单元(例如,位线264B(其从图1A中的页面向外)、字线220B、SGS(选择栅极源极)252B、SGD(选择栅极漏极)260B)。在例示的示例中,源极板250B位于柱256B和导电互连226B之间。在CMOS电路和阵列之间,每个管芯包括导电互连以将阵列与CMOS电路耦合。例如,参考管芯200B,互连226B将CMOS电路201B与阵列203B耦合。在例示的示例中,多(多晶硅)层236B在导电互连226B和CMOS电路之间。附加导电层(例如,212B、218B和过孔202B、204B、206B、208B、224B、262B和266B)使得能够将阵列耦合到CMOS电路或将CMOS电路耦合到存储部件外部的其它电路。在例示的示例中,过孔以交错或阶梯状配置与字线220B耦合。管芯200A还包括阵列203A和互连226A,其可以与管芯200B的那些相同或相似。在图1A所示的示例中,管芯200A的特征相对于管芯200B被翻转或成镜像。
在图1A所示的示例中,阵列203A和203B是3D闪存阵列。阵列203A和203B可以使用三维(3D)电路构建,使得存储器单元构建在衬底的顶部上。这种3D电路技术可以使用衬底作为存储器阵列的机械基底,而不将衬底本身用于存储器阵列的电路。在其它示例中,阵列的部分可以形成在衬底中。阵列可以包括任何类型的3D存储器,例如浮置栅极闪存存储器、电荷捕获(例如,替换栅极)闪存存储器、相变存储器、电阻式存储器、奥氏存储器、铁电晶体管随机存取存储器(FeTRAM)、纳米线存储器或任何其它3D存储器。在一个示例中,3D闪存阵列是堆叠的NAND闪存阵列,其在以NAND(非AND)方式布线的垂直堆叠体中堆叠多个浮置栅极或电荷捕获闪存存储器单元。在另一个示例中,3D闪存阵列包括NOR(非OR)存储单元。
在图1A所示的示例中,阵列203A和203B包括形成存储单元的柱,诸如NAND闪存存储单元。图1A示出了每个管芯上的两个叠层,其中每个叠层包括多个层级(层)。然而,其它示例可以包括具有一个叠层或超过两个叠层的阵列。在存储单元包括浮置栅极晶体管的示例中,可以通过对存储单元的浮置栅极充电来对单元进行编程。浮置栅极典型地包括导电或半导体材料。在存储单元包括电荷捕获的示例中,可以通过将电荷存储在电荷捕获中来对存储单元进行编程。电荷捕获典型地包括绝缘材料(例如氮化硅或能够存储电荷的另一种绝缘材料)。也可以使用用于实现存储数据的其它存储单元技术。
阵列203B之下的是控制电路201B。在一个示例中,控制电路201B包括CMOS电路(并且因此被称为“阵列之下的CMOS”或CuA)。在一个这样的示例中,首先在衬底240B中形成CMOS电路,接着在CMOS电路201B之上形成导电互连,并且然后在互连226B和CMOS电路201B的顶部上构建阵列203B。还可以在存储阵列旁边形成CMOS电路。在一个这样的示例中,衬底的部分用于构建阵列,并且衬底的另一部分用于构建与阵列相邻的CMOS电路,并且在CMOS电路和阵列之间存在互连。在阵列之下而不是在阵列旁边形成CMOS电路的一个优点是总芯片面积减小。在另一个示例中,CMOS电路可以部分地位于阵列之下并且部分地位于阵列旁边。无论控制电路是在阵列之下还是在阵列旁边,控制电路都可以被称为“外围”。
控制电路201A和201B包括用于控制对阵列203A和203B的访问的电路。控制电路201A和201B包括以下中的一个或多个:地址解码器、线路驱动器、感测放大器、电荷泵、状态机、缓冲器或各种其它类型的电路。控制电路201A和201B典型地包括晶体管。在一个示例中,控制电路201A和201B包括n沟道金属氧化物半导体场效应晶体管(MOSFET)、p沟道MOSFET或两者。控制电路201A和201B还可以分别包括多路由248A和248B。控制电路201A和201B使用过孔与访问线路耦合,以允许控制电路201A和201B与访问线路之间的电通信,从而实现对存储单元的访问。导电访问线路、导电互连和过孔由导电(例如,金属)或半导电材料形成,以实现部件之间的电耦合。
图1A中的3D闪存存储部件包括在管芯200B之下并与管芯200B接合的第二管芯200A。因此,与包括单个管芯的常规3D闪存存储部件不同,多个管芯(每个具有多个层或层级)被堆叠并接合在一起。管芯200A和200B通过晶片到晶片接合工艺接合在一起。在图1A所示的示例中,在接合之前,翻转晶片中的一个,使得管芯200A的CMOS电路201A面向管芯200B的CMOS电路201B。需注意,即使CMOS电路201A看起来如图1A所示在阵列的“之上”,晶片200A仍然可以被认为是阵列之下的CMOS(CuA)实施方式,因为在晶片被翻转之前,阵列形成在CMOS电路之上。通过晶片到晶片接合工艺,管芯200B的CMOS电路201B和管芯200A的CMOS电路201A电耦合在一起。在例示的示例中,晶片接合焊盘242被包括在两个管芯200A和200B之间。在图1A所示的示例中,晶片接合焊盘施加到每个晶片(例如,接合焊盘施加到包括管芯200A的晶片和包括管芯200B的晶片),并且晶片在晶片接合焊盘242处接合在一起。在一个这样的示例中,晶片之间的任何空间(例如,x方向上的接合焊盘之间和y方向上的晶片之间的空间)可以是空气或填充有诸如绝缘体的填充物材料,以提供结构支持。
尽管例示的示例包括管芯200A和200B之间的接合焊盘242,但是接合焊盘可以或可以不用于接合晶片。在没有接合焊盘的示例中,在一个晶片的底部暴露的任何导电表面可以被接合到在另一个晶片的顶部暴露的导电表面。例如,每个晶片的暴露的导电互连表面(例如,表面251A和251B)可以接合在一起。因此,在没有居间接合焊盘的情况下,接合可以包括“过孔到过孔”或“金属到金属”接合。管芯的非常好的对准(例如,导电互连表面251A与表面251B的对准)能够实现在没有接合焊盘的情况下接合晶片。在具有接合焊盘的示例中,与传统接合焊盘相比更小(例如,在x和z方向上更小)的接合焊盘能够实现耦合管芯200A和200B中的每个的CMOS电路。用于晶片到晶片接合的接合焊盘比标准接合焊盘小,因为有许多信号要接合。更小的焊盘是有挑战性的,因为对准要求很严格。在一个示例中,接合焊盘具有的尺寸大约为接触部尺寸。在一个这样的示例中,与具有10微米或更大的宽度的常规接合焊盘相比,接合焊盘242具有0.5微米或更小的宽度。
将管芯堆叠并接合在一起可以以各种方式实现控制电路的共享,以减小控制电路占用的面积,提高性能和/或降低功耗。由于通过接合的接触部(在例示示例中通过接合焊盘242)进行电连接,顶部和底部晶片的外围区域可以共享,并且重复的电路被移除。移除重复电路有助于将外围电路装配在阵列之下并降低CMOS电路消耗的功率。一个或多于一个管芯可以包括控制电路。在图1A所示的示例中,阵列200A和200B都包括控制电路。在两个管芯都包括控制电路的情况下,至少一个管芯包括共享电路;然而,多个(最多全部)管芯可以包括共享电路。共享电路可以涉及跨管芯将电路分开(例如,包括一个管芯上的字符串驱动器的一半、以及另一管芯上的字符串驱动器的一半)或在管芯之一上形成一种类型的控制电路并且在另一管芯上形成不同类型的控制电路(例如,管芯之一上的字符串驱动器和另一个管芯上的页面缓冲器,或控制电路的任何其它划分)。在一个示例中,顶部管芯200B包括电荷泵、静态页面缓冲器、字符串驱动器的一半和IO。底部管芯200A包括控制逻辑、静态页面缓冲器、字符串驱动器的一半和焊盘。通过接合焊盘的电连接使得两个管芯都能够访问两个晶片上的CMOS。
在一个示例中,将不同类别的晶体管(例如,高电压(HV)晶体管或低电压(LV)晶体管)放置在两个不同的晶片上。在不同晶片上形成不同类别的晶体管可以通过在晶片的仅其中之一(或少于全部)上形成更昂贵类别的晶体管(例如,HV晶体管)来降低成本。在一个示例中,电荷泵、字符串驱动器和电压调节器使用具有厚栅极氧化物的高电压晶体管。逻辑电路、数据路径电路和静态页面缓冲器使用具有薄栅极氧化物的高速、低电压器件。因此,在一个示例中,一个晶片上的CMOS电路包括电荷泵、字符串驱动器和电压调节器中的一个或多个,并且不包括使用低电压器件的电路(例如,逻辑电路、数据路径电路和静态页面缓冲器)。在该示例中,另一晶片上的CMOS电路将包括使用低电压器件的电路(例如,逻辑电路、数据路径电路和静态页面缓冲器中的一个或多个),并且不包括使用高电压器件的电路(例如,电荷泵、字符串驱动器和电压调节器)。
在另一个示例(未示出)中,一个管芯由阵列加CMOS组成,而第二管芯仅包含阵列。这降低了第二晶片的处理成本和每千兆字节(GB)的总成本,尽管它伴随着性能下降。
图1B示出了使用晶片接合形成的具有共享CMOS电路的3D闪存存储部件的另一示例的截面。图1B中的3D闪存存储部件类似于图1A中的部件,除了图1B中的管芯在不翻转管芯的其中之一的情况下被堆叠并接合。因此,管芯200C和200D具有相同的取向。由于管芯的取向和接合位置,管芯200C的CMOS电路201C和管芯200D的CMOS电路201D彼此不相邻。因此,为了在两个管芯之间共享CMOS电路,使用过孔来电耦合管芯的CMOS电路。在图1B所示的示例中,没有直接连接CMOS电路的单个过孔。晶片与过孔227D接合,但是必须经过若干金属和过孔层(例如,导电互连218C)。
而且,与图1A中所示的示例相反,图1B示出了没有接合焊盘的示例。因此,管芯200C和管芯200D在过孔227D的暴露的底表面和位线264C的暴露的上表面处接合在一起。接合点之间的区域可以是空气或可以被填充有绝缘材料。在例示的示例中,可以消除金属层中的一些和钝化层。例如,管芯200C在位线264C之上不包括附加的金属层和钝化层(诸如图1A的导电互连212B和钝化层210B)。与常规3D NAND装置不同,阵列203D顶部的金属212D也可以用于访问管芯200C上的电路(除了用于管芯200D之外),并且因此可以消除用于管芯200C的附加金属层。因此,尽管例示的示例可以通过消除一个或多个层来降低成本,但是与管芯的其中之一相对于另一个管芯被翻转的情况相比,两个管芯的CMOS电路之间的连接更长。
与图1A类似,图1B中的部件包括共享CMOS电路。CMOS电路201C、201D或两者可以包括用于访问第一管芯200C上的阵列203C和管芯200D上的阵列203D的共享电路。因此,图1A和图1B示出了使用晶片接合以在两个或更多个管芯之间共享外围电路的两个不同示例。如前所述,晶片到晶片接合的使用不限于两个管芯。通过制造横贯减薄的管芯的过孔,可以通过多个管芯的堆叠体进行连接。这使得外围能够在多个管芯上共享,这可以用于进一步减小管芯面积和功耗。这种方法的额外的好处是,由于管芯之间的连接已经存在,可以降低封装成本。在两个或多个独立管芯之间共享外围电路可以使得能够在受CuA约束的设计中减小管芯尺寸并且增加(例如,加倍)每个管芯中的平面的数量。3D NAND存储器中的存储器单元被分组为平面(例如,其中平面典型地包括16k字节,但是尺寸可以更小或更大)。平面中的所有位都是并行读取或写入的。用户可以并行读取或写入多个平面,因此具有更多平面为用户提供更好的性能。共享外围还可以实现功率/性能改进。例如,如果平面的数量增加,则吞吐量/功率更高,因为外围功耗在更大数量的平面上分摊。即使在管芯不一定受CuA限制的情况下,晶片到晶片接合和共享CMOS电路也可以实现其它优化,例如减少管芯占用面积。例如,如果管芯太大而不能装配到封装中,则可以将该管芯划分成两个管芯,然后将两个管芯接合在一起(例如,下面参考图4B所讨论的)。
图2A和图2B还示出了3D闪存存储部件的示例的横截面。图2A示出了具有衬底到衬底接合的两个晶片的3D闪存存储部件,并且图2B示出了具有顶部金属到顶部金属接合的两个晶片的3D闪存存储部件。因此,图2A中的部件与图1A中所示的部件相似,其相似之处在于晶片之一被翻转,使得晶片的CMOS电路面向彼此。
与图1A和图1B类似,图2A和图2B中的3D闪存存储部件均包括经由晶片接合而接合在一起的两个管芯,每个管芯包括存储阵列和CMOS电路。例如,图1A示出了管芯280A和280B。参考管芯280A,CMOS电路282A位于阵列281A之下,并且存在将阵列281A与CMOS电路282A耦合的导电互连284A。CMOS电路282A可以与相对于图1A和图1B所描述的CMOS电路相同或相似。类似地,管芯280B包括在阵列281B“之下”并与导电互连284B耦合的CMOS电路282B。
在图2A所示的示例中,跨管芯280A和280B的CMOS电路282A和282B包括共享字符串驱动器288A和288B。字符串驱动器包括用于驱动阵列281A和281B的字线的晶体管。常规3D闪存存储部件将包括专用于仅驱动该管芯上的阵列的字符串驱动器电路。相反,在图2A所示的示例中,字符串驱动器的一半在一个管芯上,并且字符串驱动器的另一半在另一个管芯上,其中两个管芯上的字符串驱动器驱动两个管芯上的阵列。例如,用于驱动奇数字线的字符串驱动器可以在顶部管芯280A上,并且用于驱动偶数字线的字符串驱动器可以在底部管芯280B上(或反之亦然)。因此,使用两个管芯上的字符串驱动器来实现驱动管芯之一的阵列中的奇数和偶数字线。因此,用于驱动管芯280A上的字线和管芯280B上的字线的字符串驱动器位于两个管芯上。相反,常规3D闪存部件利用字符串驱动器在与被驱动的阵列和字线相同的管芯上驱动偶数和奇数字线。因此,对于两个阵列,与图2A的示例相比,常规部件将包括两倍的字符串驱动器。
在图2A所示的示例中,部件包括穿过CMOS电路和衬底的过孔286A和286B,以将CMOS电路282A与CMOS电路282B耦合。典型地,过孔不是穿过CMOS形成的,而是形成在CMOS上方以将CMOS耦合到阵列(对于CuA)。穿过CMOS形成过孔带来了潜在的挑战。例如,衬底和过孔之间的不同电压可能导致从字符串驱动器到衬底的寄生电流路径。为了防止潜在的泄漏,可以向CMOS中的过孔中添加绝缘衬垫。另外,因为每个字符串驱动器正在驱动更高的电容(例如,与常规字符串驱动器相比,使电容加倍),所以与常规字符串驱动器相比,图2A的字符串驱动器包括更大的晶体管。而且,相对于常规3D闪存存储部件,图2A中所示的示例实现了改进的路由和增大的信号密度。例如,字符串驱动器中的路由得到改进,因为可以组合两个晶片中的所有金属线以用于字线的路由。
图2B也示出了两个接合在一起的晶片,但是晶片利用面向彼此的顶部金属层290C和290D接合。尽管图2B中示出了金属层290C和290D,但是可以消除金属层290C或290D中的一个。消除金属层中的一个可以降低成本(在材料和处理方面)。因为金属层290C和290D在阵列281C和281D之间以及CMOS电路282C和282D之间,所以图2B中的示例不包括穿过CMOS的过孔。因此,图2B中所示的部件不会面临上面相对于图2A所提及的关于由于穿过CMOS的过孔而引起的潜在电流泄漏的挑战。然而,缺少用于耦合每个管芯的CMOS电路的穿过部件中间的过孔会带来其它潜在的挑战。在阵列外部或穿过阵列的其它互连将CMOS电路282C与282D耦合。因此,CMOS不直接与过孔连接,而是通过两个管芯中的许多(最多全部)金属/过孔堆叠体。在该示例中,晶片到晶片接合仅将金属堆叠体的顶部连接在一起。
与图2A中所示的部件类似,尽管图2B未示出导电互连290C和290D之间的接合焊盘,但是可以包括与图1A的接合焊盘242相似或相同的接合焊盘。3D闪存存储部件也可以包括顶部和/或底部处的接合焊盘,以将部件与部件外部的电路(例如,在封装级)耦合。为了将导电互连290C和290D与顶部和/或底部处的接合焊盘耦合,可以存在穿过CMOS 282C和282D形成的过孔。然而,与图2A的过孔286A不同,将导电互连与上或下接合焊盘耦合的过孔将位于接合焊盘处(例如,在接合焊盘之下或上方)。
图3A和图3B示出了用于在封装中堆叠并连接接合的3D闪存存储管芯的不同技术的示例。图3A示出了交错的管芯,并且图3B示出了具有用于在封装级连接管芯的模拟过孔的垂直堆叠管芯的示例。图3A和图3B均示出了四个3D闪存存储管芯(或两个管芯对)。例如,图3A示出了管芯301、302、303和304。管芯301和302经由上述晶片接合技术接合在一起。管芯303和304也经由晶片接合而接合在一起。类似地,图3B的管芯351和352以及管芯353和354经由晶片接合技术接合在一起。在图3A和图3B所示的示例中,管芯在它们各自的CMOS电路面向彼此的情况下接合在一起,例如图1A和图2A中所示。因此,管芯301和302在那些接合的管芯上包括至少一些共享CMOS电路,并且管芯303和304包括至少一些共享CMOS电路。类似地,管芯351和352包括至少一些共享CMOS电路,并且管芯353和354包括至少一些共享CMOS电路。然后管芯对在封装中堆叠在彼此的顶部上(但不像管芯对中的管芯那样接合在一起)。在例示的示例中,包括管芯301和302的管芯对堆叠在包括管芯303和304的管芯对之上。类似地,包括管芯351和352的管芯对堆叠在包括管芯353和354的管芯对之上。
图3A示出了接合的管芯像屋顶板一样交错的示例。因此,接合的管芯中的每一对的表面的一部分(例如,管芯301的顶表面和管芯303的顶表面的一部分)被暴露,以使得能够在封装级将该对连接到外部电路或接触部。可以将接合焊盘(例如,引线接合焊盘,例如焊盘310A和310B)放置在所述表面的用于连接到外部电路或接触部的暴露部分上。然后可以将引线接合到接合焊盘310A和310B。因此,除了管芯301和302之间以及管芯303和304之间的接合焊盘(如果存在)之外,引线接合焊盘还能够在封装级访问每个管芯对。
图3B示出了接合并连接两个管芯对的另一个示例。与图3A的交错方法相反,图3B中的管芯直接堆叠在彼此之上。每个管芯对在其顶表面和底表面处包括接合焊盘。例如,管芯351和353在其顶表面上包括接合焊盘(分别为接合焊盘310C和310E),并且管芯352和354在其底表面上包括接合焊盘(分别为接合焊盘310D和310F)。然后,在晶片接合焊盘310D和310E处将管芯对接合在一起,以将管芯电耦合到外部电路或接触部。在图3B所示的示例中,引线不需要接合到每个管芯或管芯对,但是可以仅接合到一个接合焊盘(例如,顶部接合焊盘310C)以访问管芯中的每一个(例如,管芯351、352、353和354中的每一个)。因此,穿过CMOS的过孔、每个管芯的导电互连以及管芯对之间的接合焊盘310D和310E模拟从顶部管芯351延伸到底部管芯354的过孔。因此,可以实现过孔的效果,而无需蚀刻穿过整个管芯堆叠体以生成穿过整个堆叠体的单个过孔。尽管在每个堆叠体中仅示出了四个管芯(两个管芯对),但是可以使用所描述的技术堆叠更多管芯(例如,8个或更多个)。
图4A示出了芯片平面图的俯视视图,该平面图示出了用于访问3D闪存存储阵列的CMOS电路。图4A所示的芯片平面图示出了CMOS电路的一种可能布局,包括阵列外部的CMOS(COA)402A、阵列之下的CMOS(CUA)404A、静态页面缓冲器(SPB)406A和字符串驱动器(SD)408A。COA 402A位于阵列外部(即,不在阵列之下或上方),并且剩余CMOS电路在阵列之下(或上方)。CUA404A可以包括CMOS电路,例如控制逻辑、电荷泵和/或其它CMOS电路。数字0、1、2和3是表示不同平面的平面编号。
图4B示出了芯片平面图的俯视视图,该平面图示出了用于使用晶片到晶片接合来访问3D闪存存储阵列的共享CMOS电路。图4B中所示的芯片平面图示出了经由晶片到晶片接合而接合在一起的两个管芯401和403的平面图。与图4A中类似,数字0、1、2和3是表示不同平面的平面编号。在图4B所示的示例中,每个管芯401和403包括阵列外部的CMOS(COA)、阵列之下的CMOS(CUA)、静态页面缓冲器(SPB)和字符串驱动器(SD)。然而,如上所述,管芯可以包括不同类型的控制电路(例如在一个管芯上的使用一类晶体管的电路和在另一管芯上的使用另一类晶体管的电路)。在该示例中,管芯401将被堆叠在管芯403的顶部上并且被接合(在晶片级,在切割之前)。每个管芯在z方向上的长度410B是图4A的管芯400的长度410A的一半。因此,每个管芯401和403中可用于CMOS电路的面积是管芯400中的可用面积的一半。在例示的示例中,COA 402B的长度是COA402A的一半,并且每个管芯401和403中可用于CUA、SD和SPB的面积是相对于管芯400的可用面积的一半。然而,图2B中用于CMOS电路的总可用面积是相同的,假设存在两个堆叠的管芯401和403,使得堆叠的管芯的厚度为两倍(在y方向上,其将从图4A和4B中的页面中出来)。
堆叠并接合管芯以使得每个管芯的CMOS电路彼此相邻可以具有若干优点。如上所述,图4B中的堆叠管芯的尺寸是:长度为图4A中的管芯的一半,但厚度是图4A中的管芯的两倍。对于一些封装,可能期望的是在z-x平面中具有小占用面积。然而,与图4A的管芯相比,图4B中的更少的管芯对可以堆叠在给定封装中。图4B的堆叠接合管芯的一个好处是,管芯中的每者上的CMOS电路的“岛”可以彼此相邻放置,使得CMOS岛之间的通信能够更容易且更好。例如,参考图4A,CMOS电路跨z-x平面分布在小区域或岛中。将所有岛(例如,标记为CUA的所有岛)彼此路由并连接可能是困难的。例如,图4A中的CMOS的路由可以包含边缘上、阵列上方、阵列下方和/或穿过阵列的金属线。不仅路由困难,而且长信号线路减慢了CMOS电路的操作。
相反,连接堆叠在彼此上并经由晶片到晶片接合而接合的CMOS电路的岛更简单。例如,如果管芯401堆叠在管芯403的顶部上,则CUA 404C将在CUA 404D上方,形成面积大于图4A的CUA岛的CUA岛。因此,CUA 404C可以在没有过孔并且没有穿过或围绕其它电路的路由的情况下与CUA 404D电耦合。通过堆叠并接合管芯401和403,图4B中可用于给定岛的面积的尺寸是相对于图4A中的面积的两倍。
图5是形成具有共享CMOS电路和经由晶片到晶片接合而接合在一起的多个管芯的3D闪存存储装置的方法的示例的流程图。图5的方法500可以用于形成3D闪存存储部件,例如图1A、1B、2A或2B中所示的部件。
方法500开始于在操作502和504处在两个晶片上形成3D非易失性存储阵列。共享CMOS电路也形成在晶片中的至少一个中或上。形成阵列和CMOS电路包含多个处理步骤,包括各种材料的沉积、掺杂和蚀刻以形成阵列和控制电路。在形成第一和第二存储阵列和共享CMOS电路之后,在操作506处将晶片接合在一起。将晶片接合在一起包含晶片到晶片接合技术以将附接到晶片的接合焊盘接合在一起,或者在晶片的导电接触部处将晶片接合在一起。具有亚微米对准精度的晶片到晶片接合是可行的,并且可以包含以下工艺流程。首先清洁晶片并激活表面(通过表面处理)以增强接合。接下来使用面对面(F2F)精确光学对准来对准晶片,这实现了亚μm对准精度。一旦对准,晶片通过在常规清洁室环境中进行热压缩而接合。优化的工具和工艺顺序可以确保在整个晶片上维持亚μm对准精度。
图6A-6D示出了根据诸如图5的方法500的示例性方法的处理的各个阶段中的3D闪存存储部件的横截面。图6A示出了第一晶片601A的一部分和第二晶片601B的一部分。晶片601A和601B均分别包括衬底602A和602B。在图6A所示的示例中,CMOS电路604A和604B形成在晶片601A和601B两者的衬底中。然而,在其它示例中,晶片中的仅一个包括CMOS电路。CMOS电路604A和604B中的一个或两个可以包括共享CMOS电路。在CMOS电路之上,形成存储阵列606A和606B,并且在阵列之上形成金属层608A和608B,其可以将阵列与外部接触部和/或电路耦合。
图6B-6D示出了使用接合焊盘的示例。参考图6B,首先翻转晶片601A和601B,使得晶片的背面(例如,晶片的具有CMOS电路的一侧)面向上。然后,减薄晶片的背面以暴露CMOS电路604A和604B的导电接触部。在减薄晶片601A和601B的背面之后,晶片接合焊盘610附接到晶片的背面,如图6C所示。然后再次翻转晶片中的一个,使得附接到每个晶片的晶片接合焊盘610面向彼此,并且晶片在接合焊盘610处接合,如图6D所示。
在晶片接合之后,可以将晶片切割成个体管芯并与诸如闪存控制器的其它逻辑封装在一起,以形成3D闪存存储装置。通过在CMOS电路处接合晶片,可以共享一个或两个管芯上的CMOS电路以访问两个管芯上的阵列606A和606B。
图7示出了根据一个示例的闪存存储装置702的方框图,其中可以实施晶片接合和共享CMOS电路。虽然将术语闪存存储用于装置702并且贯穿本公开,但是闪存存储装置也可以被称为闪存存储器装置。在一个示例中,闪存存储装置702是固态驱动器(SSD),其包括闪存存储部件722。闪存存储部件722包括用于存储数据的非易失性存储阵列731。闪存存储部件722还包括CMOS电路733以访问存储阵列731。如上所述,闪存存储部件722可以包括接合在一起的多个管芯。每个管芯可以包括存储阵列,并且给定管芯上的共享CMOS电路使得能够访问多个管芯上的阵列。尽管图7中示出了单个闪存存储部件,但是闪存存储装置702可以包括一个以上的闪存存储部件。
在一个示例中,闪存存储装置702可以是使用PCI高速(PCIe)、串行高级技术附件(ATA)、并行ATA和/或通用串行总线(USB)接口连接到处理器的基于闪存的驱动器。存储阵列731可以包括NAND闪存、NOR闪存、相变存储器(PCM)、具有开关的相变存储器(PCMS)、电阻式存储器或其它非易失性存储介质中的一个或多个。数据可以以单级单元(SLC)、三级单元(TLC)、四级单元(QLC)和/或多级单元(MLC)格式存储。
除了非易失性储存器731之外,闪存存储装置702还可以包括DRAM 708(或其它易失性存储器)。DRAM 708包括易失性存储器,其可以在闪存存储装置702通电(例如,操作)时存储数据。DRAM可以符合电子装置工程联合会(JEDEC)颁布的标准,例如用于DDR双倍数据速率(DDR)SDRAM的JESD79F、用于DDR2 SDRAM的JESD79-2F、用于DDR3 SDRAM的JESD79-3F、用于DDR4 SDRAM的JESD79-4A、LPDDR3(低功耗双倍数据速率版本3、由JEDEC(电子装置工程联合会)发布的原始版本JESD209-3B(2013年8月,JEDEC)、LPDDR4(低功耗双倍数据速率(LPDDR)版本4、最初由JEDEC于2014年8月公布的JESD209-4、或其它JEDEC标准(这些标准可在www.jedec.org获得)。可以使用其它易失性存储器。一些闪存存储装置不包括DRAM(例如,“无DRAM”SSD)。在一个这样的示例中,闪存存储装置可以包括SSD控制器存储器(未示出),例如SRAM。DRAM 708可以用于存储与闪存存储装置702的操作有关的数据,例如逻辑到物理间接表或其它这种信息。
闪存存储装置702还包括控制器730以控制对存储部件722的访问。在一个示例中,控制器730包括通往存储部件722的输入/输出(I/O)接口,并且包括通往主机的接口(图7中未示出)。控制器730包括用于通信的硬件逻辑(例如,命令逻辑),以控制向存储部件722的写入和从存储部件722的读取。命令逻辑包括用于生成并发出命令以读取储存器731的存储单元的电路。CMOS电路响应于来自控制器730的命令而施加电压选通以读取和写入存储阵列731的存储单元。因此,CMOS电路733包括用于解码来自控制器730的命令并根据所接收的命令将读或写选通施加到存储器单元的电路。控制器还可以包括错误代码校正(ECC)逻辑,以检测和校正从储存器731读取的数据中的错误。控制器730可以是连接到诸如串行ATA的接口的专用集成电路控制器(ASIC)器件或者是集成驱动电子装置控制器。在另一个示例中,控制器730包括处理器或其它处理电路(未示出)。在一个示例中,控制器730可以包括在单个集成电路芯片上的片上系统(SoC)中。
闪存存储装置702还可以包括固件(未示出)。固件可以执行各种功能,例如转换、垃圾收集、耗损均衡以及用于闪存存储装置702的操作和优化的其它功能。在一个示例中,固件可以包括闪存转换层(FTL),其包括用于提供间接方式以识别逻辑地址(例如从文件系统接收的请求的逻辑块地址(LBA))的物理地址空间的逻辑。
闪存存储装置702可以存在于计算机封装的范围内(例如,在膝上型电脑/笔记本电脑或其它计算机内),或者闪存存储装置702也可以经由诸如局域网(例如,以太网)之类的较大网络、或甚至广域网(例如无线蜂窝网、互联网等)来访问。
图8提供了计算系统800(例如,智能电话、平板计算机、膝上型计算机、台式计算机、服务器计算机等)的示例性描绘。如图8中所观察到的,系统800可以包括一个或多个处理器或处理单元801(例如,主机处理器)。处理器801可以包括一个或多个中央处理单元(CPU),所述中央处理单元中的每个可以包括例如多个通用处理核。处理器801还可以或替代地包括一个或多个图形处理单元(GPU)或其它处理单元。处理器801可以包括存储器管理逻辑(例如,存储器控制器)和I/O控制逻辑。
系统800还包括存储器802(例如,系统存储器)、非易失性储存器804、通信接口806和其它部件808。其它部件可以包括例如显示器(例如,触摸屏、平板)、电源(例如,电池或/或其它电源)、传感器、功率管理逻辑或其它部件。通信接口806可以包括支持通信接口的逻辑和/或特征。对于这些示例,通信接口806可以包括一个或多个通信接口,其根据各种通信协议或标准进行操作以通过直接或网络通信链路或信道进行通信。直接通信可以经由使用在诸如与PCIe规范相关联的那些的一个或多个行业标准(包括后代和变体)中描述的通信协议或标准来发生。网络通信可以经由使用诸如在IEEE颁布的一个或多个以太网标准中描述的那些的通信协议或标准发生。例如,一个这种以太网标准可以包括IEEE 802.3。网络通信也可以根据诸如OpenFlow交换机规范之类的一个或多个OpenFlow规范而发生。通信接口的其它示例包括例如本地有线点对点链路(例如,USB)接口、无线局域网(例如,WiFi)接口、无线点对点链路(例如,蓝牙)接口、全球定位系统接口和/或其它接口。
计算系统还包括非易失性储存器804,其可以是系统的大容量存储部件。非易失性储存器804可以与上述的图7的闪存存储装置702相似或相同。非易失类型的存储器可以包括字节或块可寻址的非易失性存储器,例如但不限于多阈值电平NAND闪存存储器、NOR闪存存储器、单级或多级相变存储器(PCM)、电阻式存储器、纳米线存储器、铁电晶体管随机存取存储器(FeTRAM)、并入了忆阻器技术的磁阻随机存取存储器(MRAM)、自旋转移矩MRAM(STT-MRAM)、包括硫族化物相变材料(例如,硫族化物玻璃)的三维(3D)交叉点存储器结构(以下称为“3D交叉点存储器”)或任何上述存储器的组合。在一个示例中,非易失性储存器804可以包括由一个或多个SSD组成的大容量储存器。SSD可以由闪存存储器芯片组成,其包括如上所述的共享CMOS电路和经由晶片到晶片接合技术接合的管芯。
以下是一些示例。在一个示例中,非易失性存储装置包括:第一管芯,该第一管芯包括非易失性存储单元的第一三维(3D)阵列和CMOS(互补金属氧化物半导体)电路;以及与所述第一管芯垂直堆叠并接合的第二管芯,该第二管芯包括非易失性存储单元的第二3D阵列,第一管芯的CMOS电路的至少一部分用于访问第一管芯的非易失性存储单元的第一3D阵列和第二管芯的非易失性存储单元的第二3D阵列两者。在一个这样的示例中,第一管芯的CMOS电路设置在非易失性存储单元的第一3D阵列和非易失性存储单元的第二3D阵列之间。在一个示例中,第二管芯还包括用于访问非易失性存储单元的第一和第二3D阵列的第二CMOS电路。在一个这样的示例中,共享CMOS电路的一部分被包括在第一管芯的第一CMOS电路中,并且共享CMOS电路的剩余部分被包括在第二管芯的第二CMOS电路中。共享CMOS电路包括电荷泵、静态页面缓冲器、IO、控制逻辑和字符串驱动器中的一个或多个。在一个示例中,共享字符串驱动器电路用于访问非易失性存储单元的第一和第二3D阵列,并且用于非易失性存储单元的第一和第二3D阵列的字符串驱动器电路的一部分被包括在第一管芯的CMOS电路中,并且字符串驱动器电路的剩余部分被包括在第二管芯的第二CMOS电路中。在一个示例中,共享CMOS电路的在第一管芯上的部分包括第一类晶体管,并且共享CMOS电路的在第二管芯上的剩余部分包括第二类晶体管。在一个这样的示例中,第一类晶体管包括高电压晶体管,并且第二类晶体管包括低电压晶体管。
在一个示例中,第三管芯与第一或第二管芯垂直堆叠并接合,第三管芯包括非易失性存储单元的第三3D阵列,第一管芯的CMOS电路用于访问非易失性存储单元的第三3D阵列。在一个示例中,第一管芯的层相对于第二管芯以相反的顺序设置,并且第一管芯的CMOS电路的导电接触部与第二管芯的第二CMOS电路的导电接触部接合。在一个示例中,部件包括第一CMOS电路的导电接触部和第二CMOS电路的导电接触部之间的接合焊盘。
在一个示例中,系统包括处理器和与处理器耦合的非易失性存储装置,所述存储装置包括:第一管芯,所述第一管芯包括非易失性存储单元的第一三维(3D)阵列和用于访问非易失性存储单元的第一3D阵列的CMOS(互补金属氧化物半导体)电路;以及与第一管芯垂直堆叠并接合的第二管芯,所述第二管芯包括非易失性存储单元的第二3D阵列,第一管芯的CMOS电路用于访问第二管芯的非易失性存储单元的第二3D阵列。
在一个示例中,三维(3D)NAND存储器装置包括:第一管芯,所述第一管芯包括非易失性NAND存储器单元的第一三维(3D)阵列和控制电路;以及与第一管芯垂直堆叠并接合的第二管芯,所述第二管芯包括非易失性NAND存储器单元的第二3D阵列,第一管芯的控制电路的至少一部分用于访问第一管芯的非易失性NAND存储器单元的第一3D阵列和第二管芯的非易失性NAND存储器单元的第二3D阵列。
在一个示例中,制造非易失性存储装置的方法包括:在第一晶片上形成第一3D非易失性存储阵列和第一CMOS电路,在第二晶片上形成第二3D非易失性存储阵列,第一CMOS电路用于访问第一和第二3D非易失性存储阵列,将第一晶片接合到第二晶片,切割接合的第一和第二晶片,以及利用经切割的接合的晶片形成非易失性存储装置。在一个示例中,将第一晶片接合到第二晶片包括将第一CMOS电路的导电接触部与第二晶片的第二CMOS电路的第二导电接触部接合。在一个示例中,该方法还包括:翻转第一晶片;减薄第一晶片的背面,其中第一CMOS电路靠近第一晶片的背面设置;以及在第一CMOS电路的导电接触部之上将晶片接合焊盘附接到第一晶片的背面,其中,将第一晶片接合到第二晶片包括将第二CMOS电路的第二导电接触部与附接到第一晶片的接合焊盘接合。
本发明的实施例可以包括如上所述的各种过程。所述过程可以体现于机器可执行指令中。所述指令可以用于使得通用或专用处理器执行某些过程。替代地,这些过程可以由包含用于执行该过程的硬布线逻辑电路或可编程逻辑电路(例如,FPGA、PLD)的专用/定制硬件部件、或者由编程的计算机部件和定制硬件部件的任何组合来执行。
本发明的元素也可以被提供为用于存储机器可执行指令的机器可读介质。机器可读介质可以包括但不限于:软盘、光盘、CD-ROM和磁光盘、闪存存储器、ROM、RAM、EPROM、EEPROM、磁卡或光卡、传播介质或适于存储电子指令的其它类型的介质/机器可读介质。例如,本发明可以被下载为计算机程序,可以经由通信链路(例如,调制解调器或网络连接)通过载波或其它传播介质中体现的数据信号将计算机程序从远程计算机(例如,服务器)传输到请求计算机(例如,客户端)。
文中示出的流程图提供了各种过程动作的序列的示例。流程图可以指示由软件或固件例程执行的操作以及物理操作。在一个示例中,流程图可以示出有限状态机(FSM)的状态,其可以以硬件、软件或组合来实施。尽管以特定顺序或次序示出,但除非另有说明,否则可以修改动作的顺序。因此,示出的实施例应该仅被理解为示例,并且过程可以按不同顺序执行,并且一些动作可以并行执行。此外,在各种示例中可以省略一个或多个动作;因此,并非每个实施例都需要所有动作。其它过程流程也是可能的。
在本文中描述各种操作或功能的程度上,可以将操作或功能描述或定义为软件代码、指令、配置、数据或组合。内容可以是直接可执行的(“对象”或“可执行”形式)、源代码或差异代码(“增量”或“补丁”代码)。本文描述的实施例的软件内容可以经由其上存储有内容的制品提供,或者经由操作通信接口以经由通信接口发送数据的方法来提供。机器可读存储介质可以使机器执行所描述的功能或操作,并且包括以机器(例如,计算装置、电子系统等)可访问的形式存储信息的任何机制,例如可记录/不可记录介质(例如,只读存储器(ROM)、随机存取存储器(RAM)、磁盘存储介质、光学存储介质、闪存存储器装置等)。通信接口包括接口连接到硬布线、无线、光学等介质中的任何介质以与另一装置通信的任何机制,例如存储器总线接口、处理器总线接口、因特网连接、磁盘控制器等。可以通过提供配置参数或发送信号或两者来配置通信接口,以准备好通信接口来提供描述软件内容的数据信号。可以经由发送到通信接口的一个或多个命令或信号来访问通信接口。
本文描述的各种部件可以是用于执行所描述的操作或功能的设备。本文描述的每个部件包括软件、硬件或这些的组合。部件可以实施为软件模块、硬件模块、特殊目的硬件(例如,专用硬件、专用集成电路(ASIC)、数字信号处理器(DSP)等)、嵌入式控制器、硬布线电路等。
除了本文所描述的那些之外,可以对所公开的实施例及本发明的实施方式做出各种修改而不脱离其范围。上面用于描述特征的取向和定位的术语,例如“顶部”、“底部”、“之上”、“之下”以及描述定位的其它这种术语旨在阐明特征相对于其它特征的相对位置,并且不描述固定或绝对的定位。例如,被描述为处于底部晶片上方或之上的顶部晶片的晶片可以被描述为处于顶部晶片之下或下方的底部晶片。因此,应当以例示性而非限制性意义来解释本文的例示和示例。本发明的范围应当仅参考后附权利要求而得到度量。
Claims (20)
1.一种非易失性存储装置,包括:
第一管芯,所述第一管芯包括非易失性存储单元的第一三维(3D)阵列和CMOS(互补金属氧化物半导体)电路;以及
与所述第一管芯垂直堆叠并接合的第二管芯,所述第二管芯包括非易失性存储单元的第二3D阵列,所述第一管芯的所述CMOS电路的至少一部分用于访问所述第一管芯的非易失性存储单元的所述第一3D阵列和所述第二管芯的非易失性存储单元的所述第二3D阵列。
2.根据权利要求1所述的非易失性存储装置,其中:
所述第一管芯的所述CMOS电路设置在非易失性存储单元的所述第一3D阵列和非易失性存储单元的所述第二3D阵列之间。
3.根据权利要求2所述的非易失性存储装置,其中:
所述第二管芯还包括用于访问非易失性存储单元的所述第一3D阵列和所述第二3D阵列的第二CMOS电路。
4.根据权利要求3所述的非易失性存储装置,其中:
共享CMOS电路的一部分被包括在所述第一管芯的所述第一CMOS电路中,并且所述共享CMOS电路的剩余部分被包括在所述第二管芯的所述第二CMOS电路中,所述共享CMOS电路包括电荷泵、静态页面缓冲器、IO、控制逻辑和字符串驱动器中的一个或多个。
5.根据权利要求3所述的非易失性存储装置,其中:
共享字符串驱动器电路用于访问非易失性存储单元的所述第一3D阵列和所述第二3D阵列;以及
用于非易失性存储单元的所述第一3D阵列和所述第二3D阵列的所述字符串驱动器电路的一部分被包括在所述第一管芯的所述CMOS电路中,并且字符串驱动器电路的剩余部分被包括在所述第二管芯的所述第二CMOS电路中。
6.根据权利要求4所述的非易失性存储装置,其中:
所述共享CMOS电路的在所述第一管芯上的所述部分包括第一类晶体管,并且所述共享CMOS电路的在所述第二管芯上的所述剩余部分包括第二类晶体管。
7.根据权利要求6所述的非易失性存储装置,其中:
所述第一类晶体管包括高电压晶体管,并且所述第二类晶体管包括低电压晶体管。
8.根据权利要求1所述的非易失性存储装置,还包括:
与所述第一管芯或所述第二管芯垂直堆叠并接合的第三管芯,所述第三管芯包括非易失性存储单元的第三3D阵列,所述第一管芯的所述CMOS电路用于访问非易失性存储单元的所述第三3D阵列。
9.根据权利要求3所述的非易失性存储装置,其中:
所述第一管芯的层相对于所述第二管芯以相反的顺序设置;
所述第一管芯的所述CMOS电路的导电接触部与所述第二管芯的所述第二CMOS电路的导电接触部接合。
10.根据权利要求3所述的非易失性存储装置,还包括:
所述第一CMOS电路的导电接触部和所述第二CMOS电路的导电接触部之间的接合焊盘。
11.一种系统,包括:
处理器;以及
与所述处理器耦合的非易失性存储装置,所述存储装置包括:
第一管芯,所述第一管芯包括非易失性存储单元的第一三维(3D)阵列和用于访问非易失性存储单元的所述第一3D阵列的CMOS(互补金属氧化物半导体)电路;以及
与所述第一管芯垂直堆叠并接合的第二管芯,所述第二管芯包括非易失性存储单元的第二3D阵列,所述第一管芯的所述CMOS电路用于访问所述第二管芯的非易失性存储单元的所述第二3D阵列。
12.根据权利要求11所述的系统,其中:
所述第一管芯的所述CMOS电路设置在非易失性存储单元的所述第一3D阵列和非易失性存储单元的所述第二3D阵列之间。
13.根据权利要求12所述的系统,其中:
所述第二管芯还包括用于访问非易失性存储单元的所述第一3D阵列和所述第二3D阵列的第二CMOS电路。
14.根据权利要求13所述的系统,其中:
共享CMOS电路的一部分被包括在所述第一管芯的所述第一CMOS电路中,并且所述共享CMOS电路的剩余部分被包括在所述第二管芯的所述第二CMOS电路中,所述共享CMOS电路包括电荷泵、静态页面缓冲器、IO、控制逻辑和字符串驱动器中的一个或多个。
15.根据权利要求13所述的系统,其中:
共享字符串驱动器电路用于访问非易失性存储单元的所述第一3D阵列和所述第二3D阵列;以及
用于非易失性存储单元的所述第一3D阵列和所述第二3D阵列的所述字符串驱动器电路的一部分被包括在所述第一管芯的所述CMOS电路中,并且字符串驱动器电路的剩余部分被包括在所述第二管芯的所述第二CMOS电路中。
16.根据权利要求14所述的系统,其中:
所述共享CMOS电路的在所述第一管芯上的所述部分包括第一类晶体管,并且所述共享CMOS电路的在所述第二管芯上的所述剩余部分包括第二类晶体管。
17.根据权利要求16所述的系统,其中:
所述第一类晶体管包括高电压晶体管,并且所述第二类晶体管包括低电压晶体管。
18.根据权利要求11所述的系统,还包括:
与所述第一管芯或所述第二管芯垂直堆叠并接合的第三管芯,所述第三管芯包括非易失性存储单元的第三3D阵列,所述第一管芯的所述CMOS电路用于访问非易失性存储单元的所述第三3D阵列。
19.一种三维(3D)NAND存储器装置,包括:
第一管芯,所述第一管芯包括非易失性NAND存储器单元的第一三维(3D)阵列和控制电路;以及
与所述第一管芯垂直堆叠并接合的第二管芯,所述第二管芯包括非易失性NAND存储器单元的第二3D阵列,所述第一管芯的所述控制电路的至少一部分用于访问所述第一管芯的非易失性NAND存储器单元的所述第一3D阵列和所述第二管芯的非易失性NAND存储器单元的所述第二3D阵列。
20.根据权利要求19所述的三维(3D)NAND存储器装置,其中:
所述第一管芯的所述控制电路设置在非易失性NAND存储器单元的所述第一3D阵列和非易失性NAND存储器单元的所述第二3D阵列之间。
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2018
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2019
- 2019-05-09 JP JP2019089382A patent/JP7346899B2/ja active Active
- 2019-05-13 KR KR1020190055738A patent/KR20190142715A/ko not_active Application Discontinuation
- 2019-05-15 DE DE102019112704.1A patent/DE102019112704A1/de active Pending
- 2019-05-17 CN CN201910410297.1A patent/CN110620117A/zh active Pending
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Also Published As
Publication number | Publication date |
---|---|
US20190043836A1 (en) | 2019-02-07 |
US10651153B2 (en) | 2020-05-12 |
JP2019220244A (ja) | 2019-12-26 |
KR20190142715A (ko) | 2019-12-27 |
DE102019112704A1 (de) | 2019-12-19 |
JP7346899B2 (ja) | 2023-09-20 |
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