JP7134902B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7134902B2 JP7134902B2 JP2019039813A JP2019039813A JP7134902B2 JP 7134902 B2 JP7134902 B2 JP 7134902B2 JP 2019039813 A JP2019039813 A JP 2019039813A JP 2019039813 A JP2019039813 A JP 2019039813A JP 7134902 B2 JP7134902 B2 JP 7134902B2
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- film
- passivation film
- semiconductor device
- conductive layers
- uneven shape
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Description
図1は、第1実施形態に係る半導体装置の平面図である。また、図2は、図1に示す切断線A-Aに沿った断面図である。図1および図2に示す半導体装置1は、メモリセルが積層された三次元積層型半導体記憶装置である。
図5は、第2実施形態に係る半導体装置の概略的な構造を示す断面図である。上述した第1実施形態と同様の構成要素には同じ符号を付し、詳細な説明を省略する。
Claims (4)
- 半導体基板と、
前記半導体基板上で、第1方向に延びるとともに、前記第1方向に垂直な第2方向に間隔をおいて並べられている複数の導電層と、
前記複数の導電層上に設けられたパッシベーション膜と、を備え、
前記パッシベーション膜は、凸部と凹部が前記第2方向に沿って繰り返される凹凸形状を有し、
前記パッシベーション膜は、前記複数の導電層が設けられたセル領域に設けられた第1部分と、前記第1方向または前記第2方向で前記セル領域に隣接する周辺回路領域に設けられた第2部分とに、設けられ、
前記第1部分が前記凹凸形状を有し、前記第2部分が平坦膜である、半導体装置。 - 前記パッシベーション膜は、前記第1部分および前記第2部分を有する第1窒化膜と、前記第1窒化膜上に設けられ、前記凹凸形状を有する第2窒化膜と、を有する、請求項1に記載の半導体装置。
- 前記第1窒化膜の水素含有量が、前記第2窒化膜の水素含有量と異なる、請求項2に記載の半導体装置。
- 前記凸部は、前記複数の導電層上に配置される、請求項1乃至3のいずれか一項に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019039813A JP7134902B2 (ja) | 2019-03-05 | 2019-03-05 | 半導体装置 |
TW108126313A TWI720555B (zh) | 2019-03-05 | 2019-07-25 | 半導體裝置 |
CN201910726276.0A CN111668157B (zh) | 2019-03-05 | 2019-08-07 | 半导体装置 |
US16/564,673 US10998335B2 (en) | 2019-03-05 | 2019-09-09 | Semiconductor device including a passivation film and multiple word lines |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019039813A JP7134902B2 (ja) | 2019-03-05 | 2019-03-05 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020145279A JP2020145279A (ja) | 2020-09-10 |
JP7134902B2 true JP7134902B2 (ja) | 2022-09-12 |
Family
ID=72335473
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019039813A Active JP7134902B2 (ja) | 2019-03-05 | 2019-03-05 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10998335B2 (ja) |
JP (1) | JP7134902B2 (ja) |
CN (1) | CN111668157B (ja) |
TW (1) | TWI720555B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021028950A (ja) * | 2019-08-09 | 2021-02-25 | キオクシア株式会社 | 半導体記憶装置 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150599A (ja) | 1998-11-17 | 2000-05-30 | Nec Corp | 半導体装置の配線構造 |
JP2004134594A (ja) | 2002-10-10 | 2004-04-30 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2005183917A (ja) | 2003-12-19 | 2005-07-07 | Hynix Semiconductor Inc | シリコン窒化膜のストレスを防止及び緩衝できるパッド構造を備えた半導体装置 |
JP2008244032A (ja) | 2007-03-27 | 2008-10-09 | Sharp Corp | 半導体装置及びその製造方法 |
JP2009143775A (ja) | 2007-12-14 | 2009-07-02 | Tosoh Quartz Corp | 石英ガラスの表面改質方法 |
JP2010219543A (ja) | 2010-04-27 | 2010-09-30 | Toshiba Corp | 半導体装置 |
JP2010243420A (ja) | 2009-04-09 | 2010-10-28 | Alps Electric Co Ltd | Memsセンサ及び製造方法 |
US20170317217A1 (en) | 2014-11-11 | 2017-11-02 | Sharp Kabushiki Kaisha | Semiconductor device and method for manufacturing same |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS63232447A (ja) * | 1987-03-20 | 1988-09-28 | Nec Corp | 半導体装置 |
JPH05291582A (ja) | 1992-04-14 | 1993-11-05 | Sony Corp | 不揮発性半導体装置 |
JPH07120784A (ja) * | 1993-10-22 | 1995-05-12 | Rohm Co Ltd | 液晶表示装置およびその製法 |
JPH0982800A (ja) * | 1995-09-13 | 1997-03-28 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
JPH1092810A (ja) | 1996-09-10 | 1998-04-10 | Mitsubishi Electric Corp | 半導体装置 |
JP3242892B2 (ja) * | 1998-01-20 | 2001-12-25 | ローム株式会社 | 半導体装置 |
JP3459355B2 (ja) * | 1998-03-27 | 2003-10-20 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP4954549B2 (ja) * | 2005-12-29 | 2012-06-20 | ローム株式会社 | 半導体発光素子およびその製法 |
KR100703984B1 (ko) * | 2006-03-22 | 2007-04-09 | 삼성전자주식회사 | 반도체 집적 회로 장치의 제조 방법 및 그 구조 |
KR101374337B1 (ko) * | 2007-10-18 | 2014-03-17 | 삼성전자주식회사 | 능동소자를 갖는 반도체소자 및 그 제조방법 |
JP2014053447A (ja) * | 2012-09-07 | 2014-03-20 | Toshiba Corp | 不揮発性半導体記憶装置 |
TWI576986B (zh) * | 2015-09-30 | 2017-04-01 | 旺宏電子股份有限公司 | 記憶體結構 |
JP2017120831A (ja) * | 2015-12-28 | 2017-07-06 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
IT201600090858A1 (it) * | 2016-09-08 | 2018-03-08 | Sabrina Barbato | Dispositivo di memoria 3d |
JP2018046167A (ja) * | 2016-09-15 | 2018-03-22 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
CN106920796B (zh) * | 2017-03-08 | 2019-02-15 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法 |
EP3654957A4 (en) * | 2017-05-24 | 2021-06-23 | Annovis Bio, Inc. | PREVENTION OR TREATMENT OF DISEASE CONDITIONS DUE TO METAL DIS-HOMEOSTASIS BY ADMINISTERING POSIPHES TO HEALTHY OR SICK PEOPLE |
US10651153B2 (en) * | 2018-06-18 | 2020-05-12 | Intel Corporation | Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding |
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2019
- 2019-03-05 JP JP2019039813A patent/JP7134902B2/ja active Active
- 2019-07-25 TW TW108126313A patent/TWI720555B/zh active
- 2019-08-07 CN CN201910726276.0A patent/CN111668157B/zh active Active
- 2019-09-09 US US16/564,673 patent/US10998335B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000150599A (ja) | 1998-11-17 | 2000-05-30 | Nec Corp | 半導体装置の配線構造 |
JP2004134594A (ja) | 2002-10-10 | 2004-04-30 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2005183917A (ja) | 2003-12-19 | 2005-07-07 | Hynix Semiconductor Inc | シリコン窒化膜のストレスを防止及び緩衝できるパッド構造を備えた半導体装置 |
JP2008244032A (ja) | 2007-03-27 | 2008-10-09 | Sharp Corp | 半導体装置及びその製造方法 |
JP2009143775A (ja) | 2007-12-14 | 2009-07-02 | Tosoh Quartz Corp | 石英ガラスの表面改質方法 |
JP2010243420A (ja) | 2009-04-09 | 2010-10-28 | Alps Electric Co Ltd | Memsセンサ及び製造方法 |
JP2010219543A (ja) | 2010-04-27 | 2010-09-30 | Toshiba Corp | 半導体装置 |
US20170317217A1 (en) | 2014-11-11 | 2017-11-02 | Sharp Kabushiki Kaisha | Semiconductor device and method for manufacturing same |
Also Published As
Publication number | Publication date |
---|---|
CN111668157B (zh) | 2023-09-15 |
US10998335B2 (en) | 2021-05-04 |
TW202034376A (zh) | 2020-09-16 |
JP2020145279A (ja) | 2020-09-10 |
US20200286913A1 (en) | 2020-09-10 |
TWI720555B (zh) | 2021-03-01 |
CN111668157A (zh) | 2020-09-15 |
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