IT201600090858A1 - Dispositivo di memoria 3d - Google Patents

Dispositivo di memoria 3d

Info

Publication number
IT201600090858A1
IT201600090858A1 IT102016000090858A IT201600090858A IT201600090858A1 IT 201600090858 A1 IT201600090858 A1 IT 201600090858A1 IT 102016000090858 A IT102016000090858 A IT 102016000090858A IT 201600090858 A IT201600090858 A IT 201600090858A IT 201600090858 A1 IT201600090858 A1 IT 201600090858A1
Authority
IT
Italy
Prior art keywords
memory device
memory
Prior art date
Application number
IT102016000090858A
Other languages
English (en)
Inventor
Sabrina Barbato
Original Assignee
Sabrina Barbato
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sabrina Barbato filed Critical Sabrina Barbato
Priority to IT102016000090858A priority Critical patent/IT201600090858A1/it
Priority to US15/698,523 priority patent/US10418375B2/en
Publication of IT201600090858A1 publication Critical patent/IT201600090858A1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
IT102016000090858A 2016-09-08 2016-09-08 Dispositivo di memoria 3d IT201600090858A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT102016000090858A IT201600090858A1 (it) 2016-09-08 2016-09-08 Dispositivo di memoria 3d
US15/698,523 US10418375B2 (en) 2016-09-08 2017-09-07 3D memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102016000090858A IT201600090858A1 (it) 2016-09-08 2016-09-08 Dispositivo di memoria 3d

Publications (1)

Publication Number Publication Date
IT201600090858A1 true IT201600090858A1 (it) 2018-03-08

Family

ID=58606378

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102016000090858A IT201600090858A1 (it) 2016-09-08 2016-09-08 Dispositivo di memoria 3d

Country Status (2)

Country Link
US (1) US10418375B2 (it)
IT (1) IT201600090858A1 (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102475454B1 (ko) * 2016-01-08 2022-12-08 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
US10593730B1 (en) 2018-10-10 2020-03-17 Micron Technology, Inc. Three-dimensional memory array
JP7134902B2 (ja) * 2019-03-05 2022-09-12 キオクシア株式会社 半導体装置
US11094784B2 (en) 2019-04-08 2021-08-17 International Business Machines Corporation Gate-all-around field effect transistor having stacked U shaped channels configured to improve the effective width of the transistor
JP2021034529A (ja) * 2019-08-22 2021-03-01 キオクシア株式会社 不揮発性半導体記憶装置
US11557537B2 (en) 2020-08-06 2023-01-17 Micron Technology, Inc. Reduced pitch memory subsystem for memory device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130153978A1 (en) * 2011-12-20 2013-06-20 Ki Hong Lee 3d non-volatile memory device and method of manufacturing the same
US20160020221A1 (en) * 2014-07-21 2016-01-21 SK Hynix Inc. Three-dimensional (3d) non-volatile memory device
US20160118395A1 (en) * 2014-10-24 2016-04-28 SK Hynix Inc. Semiconductor device and method of fabricating the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101164954B1 (ko) * 2009-09-14 2012-07-12 에스케이하이닉스 주식회사 3차원 구조를 갖는 비휘발성 메모리 소자 및 그 제조 방법
US8187932B2 (en) * 2010-10-15 2012-05-29 Sandisk 3D Llc Three dimensional horizontal diode non-volatile memory array and method of making thereof
KR20120130939A (ko) 2011-05-24 2012-12-04 에스케이하이닉스 주식회사 3차원 구조의 비휘발성 메모리 소자 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130153978A1 (en) * 2011-12-20 2013-06-20 Ki Hong Lee 3d non-volatile memory device and method of manufacturing the same
US20160020221A1 (en) * 2014-07-21 2016-01-21 SK Hynix Inc. Three-dimensional (3d) non-volatile memory device
US20160118395A1 (en) * 2014-10-24 2016-04-28 SK Hynix Inc. Semiconductor device and method of fabricating the same

Also Published As

Publication number Publication date
US20180069016A1 (en) 2018-03-08
US10418375B2 (en) 2019-09-17

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