IT201600090862A1 - Dispositivo di memoria 3d - Google Patents

Dispositivo di memoria 3d

Info

Publication number
IT201600090862A1
IT201600090862A1 IT102016000090862A IT201600090862A IT201600090862A1 IT 201600090862 A1 IT201600090862 A1 IT 201600090862A1 IT 102016000090862 A IT102016000090862 A IT 102016000090862A IT 201600090862 A IT201600090862 A IT 201600090862A IT 201600090862 A1 IT201600090862 A1 IT 201600090862A1
Authority
IT
Italy
Prior art keywords
memory device
memory
Prior art date
Application number
IT102016000090862A
Other languages
English (en)
Inventor
Sabrina Barbato
Original Assignee
Sabrina Barbato
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sabrina Barbato filed Critical Sabrina Barbato
Priority to IT102016000090862A priority Critical patent/IT201600090862A1/it
Priority to US15/698,529 priority patent/US10431592B2/en
Publication of IT201600090862A1 publication Critical patent/IT201600090862A1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
IT102016000090862A 2016-09-08 2016-09-08 Dispositivo di memoria 3d IT201600090862A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT102016000090862A IT201600090862A1 (it) 2016-09-08 2016-09-08 Dispositivo di memoria 3d
US15/698,529 US10431592B2 (en) 2016-09-08 2017-09-07 3D memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102016000090862A IT201600090862A1 (it) 2016-09-08 2016-09-08 Dispositivo di memoria 3d

Publications (1)

Publication Number Publication Date
IT201600090862A1 true IT201600090862A1 (it) 2018-03-08

Family

ID=58606379

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102016000090862A IT201600090862A1 (it) 2016-09-08 2016-09-08 Dispositivo di memoria 3d

Country Status (2)

Country Link
US (1) US10431592B2 (it)
IT (1) IT201600090862A1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102585085B1 (ko) 2019-03-01 2023-10-04 양쯔 메모리 테크놀로지스 씨오., 엘티디. 비트 라인 수가 증가된 아키텍처를 가진 3차원 메모리 소자
US20210296360A1 (en) * 2020-03-21 2021-09-23 Fu-Chang Hsu Three dimensional double-density memory array

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130153978A1 (en) * 2011-12-20 2013-06-20 Ki Hong Lee 3d non-volatile memory device and method of manufacturing the same
US20160020221A1 (en) * 2014-07-21 2016-01-21 SK Hynix Inc. Three-dimensional (3d) non-volatile memory device
US20160118395A1 (en) * 2014-10-24 2016-04-28 SK Hynix Inc. Semiconductor device and method of fabricating the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5072696B2 (ja) * 2008-04-23 2012-11-14 株式会社東芝 三次元積層不揮発性半導体メモリ
JP5072995B2 (ja) * 2010-03-24 2012-11-14 株式会社東芝 不揮発性半導体記憶装置
JP2012227326A (ja) * 2011-04-19 2012-11-15 Toshiba Corp 不揮発性半導体記憶装置とその製造方法
KR20120130939A (ko) 2011-05-24 2012-12-04 에스케이하이닉스 주식회사 3차원 구조의 비휘발성 메모리 소자 및 그 제조 방법
US8897070B2 (en) * 2011-11-02 2014-11-25 Sandisk Technologies Inc. Selective word line erase in 3D non-volatile memory
KR20130088348A (ko) * 2012-01-31 2013-08-08 에스케이하이닉스 주식회사 3차원 비휘발성 메모리 소자
JP5808708B2 (ja) * 2012-04-10 2015-11-10 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US8970040B1 (en) * 2013-09-26 2015-03-03 Macronix International Co., Ltd. Contact structure and forming method
JP6139370B2 (ja) * 2013-10-17 2017-05-31 株式会社東芝 不揮発性半導体記憶装置
JP2015176870A (ja) * 2014-03-12 2015-10-05 株式会社東芝 不揮発性半導体記憶装置
US9397043B1 (en) * 2015-03-27 2016-07-19 Kabushiki Kaisha Toshiba Semiconductor memory device
US9721668B2 (en) * 2015-08-06 2017-08-01 Macronix International Co., Ltd. 3D non-volatile memory array with sub-block erase architecture
KR20170028731A (ko) * 2015-09-04 2017-03-14 에스케이하이닉스 주식회사 비휘발성 메모리 소자 및 그 제조방법
KR102408648B1 (ko) * 2015-11-05 2022-06-14 에스케이하이닉스 주식회사 3차원 비휘발성 메모리 장치
US10223004B2 (en) * 2016-04-07 2019-03-05 International Business Machines Corporation Parallel read and writes in 3D flash memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130153978A1 (en) * 2011-12-20 2013-06-20 Ki Hong Lee 3d non-volatile memory device and method of manufacturing the same
US20160020221A1 (en) * 2014-07-21 2016-01-21 SK Hynix Inc. Three-dimensional (3d) non-volatile memory device
US20160118395A1 (en) * 2014-10-24 2016-04-28 SK Hynix Inc. Semiconductor device and method of fabricating the same

Also Published As

Publication number Publication date
US20180069017A1 (en) 2018-03-08
US10431592B2 (en) 2019-10-01

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