TWI800873B - 半導體記憶裝置 - Google Patents

半導體記憶裝置 Download PDF

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Publication number
TWI800873B
TWI800873B TW110126661A TW110126661A TWI800873B TW I800873 B TWI800873 B TW I800873B TW 110126661 A TW110126661 A TW 110126661A TW 110126661 A TW110126661 A TW 110126661A TW I800873 B TWI800873 B TW I800873B
Authority
TW
Taiwan
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Application number
TW110126661A
Other languages
English (en)
Other versions
TW202209331A (zh
Inventor
山崎貴史
菊地伸一
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202209331A publication Critical patent/TW202209331A/zh
Application granted granted Critical
Publication of TWI800873B publication Critical patent/TWI800873B/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C14/00Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G11C14/0018Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/10Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141Battery and back-up supplies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B80/00Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Memories (AREA)
TW110126661A 2017-12-12 2018-08-06 半導體記憶裝置 TWI800873B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017238103A JP6942039B2 (ja) 2017-12-12 2017-12-12 半導体記憶装置
JP2017-238103 2017-12-12

Publications (2)

Publication Number Publication Date
TW202209331A TW202209331A (zh) 2022-03-01
TWI800873B true TWI800873B (zh) 2023-05-01

Family

ID=66696377

Family Applications (3)

Application Number Title Priority Date Filing Date
TW107127275A TWI690057B (zh) 2017-12-12 2018-08-06 半導體記憶裝置
TW109106111A TWI737192B (zh) 2017-12-12 2018-08-06 半導體記憶裝置
TW110126661A TWI800873B (zh) 2017-12-12 2018-08-06 半導體記憶裝置

Family Applications Before (2)

Application Number Title Priority Date Filing Date
TW107127275A TWI690057B (zh) 2017-12-12 2018-08-06 半導體記憶裝置
TW109106111A TWI737192B (zh) 2017-12-12 2018-08-06 半導體記憶裝置

Country Status (4)

Country Link
US (2) US10629263B2 (zh)
JP (1) JP6942039B2 (zh)
CN (2) CN109920783B (zh)
TW (3) TWI690057B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6942039B2 (ja) * 2017-12-12 2021-09-29 キオクシア株式会社 半導体記憶装置
US11715520B2 (en) 2021-04-05 2023-08-01 Micron Technology, Inc. Socket structure for spike current suppression in a memory array
US11348640B1 (en) 2021-04-05 2022-05-31 Micron Technology, Inc. Charge screening structure for spike current suppression in a memory array
US11862215B2 (en) 2021-08-27 2024-01-02 Micron Technology, Inc. Access line having a resistive layer for memory cell access
JP2023045290A (ja) * 2021-09-21 2023-04-03 キオクシア株式会社 記憶装置
JP2023137985A (ja) * 2022-03-18 2023-09-29 キオクシア株式会社 メモリシステム

Citations (4)

* Cited by examiner, † Cited by third party
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US20050207205A1 (en) * 2001-08-16 2005-09-22 Sony Corporation Ferroelectric-type nonvolatile semiconductor memory
US20150078055A1 (en) * 2013-09-17 2015-03-19 Samsung Electronics Co., Ltd. Memory module and manufacturing method thereof
US20160049177A1 (en) * 2014-08-15 2016-02-18 Kabushiki Kaisha Toshiba Memory system, storage system
US20160254031A1 (en) * 2015-02-26 2016-09-01 Kabushiki Kaisha Toshiba Semiconductor memory device

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US5910755A (en) * 1993-03-19 1999-06-08 Fujitsu Limited Laminate circuit board with selectable connections between wiring layers
JP2002074985A (ja) * 2000-08-29 2002-03-15 Mitsubishi Electric Corp メモリモジュールおよびその製造方法ならびにそれに使用するテストコネクタ
US7414312B2 (en) * 2005-05-24 2008-08-19 Kingston Technology Corp. Memory-module board layout for use with memory chips of different data widths
KR20100101958A (ko) 2009-03-10 2010-09-20 삼성전자주식회사 슈퍼 커패시터를 포함하는 고체 상태 구동기
KR20110028999A (ko) * 2009-09-14 2011-03-22 삼성전자주식회사 이종의 커넥터를 선택적으로 적용할 수 있는 메모리 장치
JP2015038643A (ja) 2010-06-29 2015-02-26 株式会社東芝 補助電源制御回路、記憶装置、および補助電源制御方法
US8310098B2 (en) * 2011-05-16 2012-11-13 Unigen Corporation Switchable capacitor arrays for preventing power interruptions and extending backup power life
JP2013033914A (ja) * 2011-06-27 2013-02-14 Toshiba Corp 半導体装置
JP5741416B2 (ja) * 2011-12-08 2015-07-01 Tdk株式会社 電子部品の実装構造
JP2016053757A (ja) * 2014-09-02 2016-04-14 株式会社東芝 メモリシステム
WO2016068978A1 (en) * 2014-10-31 2016-05-06 Hewlett-Packard Development Company, L.P. Power-loss protection
JP6313252B2 (ja) * 2015-03-16 2018-04-18 東芝メモリ株式会社 半導体メモリ装置
JP6381480B2 (ja) * 2015-05-12 2018-08-29 東芝メモリ株式会社 半導体装置
JP6523136B2 (ja) 2015-10-27 2019-05-29 東芝メモリ株式会社 半導体装置及び電子機器
US10283173B2 (en) * 2017-04-19 2019-05-07 Seagate Technologies Llc Intelligent backup capacitor management
JP6942039B2 (ja) * 2017-12-12 2021-09-29 キオクシア株式会社 半導体記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050207205A1 (en) * 2001-08-16 2005-09-22 Sony Corporation Ferroelectric-type nonvolatile semiconductor memory
US20150078055A1 (en) * 2013-09-17 2015-03-19 Samsung Electronics Co., Ltd. Memory module and manufacturing method thereof
US20160049177A1 (en) * 2014-08-15 2016-02-18 Kabushiki Kaisha Toshiba Memory system, storage system
US20160254031A1 (en) * 2015-02-26 2016-09-01 Kabushiki Kaisha Toshiba Semiconductor memory device

Also Published As

Publication number Publication date
TW202025455A (zh) 2020-07-01
JP6942039B2 (ja) 2021-09-29
TWI690057B (zh) 2020-04-01
CN109920783A (zh) 2019-06-21
US11158372B2 (en) 2021-10-26
CN116759420A (zh) 2023-09-15
JP2019106227A (ja) 2019-06-27
TW201929196A (zh) 2019-07-16
TW202209331A (zh) 2022-03-01
US10629263B2 (en) 2020-04-21
US20190180819A1 (en) 2019-06-13
TWI737192B (zh) 2021-08-21
CN109920783B (zh) 2023-08-25
US20200219565A1 (en) 2020-07-09

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