CN114093874A - 3d nand闪速存储器件及其集成方法 - Google Patents

3d nand闪速存储器件及其集成方法 Download PDF

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CN114093874A
CN114093874A CN202111229286.7A CN202111229286A CN114093874A CN 114093874 A CN114093874 A CN 114093874A CN 202111229286 A CN202111229286 A CN 202111229286A CN 114093874 A CN114093874 A CN 114093874A
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flash memory
memory device
nand flash
cmos die
onfi
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顾沂
侯春源
李跃平
陈嘉伟
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Yangtze Memory Technologies Co Ltd
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Abstract

本申请实施例公开了一种存储器件，所述存储器件包括：CMOS管芯；设置于所述CMOS管芯上的至少一个NOR闪存存储器；所述至少一个NOR闪存存储器与所述CMOS管芯上的开放NAND闪存接口ONFI连接。

Description

3D NAND闪速存储器件及其集成方法
本申请是针对申请日为2020年05月20日，申请号为202080001324.0，发明名称为3D NAND闪速存储器件及其集成方法的专利的分案申请。
技术领域
本申请实施例涉及3D NAND闪速存储器件及其集成方法，涉及但不限于一种能够改善存储空间和读/写性能的3D NAND闪速存储器件及其集成方法。
背景技术
为了提供固态盘(SSD)的更好性能，在常规SSD实现方式中广泛利用了单级单元(SLC)NAND闪速存储器和3D三级单元(TLC)NAND闪速存储器的组合结构。常常被读/写的热数据存储在SLC NAND闪存中，不常被读/写的冷数据存储在3D TLC NAND闪存中。然而，以上组合结构利用的3D TLC NAND闪速存储器降低了存储密度并且提高了SSD的成本。另外，组合结构的SLC NAND的读/写性能不令人满意。因此，对现有技术做出改进是必要的。
发明内容
本公开实施例提供了一种3D NAND闪速存储器件及其制造方法，以改善存储空间和读/写性能。本申请实施例提供一种3D NAND闪速存储器件及其制造方法。
本公开的实施例公开了一种用于3D NAND闪速存储器件的集成方法，包括：在CMOS管芯上设置多个3D三级单元(TLC)NAND闪速存储器；在所述3D NAND闪速存储器件的所述CMOS管芯上设置至少一个NOR闪速存储器；以及将所述至少一个NOR闪速存储器连接到所述3D NAND闪速存储器件的开放NAND闪存接口(ONFI)；其中所述至少一个NOR闪速存储器设置于所述CMOS管芯的未使用区域上。
本公开的另一实施例公开了一种集成于CMOS管芯上的3D NAND闪速存储器件，包括：设置于CMOS管芯上的多个3D三级单元(TLC)NAND闪速存储器；以及设置于所述CMOS管芯上的至少一个NOR闪速存储器，所述至少一个NOR闪速存储器连接到所述3D NAND闪速存储器的开放NAND闪存接口(ONFI)；其中，所述至少一个NOR闪速存储器设置于所述CMOS管芯的未使用区域上。
在阅读各附图所示的优选实施例的以下详细描述之后，本领域的普通技术人员将毫无疑问得地明了本公开实施例的这些和其它目的。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1是根据本公开实施例的用于3D NAND闪速存储器件的集成工艺的示意图；
图2-图3是根据本公开实施例的应用所述集成工艺的3D NAND闪速存储器件的示意图。
具体实施方式
图1是根据本公开实施例的用于3D NAND闪速存储器件的集成工艺10的示意图。用于3D NAND闪速存储器件的集成工艺10包括以下步骤：
步骤102：开始。
步骤104：在CMOS管芯上设置多个3D三级单元(TLC)NAND闪速存储器。
步骤106：在所述3D NAND闪速存储器件的所述CMOS管芯上设置至少一NOR闪速存储器。
步骤108：将所述至少一NOR闪速存储器连接到所述3D NAND闪速存储器件的开放NAND闪存接口(ONFI)。
步骤110：在所述3D NAND闪速存储器件的所述至少一NOR闪速存储器与所述ONFI之间连接数据通路逻辑单元。
步骤112：结束。
为了解释集成工艺10，请还参考图2和图3，图2和图3是根据本公开实施例的应用集成工艺10的3D NAND闪速存储器件20的示意图。如图2中所示，3D NAND闪速存储器件20包括嵌入有多个3D TLC NAND闪速存储器204的CMOS管芯202。
根据集成工艺10，在步骤104中，将3D TLC NAND闪速存储器204设置于CMOS管芯202上，每个3D TLC NAND闪速存储器204彼此不重叠，从而在CMOS管芯202上形成在每个3DTLC NAND闪速存储器204之间的间隙。
在步骤106中，在3D NAND闪速存储器件20的CMOS管芯202上设置至少一NOR闪速存储器，其中，所述至少一NOR闪速存储器设置于CMOS管芯202的未使用区域上，CMOS管芯202的未使用区域可以是在3D TLC NAND闪速存储器204中的每一者之间的间隙、CMOS管芯202的冗余或空白区域。同样地，如图3所示，在CMOS管芯202的未使用区域中设置多个NOR闪速存储器206，使得随着NOR闪速存储器206的设置，3D NAND闪速存储器件20的存储空间增大，并且改善3D NAND闪速存储器件20的灵活性。要指出的是，NOR闪速存储器206的量不限于图2和图3中所示的四个，根据其它要求可以在CMOS管芯202的未使用区域中设置其它量的一定部署密度的NOR闪速存储器。
在步骤108中，将NOR闪速存储器206连接到3D NAND闪速存储器件20的ONFI，其中，ONFI是用于对3D NAND闪速存储器件20的管脚分配和命令进行标准化的接口，所述ONFI连接3D TLC NAND闪速存储器204。在步骤110中，连接在NOR闪速存储器206于ONFI之间的数据通路逻辑单元。在步骤108中将NOR闪速存储器206的数据通路逻辑单元连接到ONFI之后，可以指示NOR闪速存储器206根据ONFI的管脚分配和命令来读/写数据。亦即，NOR闪速存储器206可以与3D TLC NAND闪速存储器204共享ONFI，以经由ONFI读/写数据，或者直接经由ONFI读/写数据。
由于NOR闪速存储器206支持随机读和随机写，所以在写入多条小数据时，改善了3D NAND闪速存储器件20的读取时间的性能和写入时间的性能。另外，将3D NAND闪速存储器件20的控制器用于执行针对存储在3D TLC NAND闪速存储器204中的数据的错误控制编码过程。然而，NOR闪速存储器206处理的数据没有错误控制编码，这样降低了3D NAND闪速存储器件20的控制器的复杂性并且改善3D NAND闪速存储器件20的性能。
本公开实施例设置有NOR闪速存储器206的3D NAND闪速存储器件20可以应用于常规固态磁盘(SSD)产品中以改善读/写性能。另外，通过在CMOS管芯202的未使用区域中设置NOR闪速存储器206，维持了3D NAND闪速存储器件20的制造成本。
如图3中所示，应用集成方法10集成在本公开实施例的CMOS管芯202上的3D NAND闪速存储器件20包括3D TLC NAND闪速存储器204和NOR闪速存储器206。3D TLC NAND闪速存储器204设置于CMOS管芯202上，并且NOR闪速存储器206设置于CMOS管芯的未使用区域上。另外，由于NOR闪速存储器206的数据通路逻辑单元连接到ONFI，ONFI对3D NAND闪速存储器件20的管脚分配和命令进行标准化，3D NAND闪速存储器件20的复杂性降低，并且读/写性能得到提高，而不会增大3D NAND闪速存储器件20的制造成本。
要指出的是，上述实施例例示了本公开的概念，本领域的技术人员可以相应地作出适当修改并且不限于此。
概括地说，本公开提供了一种3D NAND闪速存储器件及其集成方法，改善了存储空间、读/写性能而不提高制造成本。
本领域的技术人员将容易发现，可以对所述装置和方法做出多种修改和更改同时保持本公开的教导。因此，应当将以上公开解释为仅受所附权利要求的范围限制。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
以上所述，仅为本申请的实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (10)

1.一种存储器件，其特征在于，包括：
CMOS管芯；
设置于所述CMOS管芯上的至少一个NOR闪存存储器；
所述至少一个NOR闪存存储器与所述CMOS管芯上的开放NAND闪存接口ONFI连接。
2.根据权利要求1所述的存储器件，其特征在于，所述器件还包括：
所述至少一NOR闪速存储器与所述ONFI之间连接数据通路逻辑单元。
3.根据权利要求1所述的存储器件，其特征在于，所述至少一NOR闪速存储器经由所述ONFI读取和/或写入数据。
4.根据权利要求3所述的存储器件，其特征在于，所述至少一NOR闪速存储器根据ONFI的管脚分配和命令进行读取和/或写入数据。
5.根据权利要求1所述的存储器件，其特征在于，所述至少一NOR闪速存储器被配置为执行随机读取和随机写入。
6.根据权利要求1所述的存储器件，其特征在于，所述CMOS管芯上还设置有3D NAND闪存存储器件。
7.根据权利要求6所述的存储器件，其特征在于，所述3D NAND闪存存储器件，包括：
3D TLC NAND闪存存储器。
8.根据权利要求6所述的存储器件，其特征在于，所述3D NAND闪存存储器件与所述NOR闪存存储器位于所述CMOS管芯的不同区域。
9.根据权利要求6所述的存储器件，其特征在于，所述3D NAND闪存存储器件与所述NOR闪存存储器共用所述CMOS管芯上的开放NAND闪存接口ONFI。
10.根据权利要求1所述的存储器件，其特征在于，所述存储器件应用于固态硬盘。
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