TW202144990A - 3d nand快閃記憶體裝置及其集成方法 - Google Patents

3d nand快閃記憶體裝置及其集成方法 Download PDF

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TW202144990A
TW202144990A TW109125133A TW109125133A TW202144990A TW 202144990 A TW202144990 A TW 202144990A TW 109125133 A TW109125133 A TW 109125133A TW 109125133 A TW109125133 A TW 109125133A TW 202144990 A TW202144990 A TW 202144990A
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顧沂
侯春源
李躍平
陳嘉偉
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大陸商長江存儲科技有限責任公司
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Abstract

一種用於3D NAND快閃記憶體裝置的集成方法包括在一互補式金屬氧化物半導體晶粒上設置複數個3D三層單元NAND快閃記憶體；在該3D NAND快閃記憶體裝置的該CMOS晶粒上設置至少一NOR快閃記憶體；以及將該至少一NOR快閃記憶體連接到該3D NAND快閃記憶體裝置的一開放NAND快閃記憶體介面；其中該至少一NOR快閃記憶體設置於該CMOS晶粒的一未使用區域上。

Description

3D　NAND快閃記憶體裝置及其集成方法
本發明係指一種3D NAND快閃記憶體裝置及其集成方法，尤指一種能夠改善儲存空間和讀/寫性能的3D NAND快閃記憶體裝置及其集成方法。
為了提供固態硬碟（Solid-state disk，SSD）的更好性能，在常規SSD實現方式中廣泛利用了單層單元（single-level cell，SLC）NAND快閃記憶體和3D三層單元（triple-level cell，TLC）NAND快閃記憶體的組合結構，其中常常被讀/寫的熱資料儲存在SLC NAND快閃記憶體中，而不常被讀/寫的冷資料儲存在3D TLC NAND快閃記憶體中。然而，以上組合結構利用的3D TLC NAND快閃記憶體降低了儲存密度並且提高了SSD的成本。另外，組合結構的SLC NAND的讀/寫性能不令人滿意。因此，對現有技術做出改進是必要的。
本發明提供了一種3D NAND快閃記憶體裝置及其製造方法，以改善儲存空間和讀/寫性能。
本發明實施例揭露了一種用於3D NAND快閃記憶體裝置的集成方法，包括在一互補式金屬氧化物半導體（Complementary Metal-Oxide-Semiconductor，CMOS）晶粒（die）上設置複數個3D三層單元（triple-level cell，TLC）NAND快閃記憶體；在該3D NAND快閃記憶體裝置的該CMOS晶粒上設置至少一NOR快閃記憶體；以及將該至少一NOR快閃記憶體連接到該3D NAND快閃記憶體裝置的一開放NAND快閃記憶體介面（Open NAND Flash Interface，ONFI）；其中該至少一NOR快閃記憶體設置於該CMOS晶粒的一未使用區域上。
本發明實施例另揭露了一種集成於CMOS晶粒上的3D NAND快閃記憶體裝置，包括設置於該CMOS晶粒上的複數個3D三層單元（TLC）NAND快閃記憶體；以及設置於該CMOS晶粒上的至少一NOR快閃記憶體，該至少一NOR快閃記憶體連接到該3D NAND快閃記憶體的開放NAND快閃記憶體介面（ONFI）；其中該至少一NOR快閃記憶體設置於該CMOS晶粒的一未使用區域上。
第1圖是根據本發明實施例的用於3D NAND快閃記憶體裝置的集成流程10之示意圖。用於3D NAND快閃記憶體裝置的集成流程10包括以下步驟：
步驟102：開始。
步驟104：在一互補式金屬氧化物半導體（Complementary Metal-Oxide-Semiconductor，CMOS）晶粒（die）上設置複數個3D三層單元（triple-level cell，TLC）NAND快閃記憶體。
步驟106：在該3D NAND快閃記憶體裝置的該CMOS晶粒上設置至少一NOR快閃記憶體。
步驟108：將該至少一NOR快閃記憶體連接到該3D NAND快閃記憶體裝置的一開放NAND快閃記憶體介面（Open NAND Flash Interface，ONFI）。
步驟110：在該3D NAND快閃記憶體裝置的該至少一NOR快閃記憶體與該ONFI之間連接資料通路邏輯（datapath logic）單元。
步驟112：結束。
為了說明集成流程10，請同時參考第2圖和第3圖，第2圖和第3圖是根據本發明實施例的應用集成流程10的3D NAND快閃記憶體裝置20之示意圖。如第2圖中所示，3D NAND快閃記憶體裝置20包括嵌入有複數個3D TLC NAND快閃記憶體204的CMOS晶粒202。
根據集成流程10，在步驟104中，將3D TLC NAND快閃記憶體204設置於CMOS晶粒202上，每個3D TLC NAND快閃記憶體204彼此不重疊，從而在CMOS晶粒202上形成在每個3D TLC NAND快閃記憶體204之間的間隙。
在步驟106中，在3D NAND快閃記憶體裝置20的CMOS晶粒202上設置至少一NOR快閃記憶體，其中該至少一NOR快閃記憶體設置於CMOS晶粒202的未使用區域上，CMOS晶粒202的未使用區域可以是在3D TLC NAND快閃記憶體204中的每一者之間的間隙、CMOS晶粒202的冗餘或空白區域。同樣地，如第3圖所示，在CMOS晶粒202的未使用區域中設置複數個NOR快閃記憶體206，使得隨著NOR快閃記憶體206的設置，3D NAND快閃記憶體裝置20的儲存空間增大，並且改善3D NAND快閃記憶體裝置20的靈活性。值得注意的是，NOR快閃記憶體206的一數量不限於第2圖和第3圖中所示的四個，根據其它要求可以在CMOS晶粒202的未使用區域中設置其它數量或其他密度的NOR快閃記憶體。
在步驟108中，將NOR快閃記憶體206連接到3D NAND快閃記憶體裝置20的ONFI，其中ONFI是用於對3D NAND快閃記憶體裝置20的腳位分配和命令進行標準化的介面，該ONFI連接3D TLC NAND快閃記憶體204。在步驟110中，連接在NOR快閃記憶體206於ONFI之間的資料通路邏輯單元。在步驟108中將NOR快閃記憶體206的資料通路邏輯單元連接到ONFI之後，可以指示NOR快閃記憶體206根據ONFI的腳位分配和命令來讀/寫資料。亦即，NOR快閃記憶體206可以與3D TLC NAND快閃記憶體204共用ONFI，以經由ONFI讀/寫資料，或者直接經由ONFI讀/寫資料。
由於NOR快閃記憶體206支援隨機讀和隨機寫，因此，在寫入多筆小資料時， 3D NAND快閃記憶體裝置20的讀取時間的性能和寫入時間的性能被改善。另外， 3D NAND快閃記憶體裝置20的控制器被用來執行針對儲存在3D TLC NAND快閃記憶體204中的資料的錯誤控制編碼過程。然而，NOR快閃記憶體206處理的資料沒有錯誤控制編碼（error control coding），這樣降低了3D NAND快閃記憶體裝置20的控制器的複雜性並且改善3D NAND快閃記憶體裝置20的性能。
本發明的設置有NOR快閃記憶體206的3D NAND快閃記憶體裝置20以應用於現有的固態硬碟（SSD）產品中以改善讀/寫性能。另外，透過在CMOS晶粒202的未使用區域中設置NOR快閃記憶體206，也維持了3D NAND快閃記憶體裝置20的製造成本。
如第3圖中所示，本發明採用集成方法10的集成有CMOS晶粒202的3D NAND快閃記憶體裝置20包括3D TLC NAND快閃記憶體204和NOR快閃記憶體206。3D TLC NAND快閃記憶體204設置於CMOS晶粒202上，並且NOR快閃記憶體206設置於CMOS晶粒的未使用區域上。另外，由於NOR快閃記憶體206的資料通路邏輯單元連接到ONFI，ONFI對3D NAND快閃記憶體裝置20的腳位分配和命令進行標準化，以降低3D NAND快閃記憶體裝置20的複雜性降低，並且提高讀/寫性能，而不會增加3D NAND快閃記憶體裝置20的製造成本。
值得注意的是，上述實施例描述本發明的概念，本領域的技術人員可以相應地作出適當修改並且不限於此。
綜而言之，本發明提供了一種3D NAND快閃記憶體裝置及其集成方法，改善了儲存空間、讀/寫性能而不提高製造成本。 以上該僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10:流程 102-112:步驟 20:3D NAND快閃記憶體裝置 202:CMOS晶粒 204:3D TLC NAND快閃記憶體 206:NOR快閃記憶體
第1圖是根據本發明實施例的用於3D NAND快閃記憶體裝置的集成流程之示意圖。 第2圖及第3圖是根據本發明實施例的應用該集成流程的3D NAND快閃記憶體裝置之示意圖。
10:流程
102-112:步驟

Claims (14)

  1. 一種用於3D NAND快閃記憶體裝置的集成方法，包括： 在一互補式金屬氧化物半導體（Complementary Metal-Oxide-Semiconductor，CMOS）晶粒（die）上設置複數個3D三層單元（triple-level cell，TLC）NAND快閃記憶體； 在該3D NAND快閃記憶體裝置的該CMOS晶粒上設置至少一NOR快閃記憶體；以及 將該至少一NOR快閃記憶體連接到該3D NAND快閃記憶體裝置的一開放NAND快閃記憶體介面（Open NAND Flash Interface，ONFI）； 其中該至少一NOR快閃記憶體設置於該CMOS晶粒的一未使用區域上。
  2. 如請求項1所述的集成方法，還包括： 在該3D NAND快閃記憶體裝置的該至少一NOR快閃記憶體與該ONFI之間連接資料通路邏輯（datapath logic）單元。
  3. 如請求項1所述的集成方法，其中該至少一NOR快閃記憶體經由該ONFI讀取和寫入資料。
  4. 如請求項1所述的集成方法，其中該至少一NOR快閃記憶體被配置為執行隨機讀取和隨機寫入。
  5. 如請求項1所述的集成方法，其中該至少一NOR快閃記憶體沒有錯誤控制編碼（error control coding）。
  6. 如請求項1所述的集成方法，其中該至少一NOR快閃記憶體與該3D三層單元（TLC）NAND快閃記憶體共用該ONFI。
  7. 如請求項1所述的集成方法，其中該CMOS晶粒的該未使用區域是由在該複數個3D三層單元（TLC）NAND快閃記憶體中的各個3D三層單元（TLC）NAND快閃記憶體之間的複數個間隙構成。
  8. 一種集成於CMOS晶粒上的3D NAND快閃記憶體裝置，包括： 設置於該CMOS晶粒上的複數個3D三層單元（TLC）NAND快閃記憶體；以及 設置於該CMOS晶粒上的至少一NOR快閃記憶體，該至少一NOR快閃記憶體連接到該3D NAND快閃記憶體的開放NAND快閃記憶體介面（ONFI）； 其中該至少一NOR快閃記憶體設置於該CMOS晶粒的一未使用區域上。
  9. 如請求項8所述的3D NAND快閃記憶體裝置，其中在該3D NAND快閃記憶體的該至少一NOR快閃記憶體與該ONFI之間連接資料通路邏輯單元。
  10. 如請求項8所述的3D NAND快閃記憶體裝置，其中該至少一NOR快閃記憶體經由該ONFI讀取和寫入資料。
  11. 如請求項8所述的3D NAND快閃記憶體裝置，其中該至少一NOR快閃記憶體被配置為執行隨機讀取和隨機寫入。
  12. 如請求項8所述的3D NAND快閃記憶體裝置，其中該至少一NOR快閃記憶體沒有錯誤控制編碼。
  13. 如請求項8所述的3D NAND快閃記憶體裝置，其中該至少一NOR快閃記憶體與該3D三層單元（TLC）NAND快閃記憶體共用該ONFI。
  14. 如請求項8所述的3D NAND快閃記憶體裝置，其中該CMOS晶粒的該未使用區域是由該複數個3D三層單元（TLC）NAND快閃記憶體中的各個3D三層單元（TLC）NAND快閃記憶體之間的複數個間隙構成。
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