WO2022206495A1 - 三维存储器件及其制造方法、以及三维存储器 - Google Patents

三维存储器件及其制造方法、以及三维存储器 Download PDF

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WO2022206495A1
WO2022206495A1 PCT/CN2022/082306 CN2022082306W WO2022206495A1 WO 2022206495 A1 WO2022206495 A1 WO 2022206495A1 CN 2022082306 W CN2022082306 W CN 2022082306W WO 2022206495 A1 WO2022206495 A1 WO 2022206495A1
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memory
storage unit
contacts
cmos
memory cell
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PCT/CN2022/082306
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English (en)
French (fr)
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胡思平
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长江存储科技有限责任公司
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Priority to EP22778678.7A priority Critical patent/EP4266369A1/en
Priority to JP2023546108A priority patent/JP2024504487A/ja
Priority to KR1020237023075A priority patent/KR20230113398A/ko
Priority to BR112023012456A priority patent/BR112023012456A2/pt
Publication of WO2022206495A1 publication Critical patent/WO2022206495A1/zh
Priority to US18/463,900 priority patent/US20230422528A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/145—Read-only memory [ROM]
    • H01L2924/1451—EPROM
    • H01L2924/14511—EEPROM
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of semiconductor devices, and in particular, to a three-dimensional memory device, a method for manufacturing the same, and a three-dimensional memory including the three-dimensional memory device.
  • 3D NAND memory is an emerging type of three-dimensional memory that solves the limited storage capacity of 2D or planar NAND memory by vertically stacking multiple data storage layers in memory chips.
  • the storage chip includes a CMOS device and a storage array device with a stepped structure.
  • the CMOS device and the storage array device are respectively formed on a substrate, and the CMOS device and the storage array device are electrically connected to each other on the side away from the respective substrates.
  • An aspect of the present disclosure provides a three-dimensional memory device including at least two memory cells stacked in sequence, the at least two memory cells including a first memory cell and at least one second memory cell stacked on the first memory cell , each storage unit includes:
  • a memory array device and a CMOS device, the memory array device and the CMOS device are stacked and electrically connected to each other;
  • a first group of contacts arranged on the side of the storage array device away from the CMOS device, and electrically connected to the CMOS device;
  • the second storage unit further includes a second group of contacts, and the second group of contacts is arranged on a side of the CMOS device of the second storage unit away from the storage array device of the second storage unit, and electrically connected to the CMOS device of the second storage unit;
  • the memory array device of the first memory cell is bonded to the CMOS device of the adjacent second memory cell, and the first set of contacts of the first memory cell is connected to the second set of contacts of the adjacent second memory cell corresponding electrical connection;
  • the second storage unit is an outer second storage unit stacked on the first storage unit, and the first group of contacts of the outer second storage unit is used for connect external devices;
  • the multiple second storage units are stacked on the first storage unit in sequence, and the adjacent two second storage units are adjacent to the first storage unit.
  • the first group of contacts of the second storage unit is electrically connected to the second group of contacts of the second storage unit farthest from the first storage unit, and the second storage unit farthest from the first storage unit in the stacking direction It is defined as the outer layer second storage unit, and the first group of contacts of the outer layer second storage unit is used to connect external devices.
  • Another aspect of the present disclosure also provides a method for manufacturing a three-dimensional memory device, comprising the following steps:
  • a first storage unit and a second storage unit are provided, each of the first storage unit and the second storage unit includes a first set of contacts, and a storage array device and a CMOS device that are arranged in a stack and are electrically connected to each other, wherein the The first group of contacts is arranged on a side of the storage array device away from the CMOS device and is electrically connected to the CMOS device;
  • a second set of contacts is formed on a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, wherein the second set of contacts is connected to the CMOS device of the second memory cell electrical connection;
  • CMOS devices of the memory cells are bonded to electrically connect the first set of contacts of the first memory cell with the second set of contacts of the second memory cell correspondingly.
  • a three-dimensional memory device including the above-mentioned three-dimensional memory device.
  • FIG. 1 is a schematic cross-sectional view of a three-dimensional memory device provided by one embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional view of a three-dimensional memory device provided by another embodiment of the present disclosure.
  • FIG. 3 is a flowchart of a method for manufacturing a three-dimensional memory device provided by the present disclosure.
  • FIG. 4 to 7 are schematic diagrams of a formation process of a memory cell of a three-dimensional memory device, wherein FIG. 4 is a schematic cross-sectional view of a memory array device and a CMOS device;
  • FIG. 5 is a schematic cross-sectional view of the memory array device and the CMOS device shown in FIG. 4 after bonding;
  • FIG. 6 is a schematic cross-sectional view of the memory array device and the CMOS device shown in FIG. 5 after the array substrate is thinned;
  • FIG. 7 is a schematic cross-sectional view of a side of the memory array device shown in FIG. 6 facing away from the CMOS device where a first group of contacts are formed and the first bonding layer is covered.
  • FIG. 8 is a schematic cross-sectional view of the second memory unit shown in FIG. 7 after the side of the memory array device facing away from the CMOS device is attached to the carrier sheet and turned over.
  • FIG. 9 is a schematic cross-sectional view of the second memory cell shown in FIG. 8 after the CMOS substrate is thinned.
  • FIG. 10 is a schematic cross-sectional view of the second memory unit shown in FIG. 9 with a conductive channel formed on the CMOS substrate and the side of the CMOS substrate facing away from the memory array device sequentially covering the first insulating layer and the second insulating layer.
  • FIG. 11 is a schematic cross-sectional view of the second memory cell shown in FIG. 10 with a second set of contacts formed on the second insulating layer and covering the second bonding layer.
  • FIG. 12 is a schematic cross-sectional view of the second memory cell shown in FIG. 11 after being turned over and bonded to the first memory cell.
  • FIG. 13 is a schematic cross-sectional view of the first storage unit and the second storage unit shown in FIG. 12 when the carrier sheet is removed in the second storage unit and the first bonding layer thereof is thinned to expose the first set of contacts.
  • the second storage unit 200 The second storage unit 200
  • the first bonding layer 42 is the first bonding layer 42
  • the present disclosure provides a three-dimensional memory device including at least two memory cells stacked in sequence, the at least two memory cells including a first memory cell 100 and a memory cell stacked on the first memory cell 100 At least one second storage unit 200 .
  • the number of the second storage unit 200 is one, and the first storage unit 100 and one second storage unit 200 are stacked to form a three-dimensional storage device 1000 ; as shown in FIG.
  • the number of the second storage units 200 is multiple (two or more), the multiple second storage units 200 are stacked on the first storage unit 100 in sequence, and the first storage unit 100 Stacked with a plurality of second memory cells 200 to form a three-dimensional memory device 1000b.
  • the three-dimensional memory device provided by the present disclosure is formed by stacking at least two memory cells, so the memory density is high.
  • each memory cell includes a memory array device 10 and a CMOS device 20 that are stacked and electrically connected to each other, and the memory array device 10 is disposed away from the CMOS device 20 . one side of the first set of contacts 40 that are electrically connected to the CMOS device 20 .
  • the memory array device 10 and the CMOS device 20 of each memory cell may be connected by bonding to realize electrical connection therebetween.
  • the memory array device 10 and the CMOS device 20 of each memory cell may also be electrically connected in other ways, including but not limited to wire connection, conductive contact connection, plug connection, and the like.
  • the storage array device 10 includes an array substrate 11 and a storage array disposed on the side of the array substrate 11 close to the CMOS device 20 .
  • the storage array has a data storage function. Several memory strings of several memory layers 13 .
  • the first set of contacts 40 of each memory cell is provided on the side of the array substrate 11 facing away from the CMOS device 20 .
  • the CMOS device 20 includes a CMOS substrate 21 and a CMOS circuit disposed on the side of the CMOS substrate 21 close to the storage array device 10 , and the CMOS circuit is used to implement logic control of the storage array device 10 , reading of stored data, etc. .
  • each memory cell further includes an interconnection channel 30 , and the interconnection channel 30 is respectively connected with the first group of contacts 40 of the memory cell and the CMOS device 20 . Electrical connections are made such that the first set of contacts 40 are electrically connected to the CMOS device 20 through the interconnect vias 30 .
  • the interconnection channel 30 is disposed in the memory array device 10 and the CMOS device 20 of the memory cell, and is perpendicular to the array substrate 11 and the CMOS substrate 21 .
  • the interconnection channel 30 may not be perpendicular to the array substrate 11 and the CMOS substrate 21 , but may also be perpendicular to the array substrate 11 or perpendicular to the CMOS substrate 21 .
  • each second memory cell 200 further includes a second set of contacts 50 .
  • the second set of contacts 50 are provided on a side of the CMOS device 20 of the second memory cell 200 facing away from the memory array device 10 of the second memory cell 200 , and are electrically connected to the CMOS device 20 of the second memory cell 200 . connect.
  • the memory array device 10 of the first memory cell 100 is bonded to the CMOS device 20 of the adjacent second memory cell 200 , and the first memory cell 100
  • One group of contacts 40 is electrically connected to the second group of contacts 50 of the adjacent second storage unit 200, so that the first storage unit 100 and the adjacent second storage unit 200 pass through the corresponding first group of contacts 40,
  • the second set of contacts 50 make electrical connections.
  • the second storage unit 200 when there is only one second storage unit 200 in the three-dimensional storage device 1000 , the second storage unit 200 is an outer layer stacked on the first storage unit 100
  • the first group of contacts 40 of the outer second storage unit 200 are used to connect external devices (such as control devices or drive circuits, etc.), so as to realize the functions of driving and controlling the three-dimensional storage device 1000 . .
  • the multiple second storage units 200 are stacked on the first storage unit 100 in sequence, and the corresponding Among the two adjacent second memory cells 200 , the first group of contacts 40 of the second memory cell 200 close to the first memory cell 100 corresponds to the second group of contacts 50 of the second memory cell 200 far from the first memory cell 100 Electrical connection, so that the two adjacent second storage units 200 are electrically connected through the corresponding first group of contacts 40 and the second group of contacts 50, so that the first storage unit 100 and the first storage unit 100 are sequentially stacked on the first storage unit 100 The plurality of second storage units 200 are electrically connected.
  • the second storage unit 200 farthest from the first storage unit 100 in the stacking direction is the outer second storage unit 200 stacked on the first storage unit 100, and the first outer layer of the second storage unit 200
  • the group contacts 40 are used to connect external devices (eg, control devices or driving circuits, etc.), so as to realize functions such as driving and controlling the three-dimensional storage device 1000b. It can be understood that, compared with the three-dimensional memory device 1000, the number of stacked memory cells in the three-dimensional memory device 1000b is larger, so the storage density of the three-dimensional memory device 1000b is higher.
  • the electrical connection between the at least two memory cells is realized, that is, the electrical connection between the at least two memory cells is realized.
  • a three-dimensional memory device with higher storage density can be formed, so that it is not necessary to stack too many memory layers 13 in the memory array device 10 of each memory cell, so that the area of the array substrate 11 of each memory cell is not too large, thereby It is beneficial to arrange the array substrate 11 and the CMOS substrate 21 of each storage unit with an appropriate area ratio, thereby reducing the unused space in each storage unit and improving the space utilization rate of the three-dimensional storage device.
  • both the array substrate 11 and the CMOS substrate 21 may be made of semiconductor materials or non-conductive materials, and the semiconductor materials include but are not limited to silicon, germanium, silicon germanium, gallium arsenide, silicon-on-insulator, germanium-on-insulator or In any suitable combination thereof, the non-conductive material includes, but is not limited to, glass, plastic, or sapphire.
  • the array substrate 11 and the CMOS substrate 21 are both silicon substrates. Except for the CMOS substrate 21 of the first storage unit 100, the array substrate 11 and the CMOS substrate 21 of any storage unit in the three-dimensional storage device can be thinned to reduce the volume of the three-dimensional storage device. Means of thinning include, but are not limited to, mechanical grinding, wet/dry etching, chemical mechanical grinding, or any combination thereof.
  • each memory array device 10 a plurality of memory layers 13 are stacked on one side of the array substrate 11 in a stepped structure, and a plurality of memory strings (eg, NAND strings) pass through and communicate with the plurality of memory layers 13, so that the plurality of storage strings and the plurality of storage layers 13 together form a storage array with a storage function.
  • a plurality of memory strings eg, NAND strings
  • each storage layer 13 extends in a lateral direction parallel to the surface of the array substrate 11 ; in a direction gradually away from and perpendicular to the array substrate 11 , each adjacent two storage layers in the plurality of storage layers 13 13 is offset by the same distance and is reduced by the same extension distance in the lateral direction. It can be understood that, one end of each adjacent two storage layers 13 in the lateral direction may be flush, and the other end may be reduced by the same distance, or the two ends in the lateral direction may be respectively reduced by the same distance. As shown in FIG. 1 and FIG. 2 , in some embodiments of the present disclosure, both ends of each adjacent two storage layers 13 in the lateral direction are respectively reduced by the same distance.
  • each storage layer 13 may include one or more conductor/dielectric layer pairs, each conductor/dielectric layer pair includes a conductor layer and a dielectric layer, and the specific structures of the conductor layer and the dielectric layer, The functions and materials are the same as the structures, functions and materials of the conductor layer and the dielectric layer commonly used in the prior art, so they will not be repeated here.
  • Each of the memory strings includes a channel structure extending in a direction perpendicular to the array substrate 11 and passing through the plurality of memory layers 13, the channel structure including being filled with a semiconductor material (as a semiconductor channel) and a dielectric material ( as a channel hole for the memory film).
  • the storage film may include a tunnel layer, a charge trapping/storage layer, and a blocking layer, and the semiconductor channel, the tunneling layer, the charge trapping/storage layer, and the blocking layer are formed along the lines of the storage strings. The centers are arranged one after the other in the outward direction. It should be noted that the specific structure, function and material of the storage string are the same as the structure, function and material of the storage string commonly used in the prior art, and therefore will not be repeated here.
  • the respective storage array devices 10 of the first storage unit 100 and the second storage unit 200 include several storage layers 13 .
  • the first memory cell The respective storage array devices 10 of 100 and the second storage unit 200 include a predetermined number of storage layers 13, and the predetermined number of layers is an integer greater than 0 and less than 500, such as 32 layers, 64 layers, and 96 layers. Or 128 floors.
  • the number of layers of the storage layers 13 in the respective storage array devices 10 of the first storage unit 100 and the second storage unit 200 may be the same or different. In some embodiments, the number of layers of the memory layers 13 in the memory array device 10 of the first memory unit 100 and the second memory unit 200 may be the same, so that the first memory unit 100 and the second memory unit 200 can be mass-produced in the same process steps.
  • the memory array device 10 and the CMOS device 20 further include other elements, such as a stack layer covering the memory array or the CMOS circuit, and disposed on the inner side of the stack layer.
  • the bonding structure on the surface including but not limited to conductive structures such as wires, plugs, solder bumps or pads), and passing through the stacked layers and electrically connected to the bonding structure and the memory array or the CMOS circuit respectively A number of interconnected conductive channels, etc., wherein the stacked layer at least includes an insulating layer covering the storage array or the CMOS circuit, and the specific structures and functions of the storage array device 10 and the CMOS device 20 are the same as those in the prior art.
  • the structure and function of the storage array device and the CMOS device are basically the same, and are not related to the improvement and creation of the present disclosure, so they will not be repeated here.
  • the interconnection channel 30 includes a first interconnection subchannel 31 , a second interconnection subchannel 32 , and a first interconnection subchannel 31 and a second interconnection subchannel 32 electrically connected to the The interconnect structure 33 between the second interconnect sub-channels 32 .
  • the first interconnection sub-channel 31 is provided in the memory array device 10 and is located on the side of the memory array device 10 where the memory array is provided, and the first interconnection sub-channel 31 penetrates through the stacked layers of the memory array device 10;
  • the second interconnection sub-channel 32 is disposed in the CMOS device 20 and is located on the side of the CMOS device 20 where the CMOS circuit is arranged.
  • the second interconnection sub-channel 32 penetrates through the stacked layers of the CMOS device 20 , wherein the second interconnection sub-channel 32 is connected to the CMOS circuit.
  • first interconnection sub-channels 31 correspond to each other, and one end of the second interconnection sub-channel 32 away from the first interconnection sub-channel 31 is electrically connected to the CMOS circuit. It should be noted that the first interconnection sub-channel 31 and the second interconnection sub-channel 32 may be formed by common means in the prior art.
  • the memory array device 10 and the second interconnection sub-channel 32 may be formed first Deep etching is performed on the respective stacked layers of the CMOS device 20 to form filling channels penetrating the stacked layers, and then conductive materials are filled into the filling channels to form first interconnection sub-channels 31 and second interconnection sub-channels, respectively Channel 32, the conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, polysilicon, suicide, or any combination thereof.
  • the number of the first interconnection sub-channel 31 and the second interconnection sub-channel 32 may be set to one or more, as long as the number of the two is correspondingly equal, which is not limited.
  • the interconnection structure 33 includes a first interconnection contact and a second interconnection contact, the first interconnection contact is provided on the inner side (ie the side close to the CMOS device) surface of the stacked layers of the memory array device 10, and Correspondingly and electrically connected to the first interconnection sub-channel 31, the second interconnection contact is provided on the inner surface of the stack layer of the CMOS device 20 (that is, the side close to the memory array device), and is connected to the second interconnection sub-channel. 32 corresponds to the electrical connection.
  • the first interconnection contact and the second interconnection contact include, but are not limited to, conductive structures such as wires, plugs, solder bumps, or pads, and the structures of the two may be the same or different. As shown in FIGS.
  • the first interconnection contacts are a plurality of solder bumps, and the plurality of solder bumps and the first interconnection sub-channels 31 are equal in number and in a one-to-one correspondence Electrical connection;
  • the second interconnection contact is a pad, one side surface of the pad is electrically connected to the second interconnection sub-channel 32 correspondingly, and the other side surface of the pad is provided with a number of solder feet, The plurality of solder feet correspond to the plurality of solder bumps of the first interconnection contact in one-to-one correspondence.
  • the first interconnection contact and the second interconnection contact are bonded together to form the interconnection structure 33, so that the interconnection structure 33 is formed.
  • the first interconnection sub-channel 31 and the second interconnection sub-channel 32 are electrically connected correspondingly through the interconnection structure 33, so as to constitute the interconnection channel 30 of the memory cell.
  • the first group of contacts 40 are disposed on the outer side of the array substrate 11 (ie, on the side away from the memory array), and the array substrate 11 is located on the corresponding side of the memory array.
  • a plurality of first conductive channels 41 are disposed at the positions of the first interconnection sub-channels 31 in the array device 10 , and each of the first conductive channels 41 penetrates through opposite sides of the array substrate 11 and is connected to a corresponding first interconnection
  • the sub-channels 31 are electrically connected such that the first set of contacts 40 are electrically connected to the first interconnecting sub-channels 31 through the first conductive channels 41 .
  • the first group of contacts 40 includes, but is not limited to, conductive structures such as wires, plugs, solder bumps, or pads.
  • the first group of contacts 40 are pads, and the pads are connected to the first The conductive channels 41 are electrically connected.
  • the outer surface of the array substrate 11 is also covered with a first bonding layer 42 , and one end of the first conductive channel 41 away from the first interconnection sub-channel 31 and the first set of contacts 40 are embedded in the first bonding layer 42 .
  • the first bonding layer 42 may be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.
  • the first bonding layer 42 includes at least one dielectric layer made of a dielectric material, and the dielectric material includes, but is not limited to, silicon oxide or silicon nitride, which is not limited thereto.
  • the first conductive channel 41 may be formed by common means such as TSV technology.
  • deep etching is first performed at positions of the first bonding layer 42 and the array substrate 11 corresponding to several first interconnection sub-channels 31 to form a plurality of first bonding layers 42 and the array substrate 11 .
  • vertical channels each of the first vertical channels exposes at least a part of a corresponding first interconnect sub-channel 31 , and then fills the first vertical channels with conductive substances until the conductive substances partially exceed the surface of the array substrate 11 .
  • a first conductive channel 41 in contact with the first interconnection sub-channel 31 can be formed, and one end of the first conductive channel 41 away from the first interconnection sub-channel 31 is located in the first bonding layer 42 .
  • the first bonding layer 42 By covering the first bonding layer 42 on the outer surface of the array substrate 11 , leakage of the conductive material in the first vertical channel during the process of the first conductive channel 41 can be prevented, thereby avoiding pollution to other processes.
  • the positions of the first bonding layer 42 corresponding to the first conductive channels 41 are continued to be etched to form a plurality of first conductive channels 41 for exposing the first conductive channels 41 away from the first interconnection.
  • One end of the channel 31 has an opening, and then a first group of contacts 40 (ie, pads) are arranged in the opening, so that the first group of contacts 40 are electrically connected to a plurality of first conductive channels 41 correspondingly.
  • the openings may be refilled with the dielectric material of the first bonding layer 42 to cover the first set of contacts
  • the contacts 40 can prevent the first group of contacts 40 from being exposed, thereby preventing the first group of contacts 40 from being damaged before they are bonded and connected with the corresponding second group of contacts 50, which is beneficial to improve the relationship between the first group of contacts 40 and the corresponding second group of contacts 50.
  • the reliability of the bond connection of the second set of contacts 50 may also be exposed.
  • first bonding layer 42 when the first set of contacts 40 within the openings of the first bonding layer 42 are covered with a dielectric material, it is required before the first set of contacts 40 are bonded to the corresponding second set of contacts 50 .
  • the first bonding layer 42 is thinned or etched to remove the dielectric material, exposing the first set of contacts 40 within the openings.
  • the second group of contacts 50 of the second memory cell 200 are disposed on the outer side of the CMOS substrate 21 (ie, the side away from the CMOS circuit), and the CMOS substrate
  • the bottom 21 is provided with a plurality of second conductive channels 60 at positions corresponding to the second interconnection sub-channels 32 in the CMOS device 20 where the bottom 21 is located.
  • the second set of contacts 50 and the CMOS devices of the CMOS device 20 are electrically connected such that the second set of contacts 50 are electrically connected to the CMOS circuits of the CMOS device 20 through the second conductive channel 60 .
  • the second conductive channel 60 may not correspond to the second interconnection sub-channel 32 , as long as the second conductive channel 60 is electrically connected to the CMOS circuit of the CMOS device 20 .
  • the second group of contacts 50 includes, but is not limited to, conductive structures such as wires, plugs, solder bumps, or pads.
  • the second group of contacts 50 is a plurality of solder bumps, and the plurality of solder bumps are connected to a plurality of solder bumps.
  • the plurality of second conductive channels 60 are electrically connected in one-to-one correspondence.
  • the outer surface of the CMOS substrate 21 of the second memory cell 200 is covered with a second bonding layer 52 , one end of the second conductive channel 60 away from the second interconnection sub-channel 32 and the second set of contacts 50 are embedded in the second bonding layer in layer 52.
  • the second bonding layer 52 may also be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof;
  • the second bonding layer 52 also includes at least one dielectric layer made of a dielectric material, and the dielectric material includes, but is not limited to, silicon oxide or silicon nitride, which is not limited thereto.
  • the formation process of the second conductive channel 60 and the first conductive channel 41 is basically the same.
  • the second bonding layer 52 and the CMOS substrate 21 may first correspond to several second interconnections
  • the positions of the sub-channels 32 are etched back to form a plurality of second vertical channels penetrating the second bonding layer 52 and the CMOS substrate 21 , each of the second vertical channels exposing at least a corresponding one of the second interconnecting sub-channels 32 and then fill the second vertical channel with conductive material until the conductive material partially exceeds the outer side of the CMOS substrate 21, so that the second conductive channel 60 in contact with the second interconnection sub-channel 32 can be formed, so that the first conductive material
  • Two conductive channels 60 are electrically connected to the CMOS circuit, and one end of the second conductive channel 60 away from the second interconnection sub-channel 32 is located in the second bonding layer 52 .
  • the conductive substances filled in the second vertical channel and the first vertical channel include but are not limited to tungsten, copper, aluminum, polysilicon, silicide or any combination thereof, and the first vertical channel and the second vertical channel
  • the conductive substances filled in the vertical channels may be the same or different.
  • the processes of the second group of contacts 50 and the first group of contacts 40 are different, and the difference is that after the second conductive channel 60 is formed, it can be directly A solder bump is disposed in each of the second vertical channels of the second bonding layer 52 , and a plurality of solder bumps in the second vertical channels constitute the second group of contacts 50 .
  • the second set of contacts 50 may be covered or exposed.
  • the second group of contacts 50 may be covered to prevent the second group of contacts 50 from being damaged before being keyed and connected with the corresponding first group of contacts 40, which is also beneficial to improve the first group of contacts.
  • the reliability of the bond connection between the point 40 and the corresponding second set of contacts 50 is improved. It can be understood that when the solder bumps in each of the second vertical channels of the second bonding layer 52 are covered by the dielectric material of the second bonding layer 52 (ie, the second set of contacts 50 are covered), in the first Before the set of contacts 40 are bonded to the corresponding second set of contacts 50, the second bonding layer 52 needs to be thinned or etched to remove the dielectric material in each of the second vertical channels, so that each of the second The solder bumps in the second vertical channel are exposed, even if the second group of contacts 50 are exposed, so as to facilitate bonding with the corresponding first group of contacts 40 .
  • the three-dimensional memory device further includes an isolation layer 300 and an array pad 400 embedded in the isolation layer 300 .
  • the isolation layer 300 covers the side of the outer second memory cell 200 facing away from the first memory cell 100 and the first set of contacts 40 of the outer second memory cell 200 .
  • the isolation layer 300 is provided with an accommodating cavity at a position corresponding to the first group of contacts 40 of the outer second storage unit 200 , and the accommodating cavity corresponds to at least a part of the first group of contacts 40 .
  • the array pad 400 is arranged in the accommodating cavity of the isolation layer 300 and is electrically connected to the first group of contacts 40 of the outer second storage unit 200 , and the three-dimensional memory device is electrically connected to the aforementioned external through the array pad 400 . device.
  • the accommodating cavity of the isolation layer 300 can be formed by common means such as etching, which will not be repeated here; the array pad 400 and the aforementioned solder bumps, pads, etc. can be prepared by common means in the prior art, Therefore, I will not go into details.
  • the isolation layer 300 can also be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition, physical vapor deposition , atomic layer deposition, or any combination thereof; the isolation layer 300 may also include at least one dielectric layer made of a dielectric material, the dielectric material including but not limited to silicon oxide or silicon nitride, which is not limited.
  • the accommodating cavity of the isolation layer 300 may be a cavity with one end facing the outer second storage unit 200, so that the array pads 400 are covered by the isolation layer 300 before connecting the external devices, which is beneficial to protect the array soldering.
  • the position of the isolation layer 300 corresponding to the accommodating cavity needs to be thinned or etched to expose the array pads 400 .
  • the accommodating cavity of the isolation layer 300 may also have a cavity structure with two ends open, so that the array pad 400 is exposed so as to be directly electrically connected to the external device.
  • the isolation layer 300 covers the outer side of the first bonding layer 42 of the outermost second memory cell 200 . It can be understood that both the isolation layer 300 and the first bonding layer 42 are made of dielectric materials, therefore, the materials of the isolation layer 300 and the first bonding layer 42 may be the same or different. That is to say, the isolation layer 300 and the first bonding layer 42 may be formed in different thin film deposition processes, or may be formed in the same thin film deposition process.
  • the isolation layer 300 and the first bonding layer 42 are formed in different thin film deposition processes, so that the first group of contacts 40 and the array pads 400 can be arranged in stages in different thin film deposition processes, and the operation is convenient Furthermore, the first bonding layer 42 and the isolation layer 300 are formed in stages. When the first bonding layer 42 and the isolation layer 300 are etched respectively, the etching depth is small, which is beneficial to improve the etching efficiency and accuracy.
  • the three-dimensional memory device further includes a protective layer 500 stacked on the outer surface of the isolation layer 300 , and the protective layer 500 covers the isolation layer 300 and corresponds to the array pad.
  • the position of 400 is provided with an opening, and at least part of the array pad 400 is exposed through the opening for connecting the external device.
  • the protective layer 500 can also cover the array pads 400 to protect the array pads 400, but when the array pads 400 and the external devices are electrically connected, the protective layer 500 needs to correspond to the array pads 400.
  • the locations are thinned or etched to expose the array pads 400 .
  • Covering the protective layer 500 on the isolation layer 300 can protect the isolation layer 300 and prevent the isolation layer 300 from being damaged, thereby preventing the array pads 400 from loosening due to the damage of the isolation layer 300 and ensuring the connection reliability of the array pads 400 .
  • the protective layer 500 may be made of materials such as silicon nitride or silicon oxide, and openings are opened by common means such as etching, which will not be repeated here.
  • the present disclosure further provides a method for manufacturing the above-mentioned three-dimensional memory device, and the method for manufacturing the three-dimensional memory device includes the following steps:
  • Step S1 providing a first storage unit and a second storage unit, the first storage unit and the second storage unit each including a first group of contacts, and a storage array device and a CMOS device that are stacked and electrically connected to each other, wherein, The first set of contacts is arranged on a side of the storage array device away from the CMOS device and is electrically connected to the CMOS device.
  • the manufacturing process of the memory cell is as follows:
  • the memory array device 10 and the CMOS device 20 are provided.
  • the memory array device 10 includes an array substrate 11 , a memory array disposed inside the array substrate 11 (ie, a side close to the CMOS device 20 ), and first interconnectors disposed in the memory array The channel 31, and the first interconnection contact 331 disposed on the inner surface of the memory array device 10 and electrically connected to the first interconnection sub-channel 31, wherein the memory array includes a plurality of memory layers 13 in a stepped structure and through and connect several storage strings of the several storage layers 13 in parallel; as shown in FIG.
  • the CMOS device 20 includes a CMOS substrate 21 , a CMOS circuit arranged inside the CMOS substrate 21 (ie, a side close to the storage array device 10 ), A second interconnection sub-channel 32 disposed on one side of the CMOS circuit and electrically connected to the CMOS circuit, and a second interconnection sub-channel 32 disposed on the inner surface of the CMOS device 20 and electrically connected to the second interconnection sub-channel 32 .
  • Connection point 332 .
  • the array substrate 11 the plurality of memory layers 13 , the plurality of memory strings, the CMOS substrate 21 , the first interconnection sub-channel 31 , the second interconnection sub-channel 32 , and the first interconnection contact
  • the storage array device 10 and the CMOS device 20 respectively include other elements, and the specific structures and functions of the two are basically the same as those of the existing storage array device and CMOS device. It has nothing to do with creation, so I won't go into details here.
  • the memory array device 10 and the CMOS device 20 are bonded face-to-face. As shown in FIG. 5 , after the memory array device 10 and the CMOS device 20 are aligned and bonded, the aforementioned first interconnection contact 331 and second interconnection contact 332 (as shown in FIG. 4 ) are bonded together to form an interconnection.
  • the interconnection structure 33 makes the aforementioned first interconnection sub-channel 31 and the second interconnection sub-channel 32 correspondingly electrically connected through the interconnection structure 33, so as to constitute the interconnection channel 30 of the storage unit, and the interconnection channel 30 is respectively connected to the
  • the first set of contacts 40 of the memory cell and the CMOS device 20 are electrically connected so that the first set of contacts 40 are electrically connected to the CMOS device 20 through the interconnection channel 30 .
  • the outer side of the array substrate 11 of the memory array device 10 is thinned.
  • Means of thinning include, but are not limited to, mechanical grinding, wet/dry etching, chemical mechanical grinding, or any combination thereof.
  • a first group of contacts 40 is formed on the outside of the memory array device 10 , so that the first group of contacts 40 are electrically connected to the first interconnection sub-channels 31 .
  • the outer surface of the array substrate 11 is covered with a first bonding layer 42 , which can be formed through the array substrate 11 and interconnected with the first sub-channel 31 by common technical means.
  • the electrically connected first conductive channel 41 , the end of the first conductive channel 41 away from the first interconnection sub-channel 31 and the first group of contacts 40 are embedded in the first bonding layer 42 , and the first group of contacts 40 pass through the first group of contacts 40 .
  • a conductive channel 41 is electrically connected to the first interconnection sub-channel 31 .
  • first bonding layer 42 and the first conductive channel 41 reference may be made to the corresponding content in the above-mentioned three-dimensional memory device, which will not be repeated here.
  • the first storage unit 100 and the parts of the second storage unit 200 that are the same as the first storage unit 100 can be prepared.
  • Step S2 thinning the side of the CMOS device of the second storage unit away from the storage array device of the second storage unit. That is, the side of the CMOS substrate of the second memory cell facing away from the CMOS circuit is thinned, and the thinning means includes but not limited to mechanical grinding, wet/dry etching, chemical mechanical grinding or any combination thereof.
  • the manufacturing method of the three-dimensional memory device before step S2, further includes the steps of: providing a carrier sheet, and attaching the carrier sheet to the The side of the storage array device of the second storage unit facing away from the CMOS device of the second storage unit, so that the carrier sheet covers the storage array device of the second storage unit carried away from the CMOS device of the second storage unit. one side and the first set of contacts of the second storage unit.
  • the second storage unit 200 is first turned over so that the storage array device 10 of the second storage unit 200 is at the bottom, and then the carrier sheet 600 is attached to the second storage unit
  • the outer side of the storage array device 10 of the second storage unit 200 ie, the side away from the CMOS device 20 of the second storage unit 200 ), so that the carrier sheet 600 covers the outer side of the storage array device 10 of the second storage unit 200 and the first set of contacts.
  • the CMOS substrate 21 of the second memory cell 200 is finally thinned.
  • the carrier sheet 600 By attaching the carrier sheet 600 to the outer side of the storage array device 10 of the second storage unit 200 , it can play the role of supporting the second storage unit 200 , which is beneficial to reduce or even avoid the second storage unit 200 being transported or the CMOS substrate 21 Deformation occurs during thinning.
  • the carrier sheet 600 may be made of glass, sapphire or semiconductor material, which is not limited.
  • attaching the carrier sheet 600 to the outside of the storage array device 10 of the second storage unit 200 further includes the following steps:
  • the side of the carrier sheet 600 facing the second storage unit 200 and the outer side of the memory array device 10 of the second storage unit 200 are coated with bonding glue, so as to enhance the bonding between the carrier sheet 600 and the second storage unit 200 .
  • Adhesion between the outer sides of the memory array device 10 are examples of bonding glue, so as to enhance the bonding between the carrier sheet 600 and the second storage unit 200 .
  • the carrier sheet 600 is bonded to the outer side of the memory array device 10 of the second memory cell 200 through a temporary bonding process or a permanent bonding process.
  • the temporary bonding process refers to bonding the carrier sheet 600 to the outside of the storage array device 10 of the second memory unit 200 , and the carrier sheet 600 can be easily removed from the outside of the storage array device 10 when needed.
  • the adopted process means that the removal of the carrier sheet 600 is relatively easy; the permanent bonding process refers to bonding the carrier sheet 600 to the outer side of the storage array device 10 of the second storage unit 200, but it needs to be supplemented with a larger Only external force can be used to remove the carrier sheet 600 from the outside of the storage array device 10 , and the bonding connection between the carrier sheet 600 and the storage array device 10 of the second memory unit 200 is relatively firm.
  • the outer side of the memory array device 10 of the second memory unit 200 is covered with the first bonding layer 42 . Therefore, in some embodiments, the carrier sheet 600 may be bonded to the first bonding layer 42 . An outer side of the bonding layer 42 .
  • Step S3 forming a second group of contacts on the side of the CMOS device of the second storage unit away from the storage array device of the second storage unit, wherein the second group of contacts and the second storage unit CMOS devices are electrically connected.
  • step S3 of the method for manufacturing a three-dimensional memory device includes the following steps:
  • a through hole (ie, the aforementioned second vertical channel) is formed on the CMOS substrate 21 of the second memory cell 200 through the CMOS substrate 21 , and the through hole exposes at least a part of the interconnection channel 30 of the second memory cell 200 ( That is, at least a part of the aforementioned second interconnection sub-channel 32);
  • a conductive medium is filled in the through hole to form a conductive channel (ie, the aforementioned second conductive channel 60 ), and the conductive channel is electrically connected to the interconnection channel 30 of the second memory unit 200 ;
  • the second group of contacts 50 of the second memory unit 200 is formed from one end of the conductive channel away from the interconnection channel 30 of the second memory unit 200 (ie, the end of the second conductive channel 60 away from the second interconnection sub-channel 32 ), The second set of contacts 50 are electrically connected to the interconnection channels 30 of the second memory cell 200 through the conductive channels.
  • the surface of the outer side (ie the side away from the CMOS circuit) of the CMOS substrate 21 of the second memory unit 200 is first covered with a second bonding layer 52, and then a second conductive channel 60 that penetrates the CMOS substrate 21 and is electrically connected to the second interconnection sub-channel 32 can be formed by common technical means.
  • the second conductive channel 60 is away from one end of the second interconnection sub-channel 32 and the The two sets of contacts 50 are both embedded in the second bonding layer 52 .
  • the second set of contacts 50 are electrically connected to the CMOS circuit of the CMOS device 20 through the second conductive channel 60 , and are also electrically connected to the second interconnection of the interconnection channel 30 . Connect sub-channel 32. Similarly, for the specific features, functions, or formation processes of the second bonding layer 52 and the second conductive channel 60, reference may be made to the corresponding contents in the above-mentioned three-dimensional memory device, which will not be repeated here.
  • the method for fabricating the three-dimensional memory device further includes: Step S4: stacking the second storage unit on the side of the storage array device of the first storage unit away from the CMOS device of the first storage unit, and connecting the storage array device of the first storage unit with the storage array device of the first storage unit.
  • the CMOS device of the second memory unit is bonded, so that the first group of contacts of the first memory unit is electrically connected to the second group of contacts of the second memory unit correspondingly.
  • the second memory unit 200 is turned over, so that the CMOS device of the second memory unit 200 is turned over. 20 faces the memory array device 10 of the first memory unit 100, and then the CMOS device 20 of the second memory unit 200 is bonded face-to-face with the memory array device 10 of the first memory unit 100, so that the first group of the first memory unit 100
  • the contacts 40 are electrically connected to the second set of contacts 50 of the second storage unit 200, so that the first storage unit 100 and the second storage unit 200 pass through the corresponding first set of contacts 40, second set of contacts 50 and
  • the respective interconnect channels 30 of each memory cell make electrical connections.
  • the first bonding layer 42 of the first memory unit 100 is adhered to the second bonding layer 52 of the second memory unit 200 .
  • the manufacturing method of the three-dimensional storage device when the carrier sheet 600 is bonded to the outer side of the memory array device 10 of the second memory unit 200 , when the second memory unit 200 is stacked on the first memory unit 100 and the After the CMOS device 20 of the second storage unit 200 is bonded to the storage array device 10 of the first storage unit 100 , the manufacturing method of the three-dimensional storage device further includes: removing the carrier sheet 600 to make the first group of the second storage unit 200 The contacts 40 are exposed.
  • the manufacturing method of the three-dimensional memory device further comprises the following steps:
  • An isolation layer 300 is formed on the side of the memory array device 10 of the outer second memory unit 200 away from the CMOS device 20 of the outer second memory unit 200 , and the isolation layer 300 covers the memory array device 10 of the outer second memory unit 200 and faces away from the outside.
  • Array pads 400 are arranged in the isolation layer 300, and the array pads 400 are electrically connected to the first group of contacts 40 of the outer second memory unit 200;
  • a protective layer 500 having an opening is formed on the side of the isolation layer 300 away from the outer second memory unit 200 , so that the protective layer 500 covers the isolation layer 300 , and the opening exposes the array pad 400 .
  • the isolation layer 300 covers the side of the first bonding layer 42 of the outer second memory unit 200 away from the array substrate 11, and the exposed array pads 400 are used to connect external devices (such as control devices or driving circuits, etc.),
  • the protective layer 500 is used to protect the isolation layer 300 from being damaged to ensure the connection reliability of the array pads 400.
  • specific features, functions or the formation process of the isolation layer 300, the array pads 400 and the protective layer 500 please refer to the above three-dimensional memory device The corresponding content in , will not be repeated here.
  • the first memory unit 100 and the second memory unit 200 can be stacked to form a three-dimensional memory device 1000 with a relatively high storage density (as shown in FIG. 1 ), so that it is not necessary to store a Too many storage layers 13 are stacked in the cell storage array device 10, so that the area of the array substrate 11 of each storage cell is not too large, which is beneficial to arrange the array substrate of each storage cell with an appropriate area ratio 11 and the CMOS substrate 21, thereby reducing the unused space in each memory unit and improving the space utilization of the three-dimensional memory device.
  • the respective memory array devices 10 of the first memory unit 100 and the second memory unit 200 each include a predetermined number of memory layers 13, and the value of the predetermined number of layers is greater than 0 and an integer less than 500, such as 32 layers, 64 layers, 96 layers or 128 layers.
  • the number of layers of the storage layers 13 in the respective storage array devices 10 of the first storage unit 100 and the second storage unit 200 may be the same or different. In some embodiments, the number of layers of the memory layers 13 in the memory array device 10 of the first memory unit 100 and the second memory unit 200 may be the same, so that the first memory unit 100 and the second memory unit 200 can be mass-produced in the same process steps.
  • the number of second storage units 200 may be set to multiple, and the manufacturing method of the three-dimensional storage device includes the following steps:
  • One of the second memory cells 200 is stacked on the side of the memory array device 10 of the first memory cell 100 that faces away from the CMOS device 20 of the first memory cell 100, and the CMOS device 20 of the one of the second memory cells 200 is stacked with the CMOS device 20 of the first memory cell 100.
  • the memory array device 10 of the first memory unit 100 is engaged, so that the second group of contacts 50 of the one of the second memory units 200 is electrically connected to the first group of contacts 40 of the first memory unit 100 correspondingly;
  • One of the other second memory cells 200 is stacked on the side of the memory array device 10 of the outer layer second memory cell 200 facing away from the CMOS device 20 of the outer layer second memory cell 200, and the other one of the second memory cells 200 is stacked.
  • the CMOS device 20 of the memory cell 200 is bonded to the memory array device 10 of the outer second memory cell 200, so that the first group of contacts 40 of the outer second memory cell 200 is connected to the other one of the second memory cells.
  • the second group of contacts 50 of the unit 200 are correspondingly electrically connected, and this step is repeated until a plurality of second storage units 200 are stacked on the first storage unit 100 in sequence, wherein the outer second storage unit 200 The second storage unit 200 is stacked on the first storage unit 100 and is farthest from the first storage unit 100 in the stacking direction.
  • the side of the storage array device 10 of each second storage unit 200 away from the CMOS device 20 may be bonded with a carrier sheet 600.
  • the step of removing the carrier sheet 600 needs to be performed.
  • the carrier sheet 600 bonded to one side of the storage array device 10 of the plurality of second storage units 200 may be the same carrier sheet 600 , that is, after the carrier sheet 600 is removed from the storage array device 10 of one second storage unit 200 , the carrier sheet 600 is again bonded to the outer side of the memory array device 10 of the next second memory unit 200 to be stacked. Repeated use of the carrier sheet 600 can reduce the number of carrier sheets 600 and reduce costs.
  • different carrier sheets 600 may be bonded to the outer side of the memory array device 10 of each second memory cell 200 .
  • the first storage unit 100 and a plurality of second storage units 200 can be stacked in sequence to form a three-dimensional storage device 1000b (as shown in FIG. 2 ).
  • the three-dimensional memory device 1000b has more memory cells, so the storage density of the three-dimensional memory device 1000b is higher, and it is not necessary to stack too many memory layers 13 in the memory array device 10 of each memory cell of the three-dimensional memory device 1000b, Thus, the space utilization rate of the three-dimensional memory device 1000b is improved.
  • the bonding method between the CMOS devices 20 includes an Xtacking bonding process.
  • the Xtacking bonding process refers to realizing the alignment bonding of bonding structures between different devices in the same process step, thereby realizing the electrical connection of the two devices.
  • the Xtacking bonding process it is beneficial to choose a more advanced manufacturing process to manufacture memory array devices and CMOS devices respectively, reducing the complexity of the manufacturing process, so that the three-dimensional memory device can obtain higher I/O transmission speed, higher density, and a smaller volume.
  • the present disclosure also provides a three-dimensional memory, the three-dimensional memory includes any of the above three-dimensional storage devices, the three-dimensional memory has the advantages of high storage density and high space utilization of the three-dimensional storage device, and also has the three-dimensional storage device. Other structural features and functions of , will not be repeated here.

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Abstract

本公开提供一种三维存储器件及其制造方法、以及三维存储器。三维存储器件包括第一存储单元和依次堆叠于第一存储单元上的至少一个第二存储单元。每一存储单元包括第一组触点及堆叠设置且相互电连接的存储阵列器件和CMOS器件，第一组触点设于存储阵列器件背离CMOS器件的一侧并与CMOS器件电连接。第二存储单元还包括设于CMOS器件背离存储阵列器件的一侧并与CMOS器件电连接的第二组触点。第一存储单元的存储阵列器件与相邻的第二存储单元的CMOS器件接合，且第一存储单元的第一组触点与相邻的第二存储单元的第二组触点对应电连接。

Description

三维存储器件及其制造方法、以及三维存储器
相关申请的交叉引用
本申请基于申请号为202110330026.2、申请日为2021年03月27日、发明名称为“三维存储器件及其制造方法、以及三维存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及半导体器件技术领域，尤其涉及一种三维存储器件及其制造方法、以及包括所述三维存储器件的三维存储器。
背景技术
3D NAND存储器是一种新兴的三维存储器类型，通过在存储芯片中垂直堆叠多层数据存储层，解决2D或者平面NAND存储器存储容量有限的问题。其中，存储芯片包括CMOS器件及具有台阶结构的存储阵列器件，CMOS器件与存储阵列器件分别形成于一衬底上，且CMOS器件与存储阵列器件远离各自衬底的一侧相互电连接。
随着3D NAND存储器高密度设计需求的日益增长，存储芯片的存储阵列器件中的存储层日益增加。然而，现有技术中，随着存储层堆叠层数的增加，存储阵列器件的台阶结构的台阶层数和占用面积均相应增加，使得存储阵列器件的衬底面积增大，进而使得存储阵列器件的衬底和CMOS器件的衬底之间出现面积不匹配的状况，导致存储芯片存在利用空间闲置的状况，从而不利于下一代的3D NAND存储器的开发以及体积小型化。
发明内容
本公开一方面提供一种三维存储器件，包括依次堆叠的至少两个存储单元，所述至少两个存储单元包括第一存储单元和堆叠于所述第一存储单元上的至少一个第二存储单元，每一存储单元包括：
存储阵列器件和CMOS器件，所述存储阵列器件与所述CMOS器件堆叠设置且相互电连接；以及
第一组触点，设于所述存储阵列器件背离所述CMOS器件的一侧，并与所述CMOS器件电连接；
其中，所述第二存储单元还包括第二组触点，所述第二组触点设于所述第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧，并与所述第二存储单元的CMOS器件电连接；
所述第一存储单元的存储阵列器件与相邻的第二存储单元的CMOS器件接合，并且所述第一存储单元的第一组触点与相邻的第二存储单元的第二组触点对应电连接；
所述第二存储单元为一个时，所述第二存储单元为堆叠于所述第一存储单元上的外层第二存储单元，所述外层第二存储单元的第一组触点用于连接外部器件；
所述第二存储单元为多个时，所述多个第二存储单元依次堆叠于所述第一存储单元上，相邻两个所述第二存储单元中，靠近所述第一存储单元的第二存储单元的第一组触点与远离所述第一存储单元的第二存储单元的第二组触点对应电连接，沿堆叠方向距离所述第一存储单元最远的第二存储单元定义为外层第二存储单元，所述外层第二存储单元的第一组触点用于连接外部器件。
本公开另一方面还提供一种三维存储器件的制造方法，包括如下步骤：
提供第一存储单元和第二存储单元，所述第一存储单元和所述第二存储单元均包括第一组触点、以及堆叠设置且相互电连接的存储阵列器件和CMOS器件，其中，所述第一组触点设于所述存储阵列器件背离所述CMOS器件的一侧并与所述CMOS器件电连接；
对所述第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧进行减薄；
在所述第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧形成第二组触点，其中，所述第二组触点与所述第二存储单元的CMOS器件电连接；以及
将所述第二存储单元堆叠于所述第一存储单元的存储阵列器件背离所述第一存储单元的CMOS器件的一侧，并将所述第一存储单元的存储阵列器件与所述第二存储单元的CMOS器件接合，使所述第一存储单元的第一组触点与所述第二存储单元的第二组触点对应电连接。
本公开再一方面还提一种三维存储器，包括上述的三维存储器件。
附图说明
图1是本公开其中一实施例提供的三维存储器件的截面示意图。
图2是本公开另一实施例提供的三维存储器件的截面示意图。
图3是本公开提供的三维存储器件的制造方法的流程图。
图4至图7是三维存储器件的存储单元的形成过程示意图，其中，图4是存储阵列器件和CMOS器件的截面示意图；
图5是图4所示存储阵列器件和CMOS器件键合后的截面示意图；
图6是图5所示存储阵列器件和CMOS器件在阵列衬底减薄后的截面示意图；
图7是图6所示存储阵列器件背离CMOS器件的一侧形成第一组触点并覆盖第一接合层的截面示意图。
图8是图7所示第二存储单元在存储阵列器件背离CMOS器件的一侧贴合承载片并翻转后的截面示意图。
图9是图8所示第二存储单元在CMOS衬底减薄后的截面示意图。
图10是图9所示第二存储单元在CMOS衬底形成导电通道、且CMOS衬底背离存储阵列器件的一侧依次覆盖第一绝缘层及第二绝缘层的截面示意图。
图11是图10所示第二存储单元在第二绝缘层形成第二组触点并覆盖第二接合层的截面示意图。
图12是图11所示第二存储单元在翻转后并且与第一存储单元键合的截面示意图。
图13是图12所示第一存储单元和第二存储单元在第二存储单元去除承载片并且其第一接合层减薄至第一组触点外露的截面示意图。
主要元件符号说明：
第一存储单元            100
第二存储单元            200
存储阵列器件            10
阵列衬底                11
存储层                  13
CMOS器件                20
CMOS衬底                21
互连通道                30
第一互连子通道          31
第二互连子通道          32
互连结构                33
第一互连触点            331
第二互连触点            332
第一组触点              40
第一导电通道            41
第一接合层              42
第二组触点              50
第二接合层              52
隔离层                  300
阵列焊盘                400
保护层                  500
第二导电通道            60
如下具体实施方式将结合上述附图进一步说明本公开。
具体实施方式
提供下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要说明的是，术语“上”、“下”、“内侧”、“外侧”等指示的方位或者位置关系为基于附图所示的方位或者位置关系，仅是为 了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性。
请参阅图1及图2，本公开提供一种三维存储器件，包括依次堆叠的至少两个存储单元，所述至少两个存储单元包括第一存储单元100和堆叠于第一存储单元100上的至少一个第二存储单元200。如图1所示，本公开的其中一实施例中，第二存储单元200的数量为一个，第一存储单元100和一个第二存储单元200堆叠构成三维存储器件1000；如图2所示，本公开的另一实施例中，第二存储单元200的数量为多个(两个或者两个以上)，多个第二存储单元200依次堆叠于第一存储单元100上，第一存储单元100和多个第二存储单元200堆叠构成三维存储器件1000b。本公开提供的三维存储器件由至少两个存储单元堆叠而成，因此存储密度高。
如图1及图2所示，本公开的一些实施例中，每一存储单元均包括堆叠设置且相互电连接的存储阵列器件10和CMOS器件20，以及设于存储阵列器件10背离CMOS器件20的一侧、并且与CMOS器件20电连接的第一组触点40。本公开的一些实施例中，每一存储单元的存储阵列器件10和CMOS器件20可以采用键合连接，从而实现二者之间的电连接。当然，在其他实施例中，每一存储单元的存储阵列器件10和CMOS器件20还可以采用其他方式实现电连接，包括但不限于导线连接、导电触点连接、接插连接等。
其中，存储阵列器件10包括阵列衬底11及设于阵列衬底11靠近CMOS器件20一侧的存储阵列，所述存储阵列具有数据存储功能，所述存储阵列包括若干存储层13及贯穿并连通若干存储层13的若干存储串。每一存储单元的第一组触点40设于阵列衬底11背离CMOS器件20的一侧。其中，CMOS器件20包括CMOS衬底21及设于CMOS衬底21靠近存储阵列器件10一侧的CMOS电路，所述CMOS电路用于实现对存储阵列器件10的逻辑控制、存储数据的读取等。
如图1及图2所示，本公开的一些实施例中，每一存储单元还包括互连通道30，所述互连通道30分别与所在存储单元的第一组触点40及CMOS器件20电连接，以使第一组触点40通过互连通道30电连接于CMOS器件20。本公开的一些实施例中，互连通道30设置于所在存储单元的存储阵列器件10与CMOS器件20之中，并且与阵列衬底11及CMOS衬底21垂直。当然，在其他实施例中，互连通道30也可以不垂直于阵列衬底11及CMOS衬底21，还可以垂直于阵列衬底11或者垂直于CMOS衬底21。
本公开的一些实施例中，每一第二存储单元200还包括第二组触点50。在一些实施例中，第二组触点50设于第二存储单元200的CMOS器件20背离第二存储单元200的存储阵列器件10的一侧，并且与第二存储单元200的CMOS器件20电连接。
如图1及图2所示，本公开的一些实施例中，第一存储单元100的存储阵 列器件10与相邻的第二存储单元200的CMOS器件20接合，并且第一存储单元100的第一组触点40与相邻的第二存储单元200的第二组触点50对应电连接，使得第一存储单元100与相邻的第二存储单元200通过对应的第一组触点40、第二组触点50实现电连接。
如图1所示，本公开的其中一实施例中，当三维存储器件1000中的第二存储单元200只有一个时，该第二存储单元200即为堆叠于第一存储单元100上的外层第二存储单元200，所述外层第二存储单元200的第一组触点40用于连接外部器件(例如控制器件或者驱动电路等)，从而实现对三维存储器件1000的驱动、控制等功能。
如图2所示，本公开的另一实施例中，当三维存储器件1000b中的第二存储单元200为多个时，多个第二存储单元200依次堆叠于第一存储单元100上，相邻两个第二存储单元200中，靠近第一存储单元100的第二存储单元200的第一组触点40与远离第一存储单元100的第二存储单元200的第二组触点50对应电连接，使得相邻两个第二存储单元200通过对应的第一组触点40、第二组触点50实现电连接，进而使得第一存储单元100和依次堆叠于第一存储单元100上的多个第二存储单元200实现电连接。其中，沿堆叠方向距离第一存储单元100最远的第二存储单元200即为堆叠于第一存储单元100上的外层第二存储单元200，所述外层第二存储单元200的第一组触点40用于连接外部器件(例如控制器件或者驱动电路等)，从而实现对三维存储器件1000b的驱动、控制等功能。可以理解的是，相比于三维存储器件1000，三维存储器件1000b中堆叠的存储单元的数量更多，因此三维存储器件1000b的存储密度更高。
本公开的实施例中，通过将至少两个存储单元依次进行堆叠，并通过对应的第一组触点40、第二组触点50实现所述至少两个存储单元之间的电连接，即可构成存储密度较高的三维存储器件，从而不必在每一存储单元的存储阵列器件10中堆叠过多的存储层13，使得每一存储单元的阵列衬底11的面积不会过大，从而有利于以适当的面积配比去设置每一存储单元的阵列衬底11和CMOS衬底21，进而能够减少每一存储单元中闲置的利用空间，提高该三维存储器件的空间利用率。
其中，阵列衬底11和CMOS衬底21均可以由半导体材料或者非导电材料制成，所述半导体材料包括但不限于硅、锗、硅锗、砷化镓、绝缘体上硅、绝缘体上锗或者其任何合适的组合，所述非导电材料包括但不限于玻璃、塑料或者蓝宝石。本公开的实施例中，阵列衬底11和CMOS衬底21均为硅衬底。其中，除了第一存储单元100的CMOS衬底21之外，三维存储器件中的任意存储单元的阵列衬底11和CMOS衬底21均可以减薄，以利于减小三维存储器件的体积。所述减薄的手段包括但不限于机械研磨、湿/干蚀刻、化学机械研磨或者其任意组合。
如图1及图2所示，每一存储阵列器件10中，若干存储层13呈台阶结构堆叠于阵列衬底11的一侧，若干存储串(例如NAND串)贯穿并连通所述若干存储层13，从而使所述若干存储串与所述若干存储层13共同构成具有存储 功能的存储阵列。
在一些实施方式中，每一存储层13沿平行于阵列衬底11表面的横向方向延伸；沿逐渐远离且垂直于阵列衬底11的方向，若干存储层13中每相邻的两个存储层13偏移相同的距离，且在横向方向上缩减相同的延伸距离。可以理解的是，每相邻的两个存储层13可以在横向方向上的一端平齐、另一端缩减相同的距离，也可以在横向方向上的两端分别缩减相同的距离。如图1及图2所示，本公开的一些实施例中，每相邻的两个存储层13在横向方向上的两端分别缩减相同的距离。其中，每一存储层13可以包括一个或者多个导体/电介质层对，每个所述导体/电介质层对包括一导体层和一电介质层，所述导体层和所述电介质层的具体结构、功能及材料与现有技术中常用的导体层和电介质层的结构、功能及材料相同，故此处不做赘述。
每一所述存储串包括沿垂直于阵列衬底11的方向延伸并贯穿所述若干存储层13的沟道结构，所述沟道结构包括填充有半导体材料(作为半导体沟道)和电介质材料(作为存储膜)的沟道孔。其中，所述存储膜可以包括隧道层、电荷捕获/存储层和阻隔层，所述半导体沟道、所述隧穿层、所述电荷捕获/存储层及所述阻隔层沿所述存储串的中心朝外的方向依次布置。需要说明的是，所述存储串的具体结构、功能及材料与现有技术中常用的存储串的结构、功能及材料相同，故此处也不做赘述。
本公开提供的三维存储器件中，第一存储单元100和第二存储单元200各自的存储阵列器件10中均包括若干存储层13。如前所述，为避免阵列衬底11的面积过大，每一存储单元的存储阵列器件10中不必堆叠过多的存储层13，本公开实施例提供的三维存储器件中，第一存储单元100和第二存储单元200各自的存储阵列器件10中均包括预定层数的存储层13，所述预定层数的取值为大于0且小于500的整数，例如32层、64层、96层或者128层。其中，第一存储单元100和第二存储单元200各自的存储阵列器件10中的存储层13的层数可以相同或者不相同。在一些实施例方式中，第一存储单元100和第二存储单元200各自的存储阵列器件10中的存储层13的层数可以为相同，以利于第一存储单元100和第二存储单元200在相同的工艺步骤中批量生产。
可以理解的是，每一存储单元中，存储阵列器件10和CMOS器件20还分别包括其他的一些元件，例如覆盖所述存储阵列或者所述CMOS电路的堆叠层、设于所述堆叠层的内侧表面的键合结构(包括但不限于导线、插头、焊块或者焊盘等导电结构)、及贯穿所述堆叠层且分别与所述键合结构及所述存储阵列或者所述CMOS电路电连接的若干互连导电通道等，其中，所述堆叠层至少包括一层覆盖所述存储阵列或者所述CMOS电路的绝缘层，存储阵列器件10和CMOS器件20的具体结构及功能与现有技术中的存储阵列器件和CMOS器件的结构及功能基本相同，因与本公开的改进与创造无关，故此处不做赘述。
如图1及图2所示，本公开的一些实施例中，互连通道30包括第一互连子通道31、第二互连子通道32、及电连接于第一互连子通道31与第二互连子通道32之间的互连结构33。
在一些实施方式中，第一互连子通道31设于存储阵列器件10中且位于存储阵列器件10设有存储阵列的一侧，第一互连子通道贯穿存储阵列器件10的堆叠层；第二互连子通道32设于CMOS器件20中且位于CMOS器件20设有CMOS电路的一侧，第二互连子通道32贯穿CMOS器件20的堆叠层，其中，第二互连子通道32与第一互连子通道31的位置对应，且第二互连子通道32远离第一互连子通道31的一端与所述CMOS电路电连接。需要说明的是，第一互连子通道31和第二互连子通道32可以采用现有技术中的常用手段来形成，例如，本公开的一些实施例中，可以先在存储阵列器件10和CMOS器件20各自的堆叠层上进行深蚀刻，以形成贯穿所述堆叠层的填充通道，然后向所述填充通道内填充导电材料，以分别形成第一互连子通道31和第二互连子通道32，所述导电材料包括但不限于钨、钴、铜、铝、多晶硅、硅化物或者其任意组合。其中，第一互连子通道31与第二互连子通道32的数量均可以设置为一条或者多条，只要二者的数量对应相等即可，对此不作限定。
互连结构33包括第一互连触点和第二互连触点，所述第一互连触点设于存储阵列器件10的堆叠层的内侧(即靠近CMOS器件的一侧)表面、且与第一互连子通道31对应电连接，所述第二互连触点设于CMOS器件20的堆叠层的内侧(即靠近存储阵列器件的一侧)表面、且与第二互连子通道32对应电连接。其中，所述第一互连触点和第二互连触点包括但不限于导线、插头、焊块或者焊盘等导电结构，二者的结构形式可以相同或者不相同。如图1及图2所示，本公开的一些实施例中，所述第一互连触点为若干焊块，所述若干焊块与第一互连子通道31的数量相等且一一对应电连接；所述第二互连触点为焊盘，所述焊盘的一侧表面与第二互连子通道32对应电连接，所述焊盘的另一侧表面设有若干焊脚，所述若干焊脚与所述第一互连触点的若干焊块一一对应。可以理解的是，当每一存储单元的存储阵列器件10和CMOS器件20面对面键合时，所述第一互连触点和第二互连触点一并键合构成互连结构33，使得第一互连子通道31与第二互连子通道32通过互连结构33对应电连接，从而构成该存储单元的互连通道30。
请再次参阅图1及图2，本公开的一些实施例中，第一组触点40设于阵列衬底11的外侧(即背离存储阵列的一侧)，阵列衬底11在对应其所在存储阵列器件10中的第一互连子通道31的位置设有若干第一导电通道41，每一第一导电通道41均贯穿阵列衬底11的相对两侧、且与对应的一第一互连子通道31电连接，使得第一组触点40通过第一导电通道41电连接于第一互连子通道31。
其中，第一组触点40包括但不限于导线、插头、焊块或者焊盘等导电结构，本公开的一些实施例中，第一组触点40为焊盘，所述焊盘与第一导电通道41电连接。
阵列衬底11的外侧表面还覆盖有第一接合层42，第一导电通道41远离第一互连子通道31的一端及第一组触点40均嵌设于第一接合层42中。第一接合层42可以通过一个或者多个薄膜沉积过程形成，所述薄膜沉积过程包括但不限于化学气相沉积、物理气相沉积、原子层沉积或者其任意组合。第一接合层42 包括至少一层由电介质材料制成的电介质层，所述电介质材料包括但不限于氧化硅或者氮化硅，对此不作限定。
本公开的一些实施例中，第一导电通道41可以采用硅穿孔技术等常用手段形成。在一些实施方式中，先在第一接合层42和阵列衬底11对应若干第一互连子通道31的位置进行深蚀刻，以形成贯穿第一接合层42和阵列衬底11的若干第一垂直通道，每一所述第一垂直通道暴露对应的一第一互连子通道31的至少部分，然后向所述第一垂直通道内填充导电物质至所述导电物质部分超出阵列衬底11的外侧面，即可形成与第一互连子通道31接触的第一导电通道41，且第一导电通道41远离第一互连子通道31的一端位于第一接合层42内。通过在阵列衬底11的外侧表面覆盖第一接合层42，可以防止在第一导电通道41的制程中所述第一垂直通道内的导电物质发生泄漏，避免对其他制程造成污染。
本公开的一些实施例中，在形成第一导电通道41后，继续蚀刻第一接合层42对应第一导电通道41的位置，以形成用于暴露若干第一导电通道41远离第一互连子通道31的一端端部的开口，然后在所述开口内设置第一组触点40(即焊盘)，使得第一组触点40与若干第一导电通道41对应电连接。本公开的一些实施例中，将第一组触点40设置于第一接合层42的所述开口内后，可以向所述开口内再次填充第一接合层42的电介质材料以覆盖第一组触点40，避免第一组触点40外露，从而防止第一组触点40在与对应的第二组触点50键合连接之前受到损伤，有利于提高第一组触点40与对应的第二组触点50键合连接的可靠性。当然，在其他实施例中，第一组触点40也可以外露。可以理解的是，当第一接合层42的所述开口内的第一组触点40被电介质材料覆盖时，在第一组触点40与对应的第二组触点50键合连接之前需要对第一接合层42进行减薄或者蚀刻，以去除所述电介质材料，使所述开口内的第一组触点40外露。
如图1及图2所示，本公开的一些实施例中，第二存储单元200的第二组触点50设于其CMOS衬底21的外侧(即背离CMOS电路的一侧)，CMOS衬底21在对应其所在CMOS器件20中的第二互连子通道32的位置设有若干第二导电通道60，每一第二导电通道60均贯穿CMOS衬底21的相对两侧、且分别与第二组触点50及CMOS器件20的所述CMOS器件电连接，以使得第二组触点50通过第二导电通道60电连接于CMOS器件20的CMOS电路。当然，在其他实施例中，第二导电通道60可以不对应第二互连子通道32，只要第二导电通道60电连接于CMOS器件20的CMOS电路即可。
其中，第二组触点50包括但不限于导线、插头、焊块或者焊盘等导电结构，本公开的一些实施例中，第二组触点50为若干焊块，所述若干焊块与若干第二导电通道60一一对应电连接。
第二存储单元200的CMOS衬底21的外侧表面覆盖有第二接合层52，第二导电通道60远离第二互连子通道32的一端及第二组触点50均嵌设于第二接合层52中。与第一接合层42类似，第二接合层52也可以通过一个或者多个薄膜沉积过程形成，所述薄膜沉积过程包括但不限于化学气相沉积、物理气相沉积、原子层沉积或者其任意组合；第二接合层52同样包括至少一层由电介质材 料制成的电介质层，所述电介质材料包括但不限于氧化硅或者氮化硅，对此不作限定。
本公开的一些实施例中，第二导电通道60与第一导电通道41的形成过程基本相同，在一些实施方式中，可以先在第二接合层52和CMOS衬底21对应若干第二互连子通道32的位置进行深蚀刻，以形成贯穿第二接合层52和CMOS衬底21的若干第二垂直通道，每一所述第二垂直通道暴露对应的一第二互连子通道32的至少部分，然后向所述第二垂直通道内填充导电物质至所述导电物质部分超出CMOS衬底21的外侧面，即可形成与第二互连子通道32接触的第二导电通道60，使得第二导电通道60与CMOS电路电连接，第二导电通道60远离第二互连子通道32的一端位于第二接合层52内。通过在CMOS衬底21的外侧表面覆盖第二接合层52，可以防止在第二导电通道60的制程中所述第二垂直通道内的导电物质发生泄漏，避免对其他制程造成污染。其中，所述第二垂直通道和前述第一垂直通道内填充的导电物质包括但不限于钨、铜、铝、多晶硅、硅化物或者其任意组合，且所述第一垂直通道和所述第二垂直通道内填充的导电物质可以相同或者不同。
需要说明的是，本公开的一些实施例中，第二组触点50与第一组触点40的制程有所不同，其不同之处在于：在形成第二导电通道60后，可以直接在第二接合层52的每一所述第二垂直通道内设置一焊块，若干第二垂直通道内的若干焊块即构成第二组触点50。此外，与第一组触点40相同的是，本公开的一些实施例中，第二组触点50可以被覆盖或者被暴露。在一些实施方式中，第二组触点50可以为被覆盖，以防止第二组触点50在与对应的第一组触点40键合连接之前受到损伤，同样有利于提高第一组触点40与对应的第二组触点50键合连接的可靠性。可以理解的是，当第二接合层52的每一所述第二垂直通道内的焊块被第二接合层52的电介质材料覆盖(即第二组触点50被覆盖)时，在第一组触点40与对应的第二组触点50键合连接之前需要对第二接合层52进行减薄或者蚀刻，以去除每一所述第二垂直通道内的电介质材料，使每一所述第二垂直通道内的焊块外露，也即使第二组触点50外露，以便于和对应的第一组触点40键合。
可以理解的是，如图1及图2所示，任意相邻的两个存储单元中，位于下方的存储单元的第一组触点40与位于上方的另一存储单元的第二组触点50对应键合之后，相邻的两个存储单元各自的CMOS电路即被连通，且所述位于下方的存储单元的第一接合层42与所述位于上方的另一存储单元的第二接合层52贴合于一体。
请再次参阅图1及图2，本公开的一些实施例中，三维存储器件还包括隔离层300及嵌设于隔离层300中的阵列焊盘400。在一些实施方式中，隔离层300覆盖外层第二存储单元200背离第一存储单元100的一侧以及外层第二存储单元200的第一组触点40。隔离层300在对应于外层第二存储单元200的第一组触点40的位置开设有容置腔，所述容置腔对应的第一组触点40的至少一部分。阵列焊盘400设置于隔离层300的所述容置腔内，并与外层第二存储单 元200的第一组触点40电连接，三维存储器件通过阵列焊盘400电连接于前述的外部器件。
其中，隔离层300的所述容置腔可以通过蚀刻等常用手段形成，此处不做赘述；阵列焊盘400和前述的焊块、焊盘等均可以采用现有技术中的常用手段制备，因此也不做赘述。
需要说明的是，与第一接合层42和第二接合层52类似，隔离层300也可以通过一个或者多个薄膜沉积过程形成，所述薄膜沉积过程包括但不限于化学气相沉积、物理气相沉积、原子层沉积或者其任意组合；隔离层300同样可以包括至少一层由电介质材料制成的电介质层，所述电介质材料包括但不限于氧化硅或者氮化硅，对此不作限定。
其中，隔离层300的所述容置腔可以是一端朝向外层第二存储单元200开口的腔体，使得阵列焊盘400在连接所述外部器件之前被隔离层300覆盖，有利于保护阵列焊盘400，但是在电连接阵列焊盘400和所述外部器件时需要对隔离层300对应所述容置腔的位置进行减薄或刻蚀，以使阵列焊盘400外露。当然，隔离层300的所述容置腔也可以两端开口的腔体结构，使得阵列焊盘400外露，以便于直接和所述外部器件电连接。
如图1及图2所示，本公开的一些实施例中，隔离层300覆盖于最外层的第二存储单元200的第一接合层42的外侧。可以理解的是，隔离层300和第一接合层42均由电介质材料构成，因此，隔离层300和第一接合层42的材料可以相同也可以不同。也即意味着，隔离层300和第一接合层42可以在不同的薄膜沉积过程中形成，也可以在相同的薄膜沉积过程中形成。在一些实施方式中，隔离层300和第一接合层42在不同的薄膜沉积过程中形成，从而可以在不同的薄膜沉积过程中分次设置第一组触点40和阵列焊盘400，操作方便；再者，分次形成第一接合层42和隔离层300，当分别蚀刻第一接合层42和隔离层300时，蚀刻深度较小，有利于提高蚀刻效率和精度。
如图1及图2所示，本公开的一些实施例中，三维存储器件还包括层叠于隔离层300的外侧面上的保护层500，保护层500覆盖隔离层300且在对应于阵列焊盘400的位置开设有开口，阵列焊盘400的至少部分通过所述开口外露以用于连接所述外部器件。当然，在其他实施例中，保护层500也可以覆盖阵列焊盘400，以保护阵列焊盘400，但是在电连接阵列焊盘400和所述外部器件时需要对保护层500对应阵列焊盘400位置进行减薄或刻蚀，以使阵列焊盘400外露。
通过在隔离层300上覆盖保护层500，可以保护隔离层300，防止隔离层300被损坏，从而避免阵列焊盘400因隔离层300的损坏而松动，保证阵列焊盘400的连接可靠性。
其中，保护层500可以由氮化硅或者氧化硅等材料制成，并通过蚀刻等常用手段开设开口，此处不做赘述。
请参阅图3，本公开还提供一种如上所述的三维存储器件的制造方法，所述三维存储器件的制造方法包括如下步骤：
步骤S1，提供第一存储单元和第二存储单元，所述第一存储单元和第二存储单元均包括第一组触点、以及堆叠设置且相互电连接的存储阵列器件和CMOS器件，其中，所述第一组触点设于所述存储阵列器件背离所述CMOS器件的一侧并与所述CMOS器件电连接。
在一些实施方式中，请一并参阅图4至图7，所述存储单元的制造过程如下：
第一步，提供存储阵列器件10和CMOS器件20。如图4所示，存储阵列器件10包括阵列衬底11、设于阵列衬底11内侧(即靠近CMOS器件20的一侧)的存储阵列、设于所述存储阵列中的第一互连子通道31、及设于存储阵列器件10的内侧表面且与第一互连子通道31电连接的第一互连触点331，其中，所述存储阵列包括呈台阶结构的若干存储层13及贯穿并连通所述若干存储层13的若干存储串；如图4所示，CMOS器件20包括CMOS衬底21、设于CMOS衬底21内侧(即靠近存储阵列器件10的一侧)的CMOS电路、设于所述CMOS电路的一侧且与所述CMOS电路电连接的第二互连子通道32、及设于CMOS器件20的内侧表面且与第二互连子通道32电连接的第二互连触点332。需要说明的是，阵列衬底11、所述若干存储层13、所述若干存储串、CMOS衬底21、第一互连子通道31、第二互连子通道32、第一互连触点331及第二互连触点332的具体特征、功能或其形成过程可以参见上述三维存储器件中的相应内容，此处不再赘述。此外，存储阵列器件10和CMOS器件20还分别包括其他的一些元件，且二者的具体结构及功能与现有的存储阵列器件和CMOS器件的结构及功能基本相同，因与本公开的改进与创造无关，故此处也不做赘述。
第二步，将存储阵列器件10和CMOS器件20面对面键合。如图5所示，存储阵列器件10和CMOS器件20对位键合后，前述的第一互连触点331与第二互连触点332(如图4所示)一并键合构成互连结构33，使得前述的第一互连子通道31与第二互连子通道32通过互连结构33对应电连接，从而构成存储单元的互连通道30，所述互连通道30分别与所在存储单元的第一组触点40及CMOS器件20电连接，以使第一组触点40通过互连通道30电连接于CMOS器件20。
第三步，如图6所示，对存储阵列器件10的阵列衬底11的外侧(即背离存储阵列的一侧)进行减薄。所述减薄的手段包括但不限于机械研磨、湿/干蚀刻、化学机械研磨或者其任意组合。
第四步，在存储阵列器件10的外侧形成第一组触点40，使第一组触点40电连接于第一互连子通道31。如图7所示，本公开的一些实施例中，阵列衬底11的外侧表面覆盖有第一接合层42，通过常用的技术手段可以形成贯穿阵列衬底11且与第一互连子通道31电连接的第一导电通道41，第一导电通道41远离第一互连子通道31的一端及第一组触点40均嵌设于第一接合层42中，第一组触点40通过第一导电通道41电连接于第一互连子通道31。同样的，第一接合层42及第一导电通道41的具体特征、功能或其形成过程可以参见上述三维存储器件中的相应内容，此处不再赘述。
通过上述第一步至第四步的步骤，即可制备第一存储单元100、及第二存储单元200与第一存储单元100相同的部分。
步骤S2，对所述第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧进行减薄。也即对所述第二存储单元的CMOS衬底背离CMOS电路的一侧进行减薄，所述减薄的手段包括但不限于机械研磨、湿/干蚀刻、化学机械研磨或者其任意组合。
请一并参阅图8及图9，本公开的一些实施例中，在步骤S2之前，所述三维存储器件的制造方法还包括步骤：提供承载片，并将所述承载片贴合于所述第二存储单元的存储阵列器件背离所述第二存储单元的CMOS器件的一侧，使所述承载片覆盖所承载的第二存储单元的存储阵列器件背离所述第二存储单元的CMOS器件的一侧及所述第二存储单元的第一组触点。
在一些实施方式中，如图8及图9所示，先将第二存储单元200翻转，使得第二存储单元200的存储阵列器件10处于下方，然后将承载片600贴合于第二存储单元200的存储阵列器件10的外侧(即背离第二存储单元200的CMOS器件20的一侧)，使得承载片600覆盖所承载的第二存储单元200的存储阵列器件10的外侧及第一组触点40，最后对第二存储单元200的CMOS衬底21进行减薄。通过将承载片600贴合于第二存储单元200的存储阵列器件10的外侧，可以起到支撑第二存储单元200的作用，有利于减少甚至避免第二存储单元200在转运或者CMOS衬底21减薄的过程中发生变形。
其中，承载片600可以是玻璃、蓝宝石或半导体材料制成，对此不作限定。
其中，将承载片600贴合于第二存储单元200的存储阵列器件10的外侧又包括以下步骤：
首先，在承载片600朝向第二存储单元200的一侧和/或第二存储单元200的存储阵列器件10的外侧涂布加热固化胶、紫外光照射固化胶、加热分解胶或者激光分解胶中的任一种键合胶。在一些实施方式中承载片600朝向第二存储单元200的一侧和第二存储单元200的存储阵列器件10的外侧均涂布有键合胶，以增强承载片600和第二存储单元200的存储阵列器件10的外侧之间的粘附性。
然后，通过临时键合工艺或者永久键合工艺将承载片600键合于第二存储单元200的存储阵列器件10的外侧。其中，所述临时键合工艺是指将承载片600键合于第二存储单元200的存储阵列器件10的外侧、且在需要时能够较为容易的将承载片600从存储阵列器件10的外侧去除所采用的工艺手段，承载片600的去除较为容易；所述永久键合工艺则是指将承载片600键合于第二存储单元200的存储阵列器件10的外侧、但需要辅加较大的外力才能将承载片600从存储阵列器件10的外侧去除所采用的工艺手段，承载片600与第二存储单元200的存储阵列器件10之间的键合连接较为牢靠。
可以理解的是，本公开的一些实施例中，第二存储单元200的存储阵列器件10的外侧覆盖有第一接合层42，因此，在一些实施方式中，承载片600可以是键合于第一接合层42的外侧。
步骤S3，在所述第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧形成第二组触点，其中，所述第二组触点与所述第二存储单元的CMOS器件电连接。
请一并参阅图10及图11，本公开的一些实施例中，所述的三维存储器件的制造方法的步骤S3包括以下步骤：
在第二存储单元200的CMOS衬底21上形成贯穿CMOS衬底21的通孔(即前述的第二垂直通道)，所述通孔暴露第二存储单元200的互连通道30的至少一部分(即前述的第二互连子通道32的至少一部分)；
在所述通孔内填充导电介质以形成导电通道(即前述的第二导电通道60)，所述导电通道与第二存储单元200的互连通道30电连接；
自所述导电通道远离第二存储单元200的互连通道30的一端(即第二导电通道60远离第二互连子通道32的一端)形成第二存储单元200的第二组触点50，使第二组触点50通过所述导电通道与第二存储单元200的互连通道30电连接。
其中，如图10及图11所示，在形成第二组触点50之前，第二存储单元200的CMOS衬底21的外侧(即背离CMOS电路的一侧)表面先覆盖有第二接合层52，然后通过常用的技术手段可以形成贯穿CMOS衬底21且与第二互连子通道32电连接的第二导电通道60，第二导电通道60远离第二互连子通道32的一端及第二组触点50均嵌设于第二接合层52中，第二组触点50通过第二导电通道60电连接于CMOS器件20的CMOS电路，同时电连接于互连通道30的第二互连子通道32。同样的，第二接合层52及第二导电通道60的具体特征、功能或其形成过程可以参见上述三维存储器件中的相应内容，此处不再赘述。
在第二存储单元200的CMOS器件20的外侧(即背离存储阵列器件10的一侧，也即CMOS衬底的外侧)形成第二组触点50之后，所述三维存储器件的制作方法还包括步骤S4：将所述第二存储单元堆叠于所述第一存储单元的存储阵列器件背离所述第一存储单元的CMOS器件的一侧，并将所述第一存储单元的存储阵列器件与所述第二存储单元的CMOS器件接合，使所述第一存储单元的第一组触点与所述第二存储单元的第二组触点对应电连接。
在一些实施方式中，请参阅图12，承载片600键合于第二存储单元200的存储阵列器件10的外侧之后，再将第二存储单元200翻转过来，使第二存储单元200的CMOS器件20面朝第一存储单元100的存储阵列器件10，然后将第二存储单元200的CMOS器件20与第一存储单元100的存储阵列器件10面对面键合，使第一存储单元100的第一组触点40与第二存储单元200的第二组触点50对应电连接，进而使第一存储单元100与第二存储单元200通过对应的第一组触点40、第二组触点50及每一存储单元各自的互连通道30实现电连接。此时，第一存储单元100的第一接合层42与第二存储单元200的第二接合层52贴合。
请参阅图13，本公开的一些实施例中，第二存储单元200的存储阵列器件 10的外侧键合有承载片600时，在将第二存储单元200堆叠到第一存储单元100上且将第二存储单元200的CMOS器件20与第一存储单元100的存储阵列器件10键合之后，所述三维存储器件的制造方法还包括：去除承载片600，使第二存储单元200的第一组触点40外露。
请参阅图1，本公开的一些实施例中，在将第二存储单元200的CMOS器件20与第一存储单元100的存储阵列器件10键合、且第二存储单元200的第一组触点40外露之后，所述的三维存储器件的制造方法还包括以下步骤：
在外层第二存储单元200的存储阵列器件10背离外层第二存储单元200的CMOS器件20的一侧形成隔离层300，隔离层300覆盖外层第二存储单元200的存储阵列器件10背离外层第二存储单元200的CMOS器件20的一侧及外层第二存储单元200的第一组触点40，其中，所述外层第二存储单元200为堆叠于第一存储单元100上且沿堆叠方向距离第一存储单元100最远的第二存储单元200；
在所述隔离层300内设置阵列焊盘400，并使阵列焊盘400与外层第二存储单元200的第一组触点40对应电连接；
在隔离层300背离外层第二存储单元200的一侧形成具有开口的保护层500，使保护层500覆盖隔离层300，且所述开口暴露阵列焊盘400。
其中，隔离层300覆盖于外层第二存储单元200的第一接合层42背离阵列衬底11的一侧，外露的阵列焊盘400用于连接外部器件(例如控制器件或者驱动电路等)，保护层500用于保护隔离层300不被损坏以保证阵列焊盘400的连接可靠性，隔离层300、阵列焊盘400以及保护层500的具体特征、功能或其形成过程可以参见上述三维存储器件中的相应内容，此处不再赘述。
通过上述步骤，本公开的一些实施例中，第一存储单元100和第二存储单元200即可堆叠构成存储密度较高的三维存储器件1000(如图1所示)，从而不必在每一存储单元的存储阵列器件10中堆叠过多的存储层13，使得每一存储单元的阵列衬底11的面积不会过大，有利于以适当的面积配比去设置每一存储单元的阵列衬底11和CMOS衬底21，进而能够减少每一存储单元中闲置的利用空间，提高该三维存储器件的空间利用率。
在一些实施方式中三维存储器件1000中，第一存储单元100和第二存储单元200各自的存储阵列器件10中均包括预定层数的存储层13，所述预定层数的取值为大于0且小于500的整数，例如32层、64层、96层或者128层。其中，第一存储单元100和第二存储单元200各自的存储阵列器件10中的存储层13的层数可以相同或者不相同。在一些实施例方式中，第一存储单元100和第二存储单元200各自的存储阵列器件10中的存储层13的层数可以为相同，以利于第一存储单元100和第二存储单元200在相同的工艺步骤中批量生产。
请参阅图2，本公开的另一些实施例中，第二存储单元200的数量可以设置为多个，所述三维存储器件的制造方法包括以下步骤：
将其中一个第二存储单元200堆叠于第一存储单元100的存储阵列器件10背离第一存储单元100的CMOS器件20的一侧，并将所述其中一个第二存储 单元200的CMOS器件20与第一存储单元100的存储阵列器件10接合，使所述其中一个第二存储单元200的第二组触点50与所述第一存储单元100的第一组触点40对应电连接；
将其中另一个第二存储单元200堆叠于外层第二存储单元200的存储阵列器件10背离所述外层第二存储单元200的CMOS器件20的一侧，并将所述其中另一个第二存储单元200的CMOS器件20与所述外层第二存储单元200的存储阵列器件10接合，使所述外层第二存储单元200的第一组触点40与所述其中另一个第二存储单元200的第二组触点50对应电连接，以及重复该步骤，直至将多个第二存储单元200依次堆叠于所述第一存储单元100上，其中，所述外层第二存储单元200为堆叠于第一存储单元100上且沿堆叠方向距离第一存储单元100最远的第二存储单元200。
需要说明的是，为避免第二存储单元200发生变形，每一第二存储单元200的存储阵列器件10背离CMOS器件20的一侧均可以键合有承载片600，因此，在将每一个第二存储单元200与其他存储单元(第一存储单元100或者另一个第二存储单元200)键合前，都需要执行去除承载片600的步骤。其中，键合于多个第二存储单元200的存储阵列器件10一侧的承载片600可以是同一个承载片600，即将承载片600从一个第二存储单元200的存储阵列器件10上去除后，该承载片600再次被键合于下一个待堆叠的第二存储单元200的存储阵列器件10的外侧，承载片600反复使用可以减少承载片600的数量，减少成本。当然，每一第二存储单元200的存储阵列器件10的外侧可以键合不同的承载片600。
通过上述步骤，本公开的另一些实施例中，第一存储单元100和多个第二存储单元200即可依次堆叠构成三维存储器件1000b(如图2所示)，相比于三维存储器件1000，三维存储器件1000b的存储单元数量更多，因此三维存储器件1000b的存储密度更高，而且也不必在三维存储器件1000b的每一存储单元的存储阵列器件10中堆叠过多的存储层13，从而提高该三维存储器件1000b的空间利用率。
本公开的实施例中，在所述三维存储器件的制作过程中，第一存储单元100的存储阵列器件10与其CMOS器件20之间的接合、第二存储单元200的存储阵列器件10与其CMOS器件20之间的接合、第一存储单元100的存储阵列器件10与第二存储单元200的CMOS器件20之间的接合、及第二存储单元200的存储阵列器件10与其他第二存储单元200的CMOS器件20之间的接合所采用的方法包括Xtacking键合工艺。所述Xtacking键合工艺是指在同一个工艺步骤中实现不同器件之间的键合结构的对位键合，从而实现两个器件的电连接。通过使用Xtacking键合工艺，有利于选择更先进的制造工艺分别制造存储阵列器件和CMOS器件，降低制造工序的复杂度，从而可以让三维存储器件获取更高的I/O传输速度，更高的密度，以及更小的体积。
本公开还提供一种三维存储器，所述三维存储器包括上述的任一种三维存储器件，所述三维存储器具备了上述三维存储器件存储密度高、空间利用率高 等优点，同时也具备上述三维存储器件的其他结构特征和功能，此处不做赘述。
尽管已经示出和描述了本公开的实施例，本领域的普通技术人员可以理解：在不脱离本公开的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本公开的范围由权利要求及其等同物限定。

Claims (17)

  1. 一种三维存储器件，包括依次堆叠的至少两个存储单元，所述至少两个存储单元包括第一存储单元和堆叠于所述第一存储单元上的至少一个第二存储单元，每一存储单元包括：
    存储阵列器件和CMOS器件，所述存储阵列器件与所述CMOS器件堆叠设置且相互电连接；以及
    第一组触点，设于所述存储阵列器件背离所述CMOS器件的一侧，并与所述CMOS器件电连接；
    其中，所述第二存储单元还包括第二组触点，所述第二组触点设于所述第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧，并与所述第二存储单元的CMOS器件电连接；
    所述第一存储单元的存储阵列器件与相邻的第二存储单元的CMOS器件接合，并且所述第一存储单元的第一组触点与相邻的第二存储单元的第二组触点对应电连接；
    所述第二存储单元为一个时，所述第二存储单元为堆叠于所述第一存储单元上的外层第二存储单元，所述外层第二存储单元的第一组触点用于连接外部器件；
    所述第二存储单元为多个时，所述多个第二存储单元依次堆叠于所述第一存储单元上，相邻两个所述第二存储单元中，靠近所述第一存储单元的第二存储单元的第一组触点与远离所述第一存储单元的第二存储单元的第二组触点对应电连接，沿堆叠方向距离所述第一存储单元最远的第二存储单元定义为外层第二存储单元，所述外层第二存储单元的第一组触点用于连接外部器件。
  2. 如权利要求1所述的三维存储器件，其中，还包括隔离层及嵌设于所述隔离层中的阵列焊盘；所述隔离层覆盖所述外层第二存储单元背离所述第一存储单元的一侧及所述外层第二存储单元的第一组触点，所述阵列焊盘与所述外层第二存储单元的第一组触点对应电连接，所述阵列焊盘用于连接所述外部器件。
  3. 如权利要求2所述的三维存储器件，其中，还包括保护层，所述保护层覆盖于所述隔离层背离所述外层第二存储单元的一侧；
    其中，所述保护层在对应于所述阵列焊盘的位置开设有开口，所述阵列焊盘通过所述开口外露以用于连接所述外部器件。
  4. 如权利要求1至3任一项所述的三维存储器件，其中，所述存储阵列器件包括阵列衬底，每一存储单元的第一组触点设于对应的存储阵列器件的阵列衬底背离对应的CMOS器件的一侧；
    所述CMOS器件包括CMOS衬底，所述第二存储单元的第二组触点设于所述第二存储单元的CMOS衬底背离所述第二存储单元的存储阵列器件的一侧。
  5. 如权利要求4所述的三维存储器件，其中，每一存储单元还包括互连通道，所述互连通道设于所在存储单元的存储阵列器件与CMOS器件之中；
    所述互连通道分别与所在存储单元的第一组触点及CMOS器件电连接，以使所述第一组触点通过所述互连通道电连接于所述CMOS器件。
  6. 如权利要求5所述的三维存储器件，其中，所述第二存储单元还包括导电通道，所述导电通道贯穿所述第二存储单元的CMOS衬底，并分别与所述第二存储单元的第二组触点及CMOS器件电连接，以使所述第二组触点通过所述导电通道与所在第二存储单元的CMOS器件电连接。
  7. 如权利要求1至3任一项所述的三维存储器件，其中，所述第一存储单元的存储阵列器件和所述第二存储单元的存储阵列器件中均包括预定层数的存储层，所述预定层数的取值为大于0且小于500的整数。
  8. 一种三维存储器件的制造方法，包括：
    提供第一存储单元和第二存储单元，所述第一存储单元和所述第二存储单元均包括第一组触点、以及堆叠设置且相互电连接的存储阵列器件和CMOS器件，其中，所述第一组触点设于所述存储阵列器件背离所述CMOS器件的一侧并与所述CMOS器件电连接；
    对所述第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧进行减薄；
    在所述第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧形成第二组触点，其中，所述第二组触点与所述第二存储单元的CMOS器件电连接；以及
    将所述第二存储单元堆叠于所述第一存储单元的存储阵列器件背离所述第一存储单元的CMOS器件的一侧，并将所述第一存储单元的存储阵列器件与所述第二存储单元的CMOS器件接合，使所述第一存储单元的第一组触点与所述第二存储单元的第二组触点对应电连接。
  9. 如权利要求8所述的三维存储器件的制造方法，其中，所述第二存储单元为多个，所述三维存储器件的制造方法包括：
    将其中一个第二存储单元堆叠于所述第一存储单元的存储阵列器件背离所述第一存储单元的CMOS器件的一侧，并将所述其中一个第二存储单元的CMOS器件与所述第一存储单元的存储阵列器件接合，使所述其中一个第二存储单元的第二组触点与所述第一存储单元的第一组触点对应电连接；
    将其中另一个第二存储单元堆叠于外层第二存储单元的存储阵列器件背离所述外层第二存储单元的CMOS器件的一侧，并将所述其中另一个第二存储单元的CMOS器件与所述外层第二存储单元的存储阵列器件接合，使所述外层第二存储单元的第一组触点与所述其中另一个第二存储单元的第二组触点对应电连接，以及重复该步骤，直至将多个所述第二存储单元依次堆叠于所述第一存储单元上，其中，所述外层第二存储单元为堆叠于所述第一存储单元上且沿堆叠方向距离所述第一存储单元最远的第二存储单元。
  10. 如权利要求8或9所述的三维存储器件的制造方法，其中，在对所述 第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧进行减薄的步骤之前，所述三维存储器件的制造方法还包括：
    提供承载片，并将所述承载片贴合于所述第二存储单元的存储阵列器件背离所述第二存储单元的CMOS器件的一侧，使所述承载片覆盖所承载的第二存储单元的存储阵列器件背离所述第二存储单元的CMOS器件的一侧及所述第二存储单元的第一组触点。
  11. 如权利要求10所述的三维存储器件的制造方法，其中，在将所述第二存储单元堆叠到其他存储单元上且将所述第二存储单元的CMOS器件与所述其他存储单元的存储阵列器件接合之后，所述三维存储器件的制造方法还包括：
    去除所述承载片，使所述第二存储单元的第一组触点外露；
    其中，所述其他存储单元为所述第一存储单元或其余的所述第二存储单元。
  12. 如权利要求8或9所述的三维存储器件的制造方法，其中，还包括：
    在外层第二存储单元的存储阵列器件背离所述外层第二存储单元的CMOS器件的一侧形成隔离层，所述隔离层覆盖所述外层第二存储单元的存储阵列器件背离所述外层第二存储单元的CMOS器件的一侧及所述外层第二存储单元的第一组触点，其中，所述外层第二存储单元为堆叠于所述第一存储单元上且沿堆叠方向距离所述第一存储单元最远的第二存储单元；
    在所述隔离层内嵌设阵列焊盘，并使所述阵列焊盘与所述外层第二存储单元的第一组触点对应电连接。
  13. 如权利要求12所述的三维存储器件的制造方法，其中，还包括：在所述隔离层背离所述外层第二存储单元的一侧形成具有开口的保护层，使所述保护层覆盖所述隔离层，且所述开口暴露所述阵列焊盘。
  14. 如权利要求10所述的三维存储器件的制造方法，其中，所述将所述承载片贴合于所述第二存储单元的存储阵列器件背离所述第二存储单元的CMOS器件的一侧具体包括：
    在所述承载片朝向所述第二存储单元的一侧和/或所述第二存储单元的存储阵列器件背离所述第二存储单元的CMOS器件的一侧涂布加热固化胶、紫外光照射固化胶、加热分解胶或者激光分解胶中的任一种键合胶；以及
    通过临时键合工艺或者永久键合工艺将所述承载片键合于所述第二存储单元的存储阵列器件背离所述第二存储单元的CMOS器件的一侧。
  15. 如权利要求8所述的三维存储器件的制造方法，其中，每一存储单元还包括互连通道，设于所在存储单元的所述存储阵列器件与所述CMOS器件之中，且分别与所在存储单元的第一组触点及CMOS器件电连接，所述第一组触点通过所述互连通道电连接于所述CMOS器件，其中，所述CMOS器件包括CMOS衬底；
    所述在所述第二存储单元的CMOS器件背离所述第二存储单元的存储阵列器件的一侧形成第二组触点具体包括：
    在所述第二存储单元的CMOS衬底上形成贯穿所述CMOS衬底的通孔，所述通孔暴露所述第二存储单元的互连通道的至少一部分；
    在所述通孔内填充导电介质以形成导电通道，所述导电通道与所述第二存储单元的互连通道电连接；以及
    自所述导电通道远离所述第二存储单元的互连通道的一端形成所述第二存储单元的第二组触点，使所述第二组触点通过所述导电通道与所述第二存储单元的互连通道电连接。
  16. 如权利要求9所述的三维存储器件的制造方法，其中，所述第一存储单元的存储阵列器件与所述第一存储单元的CMOS器件之间的接合、所述第二存储单元的存储阵列器件与所述第二存储单元的CMOS器件之间的接合、所述第一存储单元的存储阵列器件与所述第二存储单元的CMOS器件之间的接合、及所述第二存储单元的存储阵列器件与其他所述第二存储单元的CMOS器件之间的接合所采用的方法包括Xtacking键合工艺。
  17. 一种三维存储器，包括如权利要求1至7任一项所述的三维存储器件。
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