CN102097327B - 双通道沟槽ldmos晶体管和bcd工艺 - Google Patents

双通道沟槽ldmos晶体管和bcd工艺 Download PDF

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CN102097327B
CN102097327B CN2010105833155A CN201010583315A CN102097327B CN 102097327 B CN102097327 B CN 102097327B CN 2010105833155 A CN2010105833155 A CN 2010105833155A CN 201010583315 A CN201010583315 A CN 201010583315A CN 102097327 B CN102097327 B CN 102097327B
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groove
trench
gate
semiconductor layer
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CN102097327A (zh
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雪克·玛力卡勒强斯瓦密
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

一个双通道沟槽LDMOS晶体管包括一个第一导电类型的衬底；一个形成在衬底上的第二导电类型的半导体层；一个形成在半导体层中的第一沟槽，沟槽栅极形成在第一沟槽的上部；一个形成在半导体层中第一沟槽附近的第一导电类型的本体区；一个形成在本体区中第一沟槽附近的第二导电类型的源极区；一个覆盖在本体区上方的平面栅极；一个第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来。平面栅极在本体区中构成一个横向通道，第一沟槽中的沟槽栅极在LDMOS晶体管的本体区中，构成一个垂直通道。

Description

双通道沟槽LDMOS晶体管和BCD工艺
技术领域
本发明涉及高压半导体器件及其制备过程，尤其是具有平面通道和沟槽通道的LDMOS晶体管，以及在BCD(双极CMOS和DMOS)制备过程中的沟槽隔离。
背景技术
横向双扩散金属氧化物半导体(Lateral double-diffused metal-oxide-semiconductor，简称LDMOS)晶体管凭借其高击穿电压的特点以及在低压器件中与互补金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，简称CMOS)技术的兼容性，通常用于高压器件(20至500伏)。一般来说，一个LDMOS晶体管包括一个多晶硅栅极、一个形成在P-型本体区中形成的N+源极区以及一个N+漏极区。N+漏极区与一个N漂移区在体区域形成的通道隔开，位于多晶硅栅极之下。众所周知，通过增大N漂移区的长度，可以相应地提高LDMOS晶体管的击穿电压。
双极-CMOS-DMOS(Bipolar-CMOS-DMOS，简称BCD)工艺技术是指，将双极器件、互补MOS(CMOS)器件和DMOS器件纳入到一个单一制备工艺流程中的半导体制备工艺。一般而言，双极器件适用于模拟电路，CMOS器件适用于数字电路，DMOS器件适用于管理片上或系统电源时处理高压和电流的要求。因此，BCD工艺常用于生产制造高压混合信号集成电路或模拟片上系统应用，以及在无线手持式电子设备和消费类电子产品中的特殊应用。
发明内容
依据本发明的一个实施例，双通道沟槽LDMOS晶体管包括一个第一导电类型的衬底；一个形成在衬底上的第二导电类型的半导体层；一个形成在半导体层中的第一沟槽，用沟槽电介质填充第一沟槽，并在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；一个形成在第一沟槽附近半导体层中的第一导电类型的本体区；一个形成在本体区中第一沟槽附近的第二导电类型的源极区；一个通过第二栅极介质层与半导体层绝缘的平面栅极，加在本体区上，所形成的源极区与平面栅极的第一边缘对齐；一个形成在半导体层中的第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来。平面栅极构成在源极区和漏极漂移区之间的本体区中的LDMOS晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成LDMOS晶体管的垂直通道。
具体而言，本发明提供一种双通道沟槽横向双扩散金属氧化物半导体晶体管，包括：
一个第一导电类型的衬底；
一个形成在衬底上的第二导电类型的半导体层；
一个形成在半导体层中的第一沟槽，用沟槽电介质填充第一沟槽，并在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；
一个形成在第一沟槽附近半导体层中的第一导电类型的本体区；
一个形成在本体区中，第一沟槽附近的第二导电类型的源极区；
一个通过第二栅极介质层与半导体层绝缘的平面栅极，加在本体区上，所形成的源极区与平面栅极的第一边缘对齐；以及
一个形成在半导体层中的第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来；
其中平面栅极构成在源极区和漏极漂移区之间的本体区中的横向双扩散金属氧化物半导体晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成横向双扩散金属氧化物半导体晶体管的垂直通道。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，第一沟槽仅仅延伸到半导体层中。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，第一沟槽穿过半导体层延伸到衬底中，沟槽栅极形成在第一沟槽的上部。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，还包括：
一个形成在第一沟槽下部的底部栅极电极，通过具有第二厚度的沟槽电介质，与第一沟槽的侧壁绝缘，第二厚度大于使沟槽栅极绝缘的第一栅极介质层的厚度，底部栅极电极电接触到源极电势上。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，还包括：
一个形成在半导体层中，并延伸到衬底中的第二沟槽，用沟槽电介质填充第二沟槽，其中第二沟槽包围着横向双扩散金属氧化物半导体晶体管的有源区，以隔离横向双扩散金属氧化物半导体晶体管。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，还包括一个沟槽栅极，形成在第二沟槽的上部，通过第三栅极介质层，与第二沟槽的侧壁绝缘，沟槽栅极处于电浮动状态或电连接到指定电势上，以便使第二沟槽中的沟槽栅极无效。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其中第三栅极介质层的厚度大于第一栅极介质层的厚度。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，还包括：
一个形成在半导体层中，并延伸到衬底中的第二沟槽，用沟槽电介质填充第二沟槽，一个形成在第二沟槽的上部，通过第三栅极介质层，与第二沟槽的侧壁绝缘的沟槽栅极，以及一个形成在第二沟槽的下部，通过沟槽电介质，与第二沟槽的侧壁绝缘的底部栅极电极，沟槽电介质的厚度大于第三栅极介质层的厚度，沟槽栅极处于电浮动状态或电连接到指定电势上，以便使第二沟槽中的沟槽栅极无效，底部栅极电极电连接到源极电势上；
其中第二沟槽包围着横向双扩散金属氧化物半导体晶体管的有源区，以隔离横向双扩散金属氧化物半导体晶体管。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，第三栅极介质层的厚度大于第一栅极介质层的厚度。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，漏极漂移区包括一个形成在半导体层中的第二导电类型的阱。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，漏极漂移区包括多个形成在半导体层中的第二导电类型的阱，这多个阱具有不同的掺杂浓度等级。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，还包括形成在平面栅极和漏极区之间的半导体层表面上或表面中的场氧化层或一步氧化层，平面栅极的第二边缘延伸到一部分场氧化层的上方或一步氧化层的上方。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，半导体层含有一个第二导电类型的外延层。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，第二半导体层还包括一个形成在衬底上的第二导电类型的掩埋层，外延层形成在掩埋层上。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，还包括多个形成在漏极漂移区中的沟槽叉指，用沟槽电介质填充多个沟槽叉指，多个沟槽叉指形成相互交错的沟槽和漏极区，沟槽栅极形成在每个沟槽叉指的上部，并通过第三栅极介质层，与沟槽叉指的侧壁绝缘，沟槽栅极电连接到源极电势上。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，第三栅极介质层的厚度大于第一栅极介质层的厚度。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，第一沟槽包括相互交错的沟槽区，这些沟槽区延伸到源极区和本体区中，形成沟槽栅极的延伸物。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，还包括：
一个位于源极区的本体接触区，以便电接触到本体区。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，第一导电类型为P-型，第二导电类型为N-型。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，还包括：
多个形成在漏极漂移区中的交替的N-型和P-型区，这多个交替的N-型和P-型区的掺杂浓度高于漏极漂移区的掺杂浓度，在漏极漂移区构成一个超级结结构。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，多个交替的N-型和P-型区包括第一N-型区、第二N-型区以及夹在第一和第二N-型区之间的P-型区，第一和第二N-型区自对准到平面栅极的第二边缘上，P-型区延伸到本体区。
上述的双通道沟槽横向双扩散金属氧化物半导体晶体管，多个交替的N-型和P-型区包括第一P-型区、第二P-型区以及夹在第一和第二P-型区之间的N-型区，第一和第二N-型区自对准到平面栅极的第二边缘上。
本发明还提供一种用于制备双通道沟槽横向双扩散金属氧化物半导体晶体管的方法，包括：
制备一个第一导电类型的衬底；
在衬底上形成一个第二导电类型的半导体层；
在半导体层中形成一个第一沟槽，用沟槽电介质填充第一沟槽；
在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；
在半导体层中第一沟槽附近形成一个第一导电类型的本体区；
在本体区中第一沟槽附近形成一个第二导电类型的源极区；
形成第二栅极介质层，覆盖在本体区上，在第二栅极介质层上形成一个与半导体层绝缘的平面栅极，形成源极区与平面栅极的第一边缘对齐；以及
在半导体层中形成一个第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来；
其中平面栅极构成在源极区和漏极漂移区之间的本体区中的横向双扩散金属氧化物半导体晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成横向双扩散金属氧化物半导体晶体管的垂直通道。
上述的方法，还包括：
在半导体层中制备第二沟槽，并延伸到衬底中，用沟槽电介质填充第二沟槽，第二沟槽包围着横向双扩散金属氧化物半导体晶体管的有源区，以隔离横向双扩散金属氧化物半导体晶体管。
本发明还提供一种由垂直沟槽横向双扩散金属氧化物半导体晶体管构成的半导体器件，垂直沟槽横向双扩散金属氧化物半导体晶体管包括：
一个第一导电类型的衬底；
一个形成在衬底上的第一导电类型的半导体层；
一个形成在半导体层中的第一沟槽，用沟槽电介质填充第一沟槽，并在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；
一个形成在半导体层中第一沟槽附近的第二导电类型的本体区；
一个形成在本体区中第一沟槽附近的第一导电类型的源极区；
一个通过第二栅极介质层与半导体层绝缘的平面栅极，加在本体区上，所形成的源极区与平面栅极的第一边缘对齐；
一个形成在半导体层中的第一导电类型的漏极漂移区；以及
一个形成在衬底背部的漏极电极；
其中平面栅极构成在源极区和漏极漂移区之间的本体区中的横向双扩散金属氧化物半导体晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成横向双扩散金属氧化物半导体晶体管的垂直通道。
上述的由垂直沟槽横向双扩散金属氧化物半导体晶体管构成的半导体器件，还包括一个形成在相同衬底的独立区域和相同的半导体层中的垂直沟槽MOS晶体管，该垂直沟槽MOS晶体管包括：
一个形成在半导体层中的第二沟槽，用沟槽电介质填充第二沟槽，第二沟槽栅极形成在第二沟槽中，通过第二栅极介质层，与第二沟槽的侧壁绝缘；
一个形成在第二沟槽附近的半导体层中的第二导电类型的第二本体区，第二本体区延伸到形成在第二沟槽中的第二沟槽栅极的底部边缘附近的深度；以及
一个形成在本体区中的、邻近第二沟槽的第一导电类型的源极区，源极区形成在本体区的顶部；
其中所形成的垂直沟槽MOS晶体管中，衬底作为垂直沟槽MOS晶体管的漏极区，半导体层作为漏极漂移区，第二沟槽栅极作为栅极电极。
阅读以下详细说明及附图之后，将更好地理解本发明。
附图说明
图1表示依据本发明的第一实施例，一个双通道沟槽LDMOS晶体管的横截面视图。
图2表示依据本发明的第二实施例，一个双通道沟槽LDMOS晶体管的横截面视图。
图3表示依据本发明的第三实施例，一个双通道沟槽LDMOS晶体管的俯视图。
图4表示依据本发明的第四实施例，一个双通道沟槽LDMOS晶体管的俯视图。
图5表示依据本发明的第五实施例，一个双通道沟槽LDMOS晶体管的俯视图。
图6表示依据本发明的第六实施例，一个双通道沟槽LDMOS晶体管的俯视图。
图7表示依据本发明的一个实施例，利用BCD工艺，采用深沟槽隔离技术制成的晶体管器件的横截面视图。
图8表示依据本发明的另一个实施例，利用BCD工艺，采用深沟槽隔离技术制成的晶体管器件的横截面视图。
图9表示依据本发明的一个实施例，一个采用漏极超级结结构的双通道沟槽LDMOS晶体管的横截面视图。
图10表示图9所示的LDMOS晶体管带有或不带有超级结结构时的电场分布。
图11表示依据本发明的一个可选实施例，一个采用漏极超级结结构的双通道沟槽LDMOS晶体管的横截面视图。
图12表示依据本发明的另一个实施例，一个采用底部漏极的双通道沟槽LDMOS晶体管的横截面视图。
图13表示依据本发明的一个实施例，一个可以与双通道器件集成的垂直沟槽MOS晶体管的横截面视图。
图14表示依据本发明的一个可选实施例，利用BCD工艺，采用深沟槽隔离技术制成的晶体管器件的横截面视图。
具体实施方式
按照本发明的原理，BCD(双极-CMOS-DMOS)制备工艺将填充氧化物的深沟槽与单一或堆积式栅极合并，作为深沟槽隔离技术使用，并用于有源栅极。在一些实施例中，将沟槽栅极用作垂直沟槽，将平面栅极用作横向通道，来制备双通道沟槽LDMOS。在其他实施例中，底部栅极电极电连接到源极电势上，以增强对所形成器件的屏蔽，并提高其击穿承受能力。在其他实施例中，超级结结构形成在LDMOS晶体管的漏极漂移区中，以降低漏极漂移区中的漏极电阻，并提高击穿电压。
通过使用带有沟槽栅极结构的深沟槽隔离技术，实现了低成本、高性能的BCD工艺。根据本发明所述的BCD工艺，可以节省多个掩膜，从而减少制备工艺的步骤和复杂性。带有深沟槽隔离技术的BCD工艺也实现了紧凑隔离，紧凑隔离与重掺杂的N-型掩埋层(NBL)一起，降低了寄生PNP增益，从而提高对闭锁的免疫能力。通过深沟槽隔离技术，以及利用在深沟槽底部的P通道阻绝植入，可以降低横向NPN增益。
由于双通道LDMOS晶体管的两个通道形成在传统LDMOS晶体管的同一区域中，实现了更高的通道密度。因此，LDMOS晶体管的通道电阻(Rds＊A)降低了一半。利用LDMOS晶体管中的垂直和横向通道，LDMOS晶体管的导通电阻降低了，LDMOS晶体管的性能得以提高。
当本发明所述的LDMOS晶体管在漏极区引入超级结结构时，晶体管的通道电阻(Rds＊A)会进一步降低。在一个实施例中，LDMOS的总电阻(Rds＊A)降低了70％以上。
(1)双通道沟槽LDMOS
依据本发明的一个方面，双通道沟槽LDMOS包括一个形成横向通道的平面栅极以及一个形成垂直通道的有源沟槽栅极。沟槽栅极形成在深氧化物填充的沟槽中，深氧化物填充的沟槽也可以用于LDMOS晶体管或相同工艺制备的其他器件的高压隔离。LDMOS晶体管的沟槽栅极形成一个屏蔽栅极沟槽(SGT)结构，实现了每个单位面积上较低的栅极至漏极电容，并提升了击穿性能。
在本发明的一些实施例中，通过将单一的浅沟槽栅极用作LDMOS晶体管的有源栅极，来制备双通道沟槽LDMOS晶体管。在其他实施例中，在沟槽中形成一个堆积式栅极结构，其底部栅极形成一个连接到源极电压上的电极，用于漏极区中的超级结效应，并提供屏蔽。
(a)单一的有源栅极
图1表示依据本发明的第一实施例，一个双通道沟槽LDMOS晶体管的横截面视图。参见图1，沟槽LDMOS晶体管10形成在P-型衬底12上，N-型掩埋层(N-type buriedlayer，简称NBL)14形成在沟槽LDMOS晶体管10上。N-型外延层16形成在掩埋层14上，晶体管的有源区就形成在掩埋层14中。N-型掩埋层14是可选的，通常选用它是为了改善器件的隔离性能和免除闭锁。在其他实施例中，可以省略N-型掩埋层14。可以通过标准的掩埋层植入工艺或一步外延工艺，形成NBL14。也就是说，首先在P衬底12上方生长一个重掺杂的N-型外延层，作为NBL14，然后在外延形成的NBL14上方生长一个比NBL14掺杂浓度轻的N-型外延层16。在本说明中，N-外延层16、N掩埋层14以及衬底12有时都称为“半导体层”。
深沟槽30形成在N-外延层16中，N-掩埋层14形成在衬底12中。用电介质材料填充沟槽30。在本实施例中，是用氧化硅填充沟槽30，因此称为“填充氧化物的沟槽”。在其他实施例中，也可使用其他电介质材料填充沟槽30。另外，沟槽栅极28形成在沟槽30的上部。在本实施例中，沟槽栅极28为多晶硅栅极。在其他实施例中，也可使用其他导电栅极材料。沟槽栅极28通过一个栅极介质层，与沟槽的侧壁绝缘。其特点是，所形成的栅极介质层与沟槽氧化物分离开来，以获得较高质量的氧化物。更确切地说，其特点是，利用热氧化，在沟槽侧壁上形成栅极介质层。这样一来，填充氧化物的沟槽30构成了沟槽LDMOS晶体管10的深沟槽隔离结构，沟槽栅极28构成了沟槽LDMOS晶体管10的有源栅极，这将在下文中详细说明。
沟槽LDMOS晶体管10包括一个平面栅极26，以及一个形成在P-型本体区22和N+漏极区24中形成的N+源极区23。在本实施例中，平面栅极26为多晶硅栅极，通过薄栅极氧化层25，与半导体层绝缘。在其他实施例中，可以利用其他导电栅极材料，制备平面栅极26。源极区23典型地自对准到平面栅极26的边缘上。在本实施例中，利用低压P-阱(Low voltage P-well，简称LVPW)技术在制备过程中，形成P-型本体区22。在其他实施例中，所形成的P-型本体区22穿过P-型植入物，自对准到平面栅极多晶硅26的边缘上。漏极区24形成在N-型区中，作为LDMOS晶体管的漏极接触区。在本实施例中，利用形成在高压N-阱(High voltage N-well，简称HVNW)18中的低压N-阱(Low voltage N-well，简称LVNW)20，制备漏极漂移区(Drain drift region)，高压N-阱(HVNW)18和低压N-阱(LVNW)20都形成在N-外延层16中。一般而言，低压N-阱20的掺杂浓度高于高压N-阱18。此处所用的掺杂方案有时是指分级掺杂的漏极，其中从本体区22向N+漏极区24掺杂浓度递增。在其他实施例中，可以利用一个或多个N-型区形成漏极漂移区。
在双通道沟槽LDMOS晶体管10中，所含的P+区用于电接触到本体区22上。在本实施例中，P+本体接触区形成在器件的z-方向上，也就是说，垂直于图1所示的横截面。因此，图1中并没有表示出P+本体接触区。因此，如图3-6所示，P+本体接触区可以作为交替的N+和P+区形成，或者P+区可以形成在岛或条纹中，这将在下文中详细说明。P+本体接触区的准确结构，对于本发明的实施并不起决定作用，它仅当P+本体接触区要与含有有源沟槽栅极的沟槽30分隔开时，是必需的。
在本实施例中，平面栅极26的末端部分延伸到场氧化层32上方。延伸到场氧化层32上方的平面栅极26，具有使平面栅极26边缘处的电场弛豫的效果。在其他实施例中，平面栅极可以延伸到一步氧化层或其他氧化物结构的上方。场氧化层在形成时消耗了半导体层最顶部的硅，从而场氧化层的一部分形成在半导体层中，由于一步氧化层面对着场氧化层，一步氧化层是指形成在半导体层上方的氧化层。然而在其他实施例中，平面栅极可以全部形成在栅极氧化层上，栅极氧化层形成在半导体层上，其末端不再延伸到任何其他氧化物结构上方。
沟槽LDMOS晶体管10还包括一个形成在半导体层上方的绝缘介质层35。在绝缘介质层中，制造一个向N+源极23的接触开口，并形成金属接头34作为到N+源极(如果可用，还可以到P+本体)的电接触。在绝缘介质层35中，制造另一个向N+漏极24的接触开口，并形成金属接头36作为到N+漏极的电接触。
因此，所形成的沟槽LDMOS晶体管10含有两个有源栅极和两个通道。平面栅极26在P-本体区22中半导体层(即N-外延层16)的表面附近，形成一个横向通道。电子从N+源极区23开始，流经P-本体区22中的横向通道，在水平方向上，流入N-外延层16、N-阱18和N-阱20所构成的漏极漂移区中，直到到达N+漏极区24为止。与此同时，沟槽栅极28在P-本体区22中沿沟槽30的一边，形成一个垂直通道。电子从N+源极区23开始，流经P-本体区22中的垂直通道，在垂直方向上，流入N-外延层16和N-掩埋层14。来自垂直通道的电子横向流经N-掩埋层14，然后向上穿过N-阱18、20，到达N+漏极区24。
假设平面栅极和垂直栅极的宽度相等，通过在LDMOS晶体管10中形成一个垂直通道和一个横向通道相结合，就可以直接降低多达50％的通道电阻Rds＊A。这两个通道可增加晶体管的通道宽度W，同时使通道电阻减半。
在一个实施例中，平面栅极和沟槽栅极电连接在一起，因此横向通道和垂直通道要同时开启和关闭。在另一个实施例中，可以分别控制平面栅极和沟槽栅极，因此每个栅极可以独立地开启和关闭。由于可以把晶体管的宽度任选地切换到增加或降低有源栅极的总宽度，因此，该结构称为“W切换”。更确切地说，当电流很高时，平面栅极和沟槽栅极都一致地开启和关闭。然而，当电流需要降低时，仅激活使用其中一个栅极即可。在电流很低时，可以任选使用平面栅极或沟槽栅极。在这种情况下，由于仅使用了总栅极的一部分(例如仅激活平面栅极)，电流很低时，也降低了栅极电容。
在图1中，形成在LDMOS晶体管10的漏极边缘上的沟槽30b中的沟槽栅极28b，可以用作相邻的沟槽LDMOS晶体管的有源栅极。当漏极边缘上的填充氧化物的沟槽30仅用于隔离时，要将沟槽栅极28b接地或连接到使栅极无效的电势上。
另外，在图1中，在沟槽30的底部，形成一个P-型通道终止区38。P-型通道终止区38具有降低横向NPN增益的作用，从而提高对闭锁的免疫能力。在本发明的其他实施例中，通道终止区38是可选的，也可以省略。
(b)堆积式栅极
图2表示依据本发明的第二实施例，一个双通道沟槽LDMOS晶体管的横截面视图。参见图2，除了在沟槽中使用了堆积式栅极结构之外，沟槽LDMOS晶体管100的制备方法与图1所示的沟槽LDMOS晶体管10的制备方法完全相同。两图中相似的元件在此不再赘述。在本实施例中，沟槽LDMOS晶体管100包括带有堆积式栅极结构的深填充氧化物的沟槽130。也就是说，每个填充氧化物的沟槽130都含有一个形成在沟槽上部的沟槽栅极128，以及一个形成在沟槽底部的底部栅极电极140。沟槽栅极128和底部栅极电极140相互绝缘。在一个实施例中，沟槽栅极和底部栅极电极都是由多晶硅制成的。在其他实施例中，也可以使用其他导电栅极材料。
更确切地说，当沟槽栅极128作为沟槽LDMOS晶体管100的有源栅极时，沟槽栅极128要连接到栅极电势。当不使用沟槽栅极作为有源栅极(例如沟槽栅极128b)时，沟槽栅极也可以接地或无效(例如连接到使栅极无效的电势上)。底部栅极电极140电连接到源极电势，在漏极区中实现了超级结效应。底部栅极电极140还具有增加沟槽栅极128对于N-掩埋层14处的漏极电势屏蔽作用。
因此在本实施例中，底部栅极电极140比沟槽栅极128薄，沟槽氧化物相邻底部栅极电极140时要更厚。较厚的沟槽氧化物提高了对于沟槽隔离结构的击穿承受力。底部栅极电极处的沟槽氧化物夹在底部栅极电极之间，底部栅极电极电连接到源极上，N-掩埋层14电连接到漏极上。因此，底部栅极附近的沟槽氧化物必须能够承受沟槽LDMOS晶体管漏极至源极的电压。
(c)沟槽和多晶硅栅极的布局图
图3表示依据本发明的第三实施例，一个双通道沟槽LDMOS晶体管的俯视图。参见图3，双通道沟槽LDMOS晶体管200含有平面栅极226、N+源极区223、P+本体接触区242以及N+漏极区224。P-型本体区(图中没有表示出)位于平面栅极226和源极223下方。漏极漂移区形成在N-外延层216中。漏极漂移区也可以含有其他N-型区，例如高压N-阱(HVNW)和/或低压N-阱(LVNW)(图3中没有表示出)。在本实施例中，含有一个沟槽栅极228b的沟槽230b，构成沟槽LDMOS晶体管200的隔离结构。沟槽230b包围着沟槽LDMOS晶体管200的有源区，将沟槽LDMOS晶体管200与形成在相同衬底上的其他器件隔离出来。沟槽栅极228b可以处于浮动状态。
在沟槽LDMOS晶体管200中，另一个沟槽230含有沟槽栅极228，用作LDMOS晶体管200中的有源栅极。用作有源栅极的沟槽栅极228，与用作隔离的沟槽栅极228b隔离开来。这样一来，所形成的双通道沟槽LDMOS晶体管200，就具有一个由平面栅极226构成的横向通道，以及一个由沟槽栅极228构成的垂直通道。
图4表示依据本发明的第四实施例，一个双通道沟槽LDMOS晶体管的俯视图。图4中所示的沟槽LDMOS晶体管250与图3所示的沟槽LDMOS晶体管200大致相同，两图中相似的元件在此不再赘述。参见图4，沟槽LDMOS晶体管250包括一个形成在晶体管漏极漂移区中的沟槽叉指260，以形成相互交错的沟槽和漏极漂移区。相互交错的沟槽叉指260的沟槽栅极262电连接到源极电势上。在这种情况下，超级结结构形成在沟槽LDMOS晶体管250的漏极中。这样形成的超级结结构允许使用更高的漏极掺杂等级，从而增加了击穿电压，降低了漏极-至源极电阻。在本实施例中，相互交错的沟槽叉指260的侧壁氧化物比栅极氧化物更厚，以便承载源极至漏极电压。必须要注意的是，沟槽叉指260与平面栅极226相互交叉的位置，平面栅极226实际上位于沟槽叉指260的上方，但是在图4中却是从相反的方向上表示的，以便更好地展示沟槽叉指260的结构。
在沟槽LDMOS晶体管250中，含有一个沟槽栅极228b的沟槽230b，构成沟槽LDMOS晶体管250的隔离结构。如上所述，沟槽栅极228b可以处于浮动状态。另外，隔离沟槽栅极228b的沟槽氧化物的厚度大于沟槽栅极中栅极氧化物层的厚度，所以沟槽230b的隔离结构可以承受更高的电压。
图5表示依据本发明的第五实施例，一个双通道沟槽LDMOS晶体管的俯视图。图6表示依据本发明的第六实施例，一个双通道沟槽LDMOS晶体管的俯视图。图5中所示的沟槽LDMOS晶体管300以及图6所示的沟槽LDMOS晶体管350，与图4所示的沟槽LDMOS晶体管250大致相同，这些图中相似的元件在此不再赘述。如上所述，在沟槽LDMOS晶体管中的P+本体接触区，用于电连接到晶体管的本体。参见图5，虽然P+本体接触区370形成在N+区323中，但是却与沟槽330的侧壁以及平面栅极226分离开。参见图6，所形成的P+本体接触区，在N+源极区323中作为分立的P+岛390。也可以利用其他适合电连接到LDMOS晶体管的P-本体区的方式制备沟槽LDMOS晶体管的本体接触区。
图6所示的LDMOS晶体管350进一步说明了，相互交错的填充氧化物的沟槽380的形成，以及沟槽栅极378延伸到相互交错的沟槽区，形成栅极延伸物。栅极延伸物增大了双通道LDMOS晶体管的通道宽度。
(2)BCD工艺中的沟槽隔离
依据本发明的另一方面，上述带有单一或堆积式栅极的填充氧化物的深沟槽，除了可用作有源栅极之外，也可用于BCD工艺中器件的深沟槽隔离技术。在这种情况下，BCD工艺中的单一的填充氧化物的沟槽结构可用于隔离全部器件(双极、CMOS、DMOS)，也用作双通道沟槽LDMOS晶体管的有源栅极。
图7表示依据本发明的一个实施例，利用BCD工艺，采用深沟槽隔离技术制成的晶体管器件的横截面视图。参见图7，BCD制备工艺形成LDMOS晶体管410、N-型金属氧化物半导体(NMOS)晶体管450、P-型金属氧化物半导体(PMOS)晶体管460和NPN双极结型晶体管(BJT)470，所有这些器件都位于带有N-掩埋层414和N-外延层416的P-型衬底412上。填充氧化物的沟槽430形成在半导体层中，并延伸到P-型衬底412中，以提供器件隔离。在本实施例中，单一的沟槽栅极428形成在沟槽430中。
在本实施例中，形成带有单一沟槽栅极的填充氧化物的沟槽430，用于在沟槽LDMOS晶体管410、MOS晶体管450和双极晶体管470之间提供隔离。由于在BCD制备工艺中，所有器件使用的都是同一种沟槽结构，因此无论沟槽栅极是否用作有源栅极，所有的氧化物填充的沟槽430都含有沟槽栅极428。当沟槽430仅用于器件隔离时，沟槽栅极428就成为一个伪栅极，处于电浮动或电连接到其他适当的电势上，使栅极无效。利用沟槽430，BCD工艺中形成的晶体管器件可以单独隔离。另外，沟槽430实现了紧凑隔离体系，从而提高了密度，降低了BCD工艺的成本。
在本实施例中，沟槽栅极428在LDMOS晶体管410中，构成一个到N-掩埋层414的垂直通道。因此，LDMOS晶体管410是一个带有平面栅极426和垂直栅极428的双通道沟槽LDMOS晶体管器件。在一个备用的实施例中，LDMOS晶体管410可以作为一个单一通道晶体管器件。可以仅用晶体管中的有源栅极制备平面栅极426。LDMOS晶体管的本体区(低压P-阱422)附近的沟槽栅极428，通过置于浮动状态或连接到使栅极无效的合适的电势上，可以使其失去活性。
在图7所示的LDMOS晶体管410中，通过低压P-阱422以及高压P-阱421，可以制成P-本体区。高压P-阱421的掺杂浓度低于低压P-阱422的掺杂浓度。
在本发明的其他实施例中，BCD工艺采用使用P-型掩埋层的器件，利用与上述相同的填充氧化物的沟槽结构隔离形成在P-掩埋层上方的器件。然而，在另一个实施例中，BCD工艺采用一个垂直MOSFET器件，例如垂直DMOS器件。利用填充氧化物的沟槽结构，作为垂直MOSFET器件的垂直通道的有源栅极。
图8表示依据本发明的一个可选实施例，利用BCD工艺，采用深沟槽隔离技术制成的晶体管器件的横截面视图。图8所示的BCD制备工艺与图7所示的BCD制备工艺基本相同，形成LDMOS晶体管、NMOS晶体管、PMOS晶体管和双极晶体管(图中没有表示出)，所有这些器件都位于带有N-掩埋层和N-外延层的P-型衬底上。图8所示的BCD制备工艺说明了，利用一个在填充氧化物沟槽中的堆积式栅极结构，提供额外的屏蔽。
(3)漏极超级结结构
依据本发明的另一方面，超级结结构形成在双通道沟槽LDMOS晶体管的漏极漂移区中，以降低LDMOS晶体管的漏极电阻，并提高击穿电压。在本发明的一个实施例中，超级结结构是利用N-型和P-型区的交替层构成的。由于选取超级结结构的N-型和P-型区合适的宽度，使它们在实际运行中完全耗尽，因此可以用比传统的漏极漂移区的掺杂等级还高的掺杂等级，制备超级结结构。耗尽超级结结构导致漏极漂移区的击穿电压增大，而较高的掺杂等级可以降低漏极电阻。
图9和图11表示依据本发明的不同实施例，带有形成在漏极漂移区中的超级结结构的双通道沟槽LDMOS晶体管的横截面视图。首先参见图9，双通道沟槽LDMOS晶体管500的制备方式与图1所示的双通道沟槽LDMOS晶体管10的制备方式基本相同，两图中类似的元件在此不再赘述。双通道沟槽LDMOS晶体管500包括一个形成横向通道的平面栅极526，以及一个形成垂直通道的沟槽栅极528。在本实施例中，平面栅极526并不延伸到场氧化层上方。
沟槽LDMOS晶体管500含有交替的N-型和P-型掺杂区，在沟槽LDMOS晶体管的漏极漂移区中构成超级结结构。在本实施例中，交替的N-型和P-型掺杂区包括第一N-型区590、第二N-型区594以及夹在第一和第二N-型区之间的P-型区592，这些区域都形成在高压N-阱518中，作为漏极漂移区。由于N-型区590和594以及P-型区592要在实际运行中耗尽，因此它们的掺杂浓度比下面的N-阱518的掺杂浓度更高。在本实施例中，P-型区592延伸到由低压P-阱522构成的P-本体区中。
在一个实施例中，利用多种能量的植入物，通过一个单一掩膜，制成交替的N-型和P-型区。另外，在另一个实施例中，所形成的交替的N-型和P-型区自对准到平面栅极526上。通过有角度的植入以及随后驱动，可以使P-型区592延伸到P-本体区522中。
因此，这样制成的位于漏极漂移区中的交替的N-型和P-型区，具有分散电场并提高LDMOS晶体管的击穿电压的作用。图10表示带有和不带有超级结结构的图9所示的沟槽LDMOS晶体管的电场分布图。曲线595表示不带有超级结结构的电场分布。电场在本体区中不断升高，直到本体区和N-外延层之间的P-N结达到临界电场为止。然后，电场沿漏极漂移区的长度方向降低。曲线597表示带有超级结结构的电场分布。电场为P-N结任一边上的掺杂等级的函数。如果掺杂等级较高，临界电场也会升高。因此，如图10所示，曲线597升高到本体区中的高电场等级。然后，由N-型和P-型区590、592、594构成的超级结区域，具有使电场均匀排布的作用，与曲线595所示的三角形状的电场相比，该电场分布呈现梯形形状，众所周知，电场下方的面积为晶体管的击穿电压。通过将电场分布转化成梯形形状，曲线597下方的面积会远大于曲线595下方的面积，因此带有超级结结构的沟槽LDMOS晶体管500的击穿电压也随之增大。
现在参见图11，双通道沟槽LDMOS晶体管600的制备方式，除了超级结结构之外，其他都与图9所示的沟槽LDMOS晶体管500的制备方式相同，两图中类似的元件在此不再赘述。在沟槽LDMOS晶体管600中，超级结结构是由第一P-型区690、第二P-型区694以及夹在第一和第二P-型区之间的N-型区692构成的，这些区域都形成在高压N-阱618中。在本实施例中，N-型区692的掺杂浓度高于P-型区。通过将N-型区692置于两个P-型区690和694之间，P-型区就像一个超级结一样，或者作为降低表面电场区，用于降低LDMOS晶体管的表面电场。因此，提高了沟槽LDMOS晶体管的击穿电压。在沟槽LDMOS晶体管600中，所形成的交替N-型和P-型区自对准到平面栅极626上。在本实施例中，N-型区692并没有延伸到高压N-阱(HVNW)618以外。在一个可选实施例中，例如通过有角度的植入代替自对准的N-型植入，植入到平面栅极626的边缘上，N-型区692可以延伸到高压N-阱以外。
(4)可选实施例
图12表示依据本发明的一个可选实施例，一个双通道沟槽LDMOS晶体管的横截面视图。参见图12，双通道沟槽LDMOS晶体管700形成在N+衬底712上，而不是像之前的实施例那样形成在P+衬底上。漏极区724形成在N+衬底712的背部，从而构成一个垂直LDMOS器件。沟槽LDMOS晶体管700包括一个平面栅极726、一个垂直栅极728以及N+源极区723，这些器件的形成方式与上述内容类似。
图13表示依据本发明的一个实施例，一个垂直沟槽MOS晶体管的横截面视图。参见图13，垂直沟槽MOS晶体管800形成在N+衬底812上，可以与一个双通道LDMOS晶体管器件(例如图12所示的晶体管700)集成。在垂直沟槽MOS晶体管800中，沟槽栅极828构成MOS晶体管的垂直栅极，并且垂直通道形成在低压P-阱(LVPW)822中。在垂直沟槽MOS晶体管800中，电流从源极区823开始，流经LVPW822中的通道区，流入N-外延层816、N-掩埋层814，然后流至N+衬底812。在衬底812的背部，制成漏极电极824。在表面上制成P+本体接头818，以便良好地接触源极金属819。
图14表示依据本发明的一个可选实施例，利用BCD工艺，采用深沟槽隔离技术制成的晶体管器件的横截面视图。图14中所示的晶体管器件的制备方式，与图8所示的晶体管器件大致相同，两图中相似的元件在此不再赘述。参见图14，深沟槽930B和930C用于器件隔离，它们延伸到P-型衬底912中。在本实施例中，深沟槽930B和930C并不包含任何沟槽栅极结构，而仅仅是填充氧化物的沟槽。在其他实施例中，如上所述，深沟槽可以包括单一沟槽栅极或堆积式栅极结构。与此同时，浅沟槽(例如沟槽930A)用于承载有源栅极。浅沟槽930A仅仅延伸到N-外延层中，并不延伸到P-型衬底中。
上述详细说明仅用于解释本发明的特殊实施例，并不作为局限。本发明范围内可能存在各种修正和变化。本发明的范围由所附的权利要求书限定。

Claims (21)

1.一种双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，包括：
一个第一导电类型的衬底；
一个形成在衬底上的第二导电类型的半导体层；
一个形成在半导体层中的第一沟槽，用沟槽电介质填充第一沟槽，并在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；
一个形成在第一沟槽附近半导体层中的第一导电类型的本体区；
一个形成在本体区中，第一沟槽附近的第二导电类型的源极区；
一个通过第二栅极介质层与半导体层绝缘的平面栅极，加在本体区上，所形成的源极区与平面栅极的第一边缘对齐；以及
一个形成在半导体层中的第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来，漏极漂移区包括多个形成在半导体层中的第二导电类型的阱，这多个阱具有不同的掺杂浓度等级；
其中平面栅极构成在源极区和漏极漂移区之间的本体区中的横向双扩散金属氧化物半导体晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成横向双扩散金属氧化物半导体晶体管的垂直通道。
2.权利要求1所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，第一沟槽仅仅延伸到半导体层中。
3.权利要求1所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，第一沟槽穿过半导体层延伸到衬底中，沟槽栅极形成在第一沟槽的上部。
4.权利要求3所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，还包括：
一个形成在第一沟槽下部的底部栅极电极，通过具有第二厚度的沟槽电介质，与第一沟槽的侧壁绝缘，第二厚度大于使沟槽栅极绝缘的第一栅极介质层的厚度，底部栅极电极电接触到源极电势上。
5.权利要求1所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，还包括形成在平面栅极和漏极区之间的半导体层表面上或表面中的场氧化层或半导体层上方的氧化层，平面栅极的第二边缘延伸到一部分场氧化层的上方或半导体层上方的氧化层的上方。
6.权利要求1所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，半导体层含有一个第二导电类型的外延层。
7.权利要求6所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，半导体层还包括一个形成在衬底上的第二导电类型的掩埋层，外延层形成在掩埋层上。
8.权利要求1所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，还包括：
一个位于源极区的本体接触区，以便电接触到本体区。
9.权利要求1所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，第一导电类型为P-型，第二导电类型为N-型。
10.权利要求9所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，还包括：
多个形成在漏极漂移区中的交替的N-型和P-型区，这多个交替的N-型和P-型区的掺杂浓度高于漏极漂移区的掺杂浓度，在漏极漂移区构成一个超级结结构。
11.权利要求10所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，多个交替的N-型和P-型区包括第一N-型区、第二N-型区以及夹在第一和第二N-型区之间的P-型区，第一和第二N-型区自对准到平面栅极的第二边缘上，P-型区延伸到本体区。
12.权利要求10所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，多个交替的N-型和P-型区包括第一P-型区、第二P-型区以及夹在第一和第二P-型区之间的N-型区，第一和第二N-型区自对准到平面栅极的第二边缘上。
13.一种双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，包括：
一个第一导电类型的衬底；
一个形成在衬底上的第二导电类型的半导体层；
一个形成在半导体层中的第一沟槽，用沟槽电介质填充第一沟槽，并在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；
一个形成在第一沟槽附近半导体层中的第一导电类型的本体区；
一个形成在本体区中，第一沟槽附近的第二导电类型的源极区；
一个通过第二栅极介质层与半导体层绝缘的平面栅极，加在本体区上，所形成的源极区与平面栅极的第一边缘对齐；以及
一个形成在半导体层中的第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来；
其中平面栅极构成在源极区和漏极漂移区之间的本体区中的横向双扩散金属氧化物半导体晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成横向双扩散金属氧化物半导体晶体管的垂直通道；
一个形成在半导体层中，并延伸到衬底中的第二沟槽，用沟槽电介质填充第二沟槽，其中第二沟槽包围着横向双扩散金属氧化物半导体晶体管的有源区，以隔离横向双扩散金属氧化物半导体晶体管。
14.权利要求13所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，还包括一个沟槽栅极，形成在第二沟槽的上部，通过第三栅极介质层，与第二沟槽的侧壁绝缘，沟槽栅极处于电浮动状态或电连接到指定电势上，以便使第二沟槽中的沟槽栅极无效。
15.权利要求14所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，其中第三栅极介质层的厚度大于第一栅极介质层的厚度。
16.一种双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，包括：
一个第一导电类型的衬底；
一个形成在衬底上的第二导电类型的半导体层；
一个形成在半导体层中的第一沟槽，用沟槽电介质填充第一沟槽，并在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；
一个形成在第一沟槽附近半导体层中的第一导电类型的本体区；
一个形成在本体区中，第一沟槽附近的第二导电类型的源极区；
一个通过第二栅极介质层与半导体层绝缘的平面栅极，加在本体区上，所形成的源极区与平面栅极的第一边缘对齐；以及
一个形成在半导体层中的第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来；
其中平面栅极构成在源极区和漏极漂移区之间的本体区中的横向双扩散金属氧化物半导体晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成横向双扩散金属氧化物半导体晶体管的垂直通道；
一个形成在半导体层中，并延伸到衬底中的第二沟槽，用沟槽电介质填充第二沟槽，一个形成在第二沟槽的上部，通过第三栅极介质层，与第二沟槽的侧壁绝缘的沟槽栅极，以及一个形成在第二沟槽的下部，通过沟槽电介质，与第二沟槽的侧壁绝缘的底部栅极电极，沟槽电介质的厚度大于第三栅极介质层的厚度，沟槽栅极处于电浮动状态或电连接到指定电势上，以便使第二沟槽中的沟槽栅极无效，底部栅极电极电连接到源极电势上；
其中第二沟槽包围着横向双扩散金属氧化物半导体晶体管的有源区，以隔离横向双扩散金属氧化物半导体晶体管。
17.权利要求16所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，第三栅极介质层的厚度大于第一栅极介质层的厚度。
18.一种双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，包括：
一个第一导电类型的衬底；
一个形成在衬底上的第二导电类型的半导体层；
一个形成在半导体层中的第一沟槽，用沟槽电介质填充第一沟槽，并在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；
一个形成在第一沟槽附近半导体层中的第一导电类型的本体区；
一个形成在本体区中，第一沟槽附近的第二导电类型的源极区；
一个通过第二栅极介质层与半导体层绝缘的平面栅极，加在本体区上，所形成的源极区与平面栅极的第一边缘对齐；以及
一个形成在半导体层中的第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来；
其中平面栅极构成在源极区和漏极漂移区之间的本体区中的横向双扩散金属氧化物半导体晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成横向双扩散金属氧化物半导体晶体管的垂直通道；
多个形成在漏极漂移区中的沟槽叉指，用沟槽电介质填充多个沟槽叉指，多个沟槽叉指形成相互交错的沟槽和漏极区，沟槽栅极形成在每个沟槽叉指的上部，并通过第三栅极介质层，与沟槽叉指的侧壁绝缘，沟槽栅极电连接到源极电势上。
19.权利要求18所述的双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，第三栅极介质层的厚度大于第一栅极介质层的厚度。
20.一种双通道沟槽横向双扩散金属氧化物半导体晶体管，其特征在于，包括：
一个第一导电类型的衬底；
一个形成在衬底上的第二导电类型的半导体层；
一个形成在半导体层中的第一沟槽，用沟槽电介质填充第一沟槽，并在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；
一个形成在第一沟槽附近半导体层中的第一导电类型的本体区；
一个形成在本体区中，第一沟槽附近的第二导电类型的源极区；
一个通过第二栅极介质层与半导体层绝缘的平面栅极，加在本体区上，所形成的源极区与平面栅极的第一边缘对齐；以及
一个形成在半导体层中的第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来；
其中平面栅极构成在源极区和漏极漂移区之间的本体区中的横向双扩散金属氧化物半导体晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成横向双扩散金属氧化物半导体晶体管的垂直通道；
第一沟槽包括相互交错的沟槽区，这些沟槽区延伸到源极区和本体区中，形成沟槽栅极的延伸物。
21.一种用于制备双通道沟槽横向双扩散金属氧化物半导体晶体管的方法，其特征在于，包括：
制备一个第一导电类型的衬底；
在衬底上形成一个第二导电类型的半导体层；
在半导体层中形成一个第一沟槽，用沟槽电介质填充第一沟槽；
在第一沟槽中形成一个沟槽栅极，通过第一栅极介质层，沟槽栅极与第一沟槽的侧壁绝缘；
在半导体层中第一沟槽附近形成一个第一导电类型的本体区；
在本体区中第一沟槽附近形成一个第二导电类型的源极区；
形成第二栅极介质层，覆盖在本体区上，在第二栅极介质层上形成一个与半导体层绝缘的平面栅极，形成源极区与平面栅极的第一边缘对齐；以及
在半导体层中形成一个第二导电类型的漏极区，漏极漂移区将漏极区和本体区间隔开来；
其中平面栅极构成在源极区和漏极漂移区之间的本体区中的横向双扩散金属氧化物半导体晶体管的横向通道，第一沟槽中的沟槽栅极在本体区中，沿源极区和半导体层之间的第一沟槽的侧壁，构成横向双扩散金属氧化物半导体晶体管的垂直通道；
在半导体层中制备第二沟槽，并延伸到衬底中，用沟槽电介质填充第二沟槽，第二沟槽包围着横向双扩散金属氧化物半导体晶体管的有源区，以隔离横向双扩散金属氧化物半导体晶体管。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412881B2 (en) 2012-07-31 2016-08-09 Silanna Asia Pte Ltd Power device integration on a common substrate
US10290702B2 (en) 2012-07-31 2019-05-14 Silanna Asia Pte Ltd Power device on bulk substrate

Families Citing this family (164)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009352A (ja) * 2009-06-24 2011-01-13 Renesas Electronics Corp 半導体装置およびその製造方法ならびにそれを用いた電源装置
US8174070B2 (en) * 2009-12-02 2012-05-08 Alpha And Omega Semiconductor Incorporated Dual channel trench LDMOS transistors and BCD process with deep trench isolation
US8431457B2 (en) 2010-03-11 2013-04-30 Alpha And Omega Semiconductor Incorporated Method for fabricating a shielded gate trench MOS with improved source pickup layout
WO2011148427A1 (en) * 2010-05-27 2011-12-01 Fuji Electric Co., Ltd. Mos-driven semiconductor device and method for manufacturing mos-driven semiconductor device
WO2011161748A1 (ja) 2010-06-21 2011-12-29 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8618627B2 (en) * 2010-06-24 2013-12-31 Fairchild Semiconductor Corporation Shielded level shift transistor
US20120007140A1 (en) * 2010-07-12 2012-01-12 National Semiconductor Corporation ESD self protecting NLDMOS device and NLDMOS array
US9064712B2 (en) * 2010-08-12 2015-06-23 Freescale Semiconductor Inc. Monolithic microwave integrated circuit
US8896064B2 (en) * 2010-10-18 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge protection circuit
US9893209B2 (en) * 2010-12-02 2018-02-13 Alpha And Omega Semiconductor Incorporated Cascoded high voltage junction field effect transistor
US8299547B2 (en) * 2011-01-03 2012-10-30 International Business Machines Corporation Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates
US8901676B2 (en) 2011-01-03 2014-12-02 International Business Machines Corporation Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage (Vb), a method of forming an LEDMOSFET, and a silicon-controlled rectifier (SCR) incorporating a complementary pair of LEDMOSFETs
SE535621C2 (sv) * 2011-03-08 2012-10-16 Eklund Innovation K Halvledarkomponent bestående av en lateral JFET kombinerad med en vertikal JFET
US8643101B2 (en) * 2011-04-20 2014-02-04 United Microelectronics Corp. High voltage metal oxide semiconductor device having a multi-segment isolation structure
CN103688363B (zh) 2011-05-18 2017-08-04 威世硅尼克斯公司 半导体器件
US8921933B2 (en) * 2011-05-19 2014-12-30 Macronix International Co., Ltd. Semiconductor structure and method for operating the same
US8754476B2 (en) * 2011-07-19 2014-06-17 Richtek Technology Corporation, R.O.C. High voltage device and manufacturing method thereof
US8829603B2 (en) 2011-08-18 2014-09-09 Alpha And Omega Semiconductor Incorporated Shielded gate trench MOSFET package
US8999769B2 (en) * 2012-07-18 2015-04-07 Globalfoundries Singapore Pte. Ltd. Integration of high voltage trench transistor with low voltage CMOS transistor
US9054133B2 (en) 2011-09-21 2015-06-09 Globalfoundries Singapore Pte. Ltd. High voltage trench transistor
US9356012B2 (en) * 2011-09-23 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage ESD protection apparatus
CN102354686A (zh) * 2011-11-17 2012-02-15 上海先进半导体制造股份有限公司 60v高边ldnmos结构及其制造方法
CN102394246B (zh) * 2011-11-29 2017-12-22 上海华虹宏力半导体制造有限公司 可升级的横向双扩散金属氧化物半导体晶体管及制造方法
CN102496575A (zh) * 2011-12-23 2012-06-13 上海先进半导体制造股份有限公司 60v非对称高压pmos结构及其制造方法
US8637370B2 (en) 2012-01-19 2014-01-28 Globalfoundries Singapore Pte. Ltd. Integration of trench MOS with low voltage integrated circuits
KR101899556B1 (ko) 2012-02-03 2018-10-04 에스케이하이닉스 시스템아이씨 주식회사 Ｂｃｄｍｏｓ 소자 및 그 제조방법
TWI548090B (zh) * 2012-02-07 2016-09-01 聯華電子股份有限公司 半導體裝置及其製作方法
US9093296B2 (en) * 2012-02-09 2015-07-28 United Microelectronics Corp. LDMOS transistor having trench structures extending to a buried layer
CN103390645B (zh) * 2012-05-08 2016-08-03 上海韦尔半导体股份有限公司 横向扩散金属氧化物半导体晶体管及其制作方法
JP2013247188A (ja) * 2012-05-24 2013-12-09 Toshiba Corp 半導体装置
US9041105B2 (en) * 2012-07-20 2015-05-26 International Business Machines Corporation Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure
US8686505B2 (en) * 2012-07-27 2014-04-01 Infineon Technologies Dresden Gmbh Lateral semiconductor device and manufacturing method therefor
US8847310B1 (en) 2012-07-31 2014-09-30 Azure Silicon LLC Power device integration on a common substrate
US8674440B2 (en) 2012-07-31 2014-03-18 Io Semiconductor Inc. Power device integration on a common substrate
KR101585537B1 (ko) 2012-07-31 2016-01-14 실라나 아시아 피티이 리미티드 공통 기판 상의 파워 소자 집적
US8928116B2 (en) * 2012-07-31 2015-01-06 Silanna Semiconductor U.S.A., Inc. Power device integration on a common substrate
US8994105B2 (en) 2012-07-31 2015-03-31 Azure Silicon LLC Power device integration on a common substrate
US8916440B2 (en) 2012-08-03 2014-12-23 International Business Machines Corporation Semiconductor structures and methods of manufacture
TWI467765B (zh) * 2012-08-20 2015-01-01 Vanguard Int Semiconduct Corp 半導體裝置及其製造方法
CN103681791B (zh) * 2012-09-05 2016-12-21 上海华虹宏力半导体制造有限公司 Nldmos器件及制造方法
JP5787853B2 (ja) * 2012-09-12 2015-09-30 株式会社東芝 電力用半導体装置
CN104685614B (zh) 2012-10-16 2017-11-14 旭化成微电子株式会社 场效应晶体管以及半导体装置
CN103779329B (zh) * 2012-10-23 2016-11-16 无锡华润上华半导体有限公司 用于mosfet噪声测试的半导体测试结构
CN103811402B (zh) * 2012-11-15 2016-08-17 上海华虹宏力半导体制造有限公司 一种超高压bcd工艺的隔离结构制作工艺方法
CN103855212B (zh) * 2012-12-04 2018-10-23 中芯国际集成电路制造(上海)有限公司 一种横向扩散半导体器件
US9337178B2 (en) 2012-12-09 2016-05-10 Semiconductor Components Industries, Llc Method of forming an ESD device and structure therefor
US20140167173A1 (en) * 2012-12-14 2014-06-19 Broadcom Corporation Increasing the breakdown voltage of a metal oxide semiconductor device
TWI476926B (zh) * 2012-12-25 2015-03-11 Richtek Technology Corp 橫向雙擴散金屬氧化物半導體元件製造方法
CN103050541B (zh) * 2013-01-06 2015-08-19 上海华虹宏力半导体制造有限公司 一种射频ldmos器件及其制造方法
US9324838B2 (en) 2013-01-11 2016-04-26 Stmicroelectronics S.R.L. LDMOS power semiconductor device and manufacturing method of the same
US9117845B2 (en) * 2013-01-25 2015-08-25 Fairchild Semiconductor Corporation Production of laterally diffused oxide semiconductor (LDMOS) device and a bipolar junction transistor (BJT) device using a semiconductor process
US9245960B2 (en) 2013-02-08 2016-01-26 Globalfoundries Inc. Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered airgap field plates
CN103165678B (zh) * 2013-03-12 2015-04-15 电子科技大学 一种超结ldmos器件
JP6182921B2 (ja) * 2013-03-21 2017-08-23 富士電機株式会社 Ｍｏｓ型半導体装置
US9041144B2 (en) 2013-05-17 2015-05-26 Micron Technology, Inc. Integrated circuitry comprising transistors with broken up active regions
US9171903B2 (en) * 2013-05-17 2015-10-27 Micron Technology, Inc. Transistors having features which preclude straight-line lateral conductive paths from a channel region to a source/drain region
CN104241353B (zh) * 2013-06-07 2017-06-06 上海华虹宏力半导体制造有限公司 射频ldmos器件及其制造方法
US8981475B2 (en) * 2013-06-18 2015-03-17 International Business Machines Corporation Lateral diffusion metal oxide semiconductor (LDMOS)
TWI511293B (zh) * 2013-06-24 2015-12-01 Chip Integration Tech Co Ltd 雙溝渠式ｍｏｓ電晶體結構及其製造方法
US9059281B2 (en) 2013-07-11 2015-06-16 International Business Machines Corporation Dual L-shaped drift regions in an LDMOS device and method of making the same
US10199459B2 (en) * 2013-07-19 2019-02-05 Great Wall Semiconductor Corporation Superjunction with surrounding lightly doped drain region
KR102115619B1 (ko) * 2013-09-06 2020-05-27 에스케이하이닉스 시스템아이씨 주식회사 반도체 장치 및 그 제조방법
CN103489915B (zh) * 2013-09-16 2016-05-11 电子科技大学 一种横向高压超结功率半导体器件
US9224854B2 (en) * 2013-10-03 2015-12-29 Texas Instruments Incorporated Trench gate trench field plate vertical MOSFET
US8987820B1 (en) * 2013-10-11 2015-03-24 Vanguard International Semiconductor Corporation Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same
CN104617139B (zh) * 2013-11-05 2017-08-08 上海华虹宏力半导体制造有限公司 Ldmos器件及制造方法
US9431531B2 (en) 2013-11-26 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having drain side contact through buried oxide
CN104681610B (zh) * 2013-12-03 2017-08-08 上海华虹宏力半导体制造有限公司 Nldmos器件
US9245998B2 (en) 2013-12-29 2016-01-26 Texas Instruments Incorporated High voltage multiple channel LDMOS
CN103762241B (zh) * 2014-01-02 2016-08-24 杭州电子科技大学 一种梳状栅纵向沟道soi ldmos单元
US9570437B2 (en) * 2014-01-09 2017-02-14 Nxp B.V. Semiconductor die, integrated circuits and driver circuits, and methods of maufacturing the same
US9450076B2 (en) 2014-01-21 2016-09-20 Stmicroelectronics S.R.L. Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof
CN104810398B (zh) * 2014-01-29 2018-06-22 世界先进积体电路股份有限公司 半导体装置及其制造方法
JP2015176974A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置
DE102014104589B4 (de) * 2014-04-01 2017-01-26 Infineon Technologies Ag Halbleitervorrichtung und integrierte Schaltung
US9263436B2 (en) * 2014-04-30 2016-02-16 Vanguard International Semiconductor Corporation Semiconductor device and method for fabricating the same
KR20160001913A (ko) * 2014-06-27 2016-01-07 에스케이하이닉스 주식회사 전력용 전자 소자
CN105448983B (zh) * 2014-07-30 2020-07-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US9520367B2 (en) 2014-08-20 2016-12-13 Freescale Semiconductor, Inc. Trenched Faraday shielding
US9331196B2 (en) * 2014-10-02 2016-05-03 Nuvoton Technology Corporation Semiconductor device
US9281379B1 (en) 2014-11-19 2016-03-08 International Business Machines Corporation Gate-all-around fin device
KR102168302B1 (ko) * 2014-11-21 2020-10-22 삼성전자주식회사 3차원 채널을 이용하는 반도체 장치
CN105789298B (zh) * 2014-12-19 2019-06-07 无锡华润上华科技有限公司 横向绝缘栅双极型晶体管及其制造方法
KR102286012B1 (ko) * 2015-02-17 2021-08-05 에스케이하이닉스 시스템아이씨 주식회사 전력용 집적소자와, 이를 포함하는 전자장치 및 전자시스템
US9520492B2 (en) * 2015-02-18 2016-12-13 Macronix International Co., Ltd. Semiconductor device having buried layer
US9837411B2 (en) * 2015-07-14 2017-12-05 Tower Semiconductors Ltd. Semiconductor die with a metal via
US10153213B2 (en) 2015-08-27 2018-12-11 Semiconductor Components Industries, Llc Process of forming an electronic device including a drift region, a sinker region and a resurf region
US9647109B2 (en) * 2015-09-07 2017-05-09 Kabushiki Kaisha Toshiba Semiconductor device
JP2017055102A (ja) * 2015-09-10 2017-03-16 株式会社豊田自動織機 トレンチゲート型半導体装置及びその製造方法
US10217733B2 (en) 2015-09-15 2019-02-26 Semiconductor Components Industries, Llc Fast SCR structure for ESD protection
US9543299B1 (en) * 2015-09-22 2017-01-10 Texas Instruments Incorporated P-N bimodal conduction resurf LDMOS
CN106571388B (zh) * 2015-10-08 2018-10-12 无锡华润上华科技有限公司 具有resurf结构的横向扩散金属氧化物半导体场效应管
US9755066B2 (en) 2015-11-30 2017-09-05 Infineon Technologies Austria Ag Reduced gate charge field-effect transistor
US9660073B1 (en) * 2015-12-17 2017-05-23 Vanguard International Semiconductor Corporation High-voltage semiconductor device and method for manufacturing the same
US9905688B2 (en) 2016-01-28 2018-02-27 Texas Instruments Incorporated SOI power LDMOS device
US9680473B1 (en) * 2016-02-18 2017-06-13 International Business Machines Corporation Ultra dense vertical transport FET circuits
JP6695188B2 (ja) * 2016-03-29 2020-05-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6688653B2 (ja) * 2016-03-30 2020-04-28 エイブリック株式会社 半導体装置および半導体装置の製造方法
JP6651957B2 (ja) * 2016-04-06 2020-02-19 株式会社デンソー 半導体装置およびその製造方法
US10388781B2 (en) * 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
CN107452800B (zh) * 2016-05-24 2021-02-26 马克西姆综合产品公司 Ldmos晶体管及相关系统和方法
US9893070B2 (en) * 2016-06-10 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabrication method therefor
KR102495452B1 (ko) 2016-06-29 2023-02-02 삼성전자주식회사 반도체 장치
US9761707B1 (en) * 2016-08-19 2017-09-12 Nxp Usa, Inc. Laterally diffused MOSFET with isolation region
US10978869B2 (en) 2016-08-23 2021-04-13 Alpha And Omega Semiconductor Incorporated USB type-C load switch ESD protection
US10103140B2 (en) * 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
US10211784B2 (en) 2016-11-03 2019-02-19 Nxp Usa, Inc. Amplifier architecture reconfiguration
CN106449759B (zh) * 2016-11-11 2019-08-02 电子科技大学 隔离型ldmos结构及其制造方法
US9941171B1 (en) * 2016-11-18 2018-04-10 Monolithic Power Systems, Inc. Method for fabricating LDMOS with reduced source region
KR102140358B1 (ko) * 2016-12-23 2020-08-03 매그나칩 반도체 유한회사 잡음 감소를 위한 분리 구조를 갖는 통합 반도체 소자
CN108242467B (zh) * 2016-12-27 2020-05-22 无锡华润上华科技有限公司 Ldmos器件及其制作方法
JP6726092B2 (ja) * 2016-12-28 2020-07-22 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US9842896B1 (en) * 2017-02-17 2017-12-12 Vanguard International Semiconductor Corporation Ultra-high voltage devices and method for fabricating the same
US9923059B1 (en) 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
CN108807512B (zh) * 2017-05-05 2021-06-04 世界先进积体电路股份有限公司 半导体装置及其形成方法
US10269951B2 (en) * 2017-05-16 2019-04-23 General Electric Company Semiconductor device layout and method for forming same
KR102227666B1 (ko) * 2017-05-31 2021-03-12 주식회사 키 파운드리 고전압 반도체 소자
TWI614891B (zh) * 2017-07-03 2018-02-11 世界先進積體電路股份有限公司 高壓半導體裝置
CN109216175B (zh) * 2017-07-03 2021-01-08 无锡华润上华科技有限公司 半导体器件的栅极结构及其制造方法
US10037988B1 (en) * 2017-08-24 2018-07-31 Globalfoundries Singapore Pte. Ltd. High voltage PNP using isolation for ESD and method for producing the same
TWI670799B (zh) * 2017-09-06 2019-09-01 世界先進積體電路股份有限公司 半導體裝置及其製造方法
US10262997B2 (en) 2017-09-14 2019-04-16 Vanguard International Semiconductor Corporation High-voltage LDMOSFET devices having polysilicon trench-type guard rings
US10388649B2 (en) 2017-10-04 2019-08-20 Vanguard International Semiconductor Corporation Semiconductor devices and methods for manufacturing the same
CN108565286B (zh) * 2017-12-26 2021-01-29 西安电子科技大学 高k介质沟槽横向双扩散金属氧化物元素半导体场效应管及其制作方法
WO2019156695A1 (en) 2018-02-09 2019-08-15 Didrew Technology (Bvi) Limited Method of manufacturing fan out package with carrier-less molded cavity
WO2019160566A1 (en) 2018-02-15 2019-08-22 Didrew Technology (Bvi) Limited Method of simultaneously fabricating multiple wafers on large carrier with warpage control stiffener
WO2019160570A1 (en) * 2018-02-15 2019-08-22 Didrew Technolgy (Bvi) Limited System and method of fabricating tim-less hermetic flat top his/emi shield package
US10680099B2 (en) * 2018-02-19 2020-06-09 Globalfoundries Singapore Pte. Ltd. Isolated laterally diffused metal oxide semiconductor (LDMOS) transistor having low drain to body capacitance
KR102359373B1 (ko) * 2018-06-11 2022-02-08 에스케이하이닉스 시스템아이씨 주식회사 고전압 반도체소자의 제조방법
TWI656646B (zh) * 2018-06-12 2019-04-11 立錡科技股份有限公司 高壓元件及其製造方法
CN110634949B (zh) * 2018-06-22 2023-03-28 立锜科技股份有限公司 高压元件及其制造方法
CN109148444B (zh) * 2018-08-22 2020-10-27 电子科技大学 Bcd半导体器件及其制造方法
US11289570B2 (en) 2018-08-24 2022-03-29 Semiconductor Components Industries, Llc Semiconductor device having optimized drain termination and method therefor
US11296075B2 (en) 2018-08-31 2022-04-05 Texas Instruments Incorporated High reliability polysilicon components
US11069804B2 (en) * 2018-08-31 2021-07-20 Alpha And Omega Semiconductor (Cayman) Ltd. Integration of HVLDMOS with shared isolation region
CN109216352B (zh) * 2018-09-13 2020-10-27 电子科技大学 一种bcd半导体集成器件
US10770584B2 (en) 2018-11-09 2020-09-08 Texas Instruments Incorporated Drain extended transistor with trench gate
TWI673880B (zh) * 2018-11-21 2019-10-01 新唐科技股份有限公司 橫向擴散金氧半導體裝置
CN109860300B (zh) * 2018-12-27 2022-04-22 北京顿思集成电路设计有限责任公司 半导体器件及其制造方法
CN109830523B (zh) * 2019-01-08 2021-08-24 上海华虹宏力半导体制造有限公司 Nldmos器件及其制造方法
US11476326B2 (en) 2019-01-21 2022-10-18 Nissan Motor Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US10886418B2 (en) * 2019-02-21 2021-01-05 Texas Instruments Incorporated Split-gate JFET with field plate
CN110534513B (zh) * 2019-09-06 2022-02-08 电子科技大学 一种高低压集成器件及其制造方法
US20210072304A1 (en) * 2019-09-09 2021-03-11 Analog Devices International Unlimited Company Semiconductor device configured for gate dielectric monitoring
CN112530805B (zh) * 2019-09-19 2022-04-05 无锡华润上华科技有限公司 横向双扩散金属氧化物半导体器件及制作方法、电子装置
FR3103318B1 (fr) * 2019-11-15 2021-12-10 St Microelectronics Crolles 2 Sas Circuit intégré comprenant un transistor nldmos et procédé de fabrication d’un tel circuit intégré
US11552190B2 (en) 2019-12-12 2023-01-10 Analog Devices International Unlimited Company High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region
US10910478B1 (en) 2020-03-04 2021-02-02 Shuming Xu Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance
CN113496939A (zh) * 2020-04-03 2021-10-12 无锡华润上华科技有限公司 一种半导体器件及其制作方法
CN111477680A (zh) * 2020-04-23 2020-07-31 西安电子科技大学 双通道均匀电场调制横向双扩散金属氧化物宽带隙半导体场效应管及制作方法
CN111477681A (zh) * 2020-04-23 2020-07-31 西安电子科技大学 双通道均匀电场调制横向双扩散金属氧化物元素半导体场效应管及制作方法
US11024749B1 (en) * 2020-06-15 2021-06-01 Taiwan Semiconductor Manufacturing Company Limited Dual channel transistor device and methods of forming the same
CN111682024B (zh) * 2020-06-30 2022-12-02 电子科技大学 一种bcd半导体器件
US11380759B2 (en) * 2020-07-27 2022-07-05 Globalfoundries U.S. Inc. Transistor with embedded isolation layer in bulk substrate
CN112436057B (zh) * 2020-10-15 2021-09-17 上海芯导电子科技股份有限公司 一种低导通电阻mos器件及制备工艺
TWI818371B (zh) * 2021-01-12 2023-10-11 立錡科技股份有限公司 高壓元件及其製造方法
US11810976B2 (en) 2021-02-18 2023-11-07 Semiconductor Components Industries, Llc Semiconductor device
CN113113495B (zh) * 2021-04-12 2022-07-05 东南大学 一种具有交错槽栅结构的横向双扩散金属氧化物半导体器件
CN113394291A (zh) * 2021-04-29 2021-09-14 电子科技大学 横向功率半导体器件
TWI798809B (zh) * 2021-06-18 2023-04-11 力晶積成電子製造股份有限公司 半導體結構以及其形成方法
KR20230144201A (ko) * 2022-04-07 2023-10-16 주식회사 키파운드리 아이솔레이션 항복 전압 향상을 위한 반도체 소자
CN114937695B (zh) * 2022-07-25 2022-10-21 北京芯可鉴科技有限公司 双沟道ldmos器件及其制备方法以及芯片
CN115662900A (zh) * 2022-10-21 2023-01-31 苏州华太电子技术股份有限公司 超级结ldmos器件的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1641886A (zh) * 2004-01-16 2005-07-20 崇贸科技股份有限公司 具有一分开井结构的隔离的高电压ldmos晶体管
EP1703566A1 (en) * 2005-03-18 2006-09-20 AMI Semiconductor Belgium BVBA MOS device having at least two channel regions
CN101180737A (zh) * 2003-12-30 2008-05-14 飞兆半导体公司 功率半导体器件及制造方法
CN101714577A (zh) * 2008-10-01 2010-05-26 东部高科股份有限公司 横向dmos晶体管及其制造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63122261A (ja) * 1986-11-12 1988-05-26 Mitsubishi Electric Corp 半導体装置の製造方法
JP3324832B2 (ja) * 1993-07-28 2002-09-17 三菱電機株式会社 半導体装置およびその製造方法
US5736753A (en) * 1994-09-12 1998-04-07 Hitachi, Ltd. Semiconductor device for improved power conversion having a hexagonal-system single-crystal silicon carbide
US5646063A (en) * 1996-03-28 1997-07-08 Advanced Micro Devices, Inc. Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US20080197408A1 (en) * 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
TW563244B (en) 2002-10-25 2003-11-21 Vanguard Int Semiconduct Corp Deep trench isolation structure of high voltage device and its manufacturing method
US7015115B1 (en) 2003-02-20 2006-03-21 Newport Fab, Llc Method for forming deep trench isolation and related structure
US7087491B1 (en) 2003-02-28 2006-08-08 Micrel, Inc. Method and system for vertical DMOS with slots
US7154159B2 (en) 2004-02-24 2006-12-26 Nanya Technology Corporation Trench isolation structure and method of forming the same
US7291541B1 (en) 2004-03-18 2007-11-06 National Semiconductor Corporation System and method for providing improved trench isolation of semiconductor devices
US7087959B2 (en) * 2004-08-18 2006-08-08 Agere Systems Inc. Metal-oxide-semiconductor device having an enhanced shielding structure
US7453119B2 (en) 2005-02-11 2008-11-18 Alphs & Omega Semiconductor, Ltd. Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact
US7468307B2 (en) 2005-06-29 2008-12-23 Infineon Technologies Ag Semiconductor structure and method
WO2009055140A1 (en) * 2007-10-26 2009-04-30 Hvvi Semiconductors, Inc. Semiconductor structure and method of manufacture
US7851314B2 (en) * 2008-04-30 2010-12-14 Alpha And Omega Semiconductor Incorporated Short channel lateral MOSFET and method
US8174070B2 (en) 2009-12-02 2012-05-08 Alpha And Omega Semiconductor Incorporated Dual channel trench LDMOS transistors and BCD process with deep trench isolation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101180737A (zh) * 2003-12-30 2008-05-14 飞兆半导体公司 功率半导体器件及制造方法
CN1641886A (zh) * 2004-01-16 2005-07-20 崇贸科技股份有限公司 具有一分开井结构的隔离的高电压ldmos晶体管
EP1703566A1 (en) * 2005-03-18 2006-09-20 AMI Semiconductor Belgium BVBA MOS device having at least two channel regions
CN101714577A (zh) * 2008-10-01 2010-05-26 东部高科股份有限公司 横向dmos晶体管及其制造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412881B2 (en) 2012-07-31 2016-08-09 Silanna Asia Pte Ltd Power device integration on a common substrate
US9825124B2 (en) 2012-07-31 2017-11-21 Silanna Asia Pte Ltd Power device integration on a common substrate
US10290702B2 (en) 2012-07-31 2019-05-14 Silanna Asia Pte Ltd Power device on bulk substrate
US10290703B2 (en) 2012-07-31 2019-05-14 Silanna Asia Pte Ltd Power device integration on a common substrate
US11791377B2 (en) 2012-07-31 2023-10-17 Silanna Asia Pte Ltd Power device integration on a common substrate

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