CN104681610B - Nldmos器件 - Google Patents

Nldmos器件 Download PDF

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CN104681610B
CN104681610B CN201310652810.0A CN201310652810A CN104681610B CN 104681610 B CN104681610 B CN 104681610B CN 201310652810 A CN201310652810 A CN 201310652810A CN 104681610 B CN104681610 B CN 104681610B
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钱文生
刘冬华
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种NLDMOS器件，组成漂移区的N型深阱由分段注入区加扩散实现，使掺杂浓度较低且能实现浓度调节的深阱非注入区设置在器件的源漏之间的局部场氧化层的靠近源区侧底部，能降低源漏之间的局部场氧化层的靠近源区侧的鸟嘴边界的电场强度并能使器件的击穿电压达到700V以上。在深阱非注入区的底部设置有一个比深阱非注入区的掺杂浓度高的第三N型注入区，能使得P阱、N型深阱和P型硅衬底之间形成的寄生PNP三极管的基区宽度更宽，能提高该寄生PNP三极管的C‑E穿通电压，能提高器件的源区所能承受的电压水平并能使源端电压抬高到40V以上，使得器件能应用于源端电压为40V以上、漏端电压为700V以上的场合。

Description

NLDMOS器件
技术领域
本发明涉及一种半导体集成电路器件，特别是涉及一种N型横向双扩散金属氧化物半导体场效应管（NLDMOS）器件。
背景技术
随着节能减排深入人心，智能电网项目的开展，功率半导体集成电路(PowerIntegrated Circuit，PIC)特别是超高压功率半导体在用电和配电领域的市场前景将非常广阔，如LED市电照明、高效马达驱动、配电网的改造、电能的AC/DC转换等。在所有的功率半导体器件中，LDMOS（Lateral Double Diffused MOSFET，横向双扩散金属氧化物半导体场效应管）高压器件具有工作电压高，工艺相对简单，开关频率高，且LDMOS器件的漏极、源极和栅极都位于其表面，易于同低压CMOS(Complementary Metal Oxide Semiconductor，互补型金属氧化物半导体)及BJT（Bipolar Junction Transistor，双极晶体管）等电路在工艺上兼容等特点，特别是对于AC/DC,DC/DC转换等电路，可以进行器件集成，而受到广泛关注，在高压集成电路和功率集成电路中被作为高压功率器件是特别适合的。从1979年J.A.Appels提出著名的RESURF(Reduce Surface Field，降低表面电场技术)原理以来，LDMOS器件得到了迅速的发展。
如图1所示，是现有NLDMOS器件剖面示意图；它是一种Double RESURF LDMOS器件，以700伏特NLDMOS为例，现有NLDMOS器件包括：
P型硅衬底101；形成于P型硅衬底101上的N型深阱（DNW）包括源端深阱注入区102a、漏端深阱注入区102b和深阱非注入区102c，所述源端深阱注入区102a和所述漏端深阱注入区102b的N型杂质都由相同的离子注入形成，所述深阱非注入区102c位于所述源端深阱注入区102a和所述漏端深阱注入区102b之间，所述深阱非注入区102c的N型杂质由所述源端深阱注入区102a和所述漏端深阱注入区102b的N型杂质横向扩散形成。P阱103，形成于所述源端深阱注入区102a中；源区108a，由形成于所述P阱103中的N+区组成；P阱引出区109，由形成于所述P阱103中的P+区组成；漏区108b，由形成于所述漏端深阱注入区102b中的N+区组成。
在所述漏区108b和所述P阱103之间的所述硅衬底101表面形成有局部场氧化 层（LOCOS）104，所述局部场氧化层104的第一侧延伸到所述深阱非注入区102c上。
栅极结构，包括依次形成于所述硅衬底101表面的栅介质层如栅氧化层105和多晶硅栅106，所述栅极结构覆盖部分所述P阱103并延伸到所述深阱非注入区102c以及所述局部场氧化层104上方，被所述栅极结构所述覆盖的所述P阱103的表面用于形成沟道；由位于所述漏区108b和所述P阱103之间的所述N型深阱组成漂移区。延伸到所述局部场氧化层104上方的多晶硅栅106用做场板，能够调节下面的电场。
在所述漏端深阱注入区102b中形成有第一P型埋层(PTOP)110a，所述第一P型埋层110a和所述局部场氧化层104的底部相隔一段距离；在所述源端深阱注入区102a中形成有第二P型埋层110b，所述第二P型埋层110b的深度和所述第一P型埋层110a的深度相同；所述第一P型埋层110a和所述第二P型埋层110b用于对所述漂移区进行纵向耗尽、降低所述漂移区的表面电场强度。
在所述局部场氧化层104的靠近漏端一侧的上方形成有多晶硅场板107。层间膜111形成在所述硅衬底101表面。所述源区108a和所述P阱引出区109的顶部分别形成有穿过所述层间膜111的金属接触孔112并通过该金属接触孔112连接源极金属层113a。所述漏区108b和所述多晶硅场板107的顶部形成有金属接触孔112并通过该金属接触孔112连接漏极金属层113b。所述多晶硅栅106的顶部形成有金属接触孔112并通过该金属接触孔112连接栅极金属层113c。
在现有技术中，所述局部场氧化层104在靠近所述源区108a一侧即第一侧的鸟嘴边界的电场比较集中，容易发生击穿，导致器件失效。且该处是所述局部场氧化层104与栅氧化层105的边界，电场较强，在源端加入电压时，会导致器件的热载流子效应加大(Hotcarrier Effect,HCE)，不利于器件的可靠性。降低该处的电场，一方面可以提高器件的击穿电压，同时另一方面也提高了器件的可靠性。在如图1所示的现有NLDMOS器件中，为了改善鸟嘴边界的电场，采取的方法是降低此处的N型掺杂浓度。其工艺实现方法是N型深阱在器件中的注入区分为两段，一段是漏端和漂移区端即所述漏端深阱注入区102b，一段是源端即源端深阱注入区102a。两段N型深阱的掺杂通过热扩散实现连接，即深阱非注入区102c的掺杂由所述源端深阱注入区102a和所述漏端深阱注入区102b的N型杂质横向扩散形成，这样能使深阱非注入区102c的掺杂浓度降低，从而降低所述局部场氧化层104的第一侧的鸟嘴边界的电场强度，所述深阱非注入区102c的掺杂浓度越小、所述局部场氧化层104的第一侧的电 场强度越小，所以能够通过控制所述深阱非注入区102c的掺杂浓度得到所需要的隔离型700伏特NLDMOS器件的击穿电压。
隔离型器件可以实现比较特殊的应用。一种比较普遍的应用是源端电压的抬高到40伏特。但上述隔离型700伏特NLDMOS器件在这种应用中，源端电压最高值不能超过40伏特，从而使的现有器件无法应用于源端电压为40伏特以上的场合。其原因是所述P阱103、所述N型深阱的所述源端深阱注入区102a和所述深阱非注入区102c、以及所述P阱硅衬底会形成寄生PNP三极管，由于所述深阱非注入区102c的掺杂浓度较低，这样寄生PNP三极管的基区宽度基本上是由所述P阱103和所述深阱非注入区102c之间的所述源端深阱注入区102a的横向宽度决定，该宽度较小，所以寄生PNP三极管的集电极和发射极（C-E）的穿通电压较低，在源端电压为40伏特以上，该寄生PNP三极管会发生C-E穿通。
发明内容
本发明所要解决的技术问题是提供一种NLDMOS器件，能使源端电压抬高到40V以上、并能使器件的击穿电压达到700V以上，使得器件能够应用于源端电压为40V以上、漏端电压为700V以上的场合。
为解决上述技术问题，本发明提供的NLDMOS器件包括：
形成于P型硅衬底上的N型深阱，所述N型深阱包括源端深阱注入区、漏端深阱注入区和深阱非注入区，所述源端深阱注入区和所述漏端深阱注入区的N型杂质都由相同的离子注入形成，所述深阱非注入区位于所述源端深阱注入区和所述漏端深阱注入区之间，所述深阱非注入区的N型杂质由所述源端深阱注入区和所述漏端深阱注入区的N型杂质横向扩散形成；所述深阱非注入区的掺杂浓度小于所述源端深阱注入区或所述漏端深阱注入区的掺杂浓度，所述源端深阱注入区和所述漏端深阱注入区之间的间距越大、所述深阱非注入区的掺杂浓度越小。
P阱，形成于所述源端深阱注入区中。
源区，由形成于所述P阱中的N+区组成。
P阱引出区，由形成于所述P阱中的P+区组成。
漏区，由形成于所述漏端深阱注入区中的N+区组成。
在所述漏区和所述P阱之间的所述硅衬底表面形成有局部场氧化层，所述局部场氧化层的第一侧延伸到所述深阱非注入区上，所述深阱非注入区的掺杂浓度越小、所 述局部场氧化层的第一侧的电场强度越小、NLDMOS器件的击穿电压越高；所述漏区和所述局部场氧化层的第二侧自对准。
栅极结构，包括依次形成于所述硅衬底表面的栅介质层和多晶硅栅，所述栅极结构覆盖部分所述P阱并延伸到所述深阱非注入区以及所述局部场氧化层上方，被所述栅极结构所述覆盖的所述P阱的表面用于形成沟道；由位于所述漏区和所述P阱之间的所述N型深阱组成漂移区。
在所述漏端深阱注入区中形成有第一P型埋层，所述第一P型埋层和所述局部场氧化层的底部相隔一段距离；在所述源端深阱注入区中形成有第二P型埋层，所述第二P型埋层的深度和所述第一P型埋层的深度相同；所述第一P型埋层和所述第二P型埋层用于对所述漂移区进行纵向耗尽、降低所述漂移区的表面电场强度。
第三N型注入区形成于所述深阱非注入区中并位于所述深阱非注入区中的底部区域，所述第三N型注入区的顶部和所述深阱非注入区的顶部相隔一段距离，所述P阱、所述N型深阱和所述P型硅衬底形成寄生PNP三极管，所述第三N型注入区的掺杂浓度大于所述深阱非注入区的掺杂浓度，所述第三N型注入区的掺杂浓度越高、所述寄生PNP三极管的集电极和发射极的穿通电压越高。
进一步的改进是，所述NLDMOS器件的击穿电压为700V以上。
进一步的改进是，所述寄生PNP三极管的集电极和发射极的穿通电压为40V以上。
进一步的改进是，所述第三N型注入区为一N型阱区。
本发明具有如下有益效果：
1、本发明通过将N型深阱进行分段式注入，使掺杂浓度较低且能实现浓度调节的深阱非注入区设置在器件的源漏之间的局部场氧化层的靠近源区侧的区域底部，从而能降低源漏之间的局部场氧化层的靠近源区侧的鸟嘴边界的电场强度，从而能使器件的击穿电压达到700V以上。
2、本发明通过在深阱非注入区的底部设置一个比深阱非注入区的掺杂浓度高的第三N型注入区，能够使得P阱、N型深阱和P型硅衬底之间形成的寄生PNP三极管的基区宽度更宽，从而能够提高该寄生PNP三极管的C-E穿通电压，从而能提高器件的源区所能承受的电压水平并能使源端电压抬高到40V以上，使得器件能够应用于源端电压为40V以上、漏端电压为700V以上的场合。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明:
图1是现有NLDMOS器件剖面示意图；
图2是本发明实施例LDMOS器件剖面示意图；
图3是图2中的寄生PNP示意图。
具体实施方式
如图2所示，是本发明实施例LDMOS器件剖面示意图；本发明实施例NLDMOS器件包括：
形成于P型硅衬底1上的N型深阱，所述N型深阱包括源端深阱注入区2a、漏端深阱注入区2b和深阱非注入区2c，所述源端深阱注入区2a和所述漏端深阱注入区2b的N型杂质都由相同的离子注入形成，所述深阱非注入区2c位于所述源端深阱注入区2a和所述漏端深阱注入区2b之间，所述深阱非注入区2c的N型杂质由所述源端深阱注入区2a和所述漏端深阱注入区2b的N型杂质横向扩散形成；所述深阱非注入区2c的掺杂浓度小于所述源端深阱注入区2a或所述漏端深阱注入区2b的掺杂浓度，所述源端深阱注入区2a和所述漏端深阱注入区2b之间的间距越大、所述深阱非注入区2c的掺杂浓度越小。
P阱3，形成于所述源端深阱注入区2a中。
源区8a，由形成于所述P阱3中的N+区组成。
P阱引出区9，由形成于所述P阱3中的P+区组成。
漏区8b，由形成于所述漏端深阱注入区2b中的N+区组成。
在所述漏区8b和所述P阱3之间的所述硅衬底1表面形成有局部场氧化层4，所述局部场氧化层4的第一侧延伸到所述深阱非注入区2c上，所述深阱非注入区2c的掺杂浓度越小、所述局部场氧化层4的第一侧的电场强度越小、NLDMOS器件的击穿电压越高；本发明实施例中通过调节所述深阱非注入区2c的掺杂浓度使所述NLDMOS器件的击穿电压达到700伏特以上。所述漏区8b和所述局部场氧化层4的第二侧自对准。
栅极结构，包括依次形成于所述硅衬底1表面的栅介质层5和多晶硅栅6；较佳为，所述栅介质层5为栅氧化层。所述栅极结构覆盖部分所述P阱3并延伸到所述深阱非注入区2c以及所述局部场氧化层4上方，被所述栅极结构所述覆盖的所述P阱3的表面用于形成沟道；由位于所述漏区8b和所述P阱3之间的所述N型深阱组成漂 移区。
在所述漏端深阱注入区2b中形成有第一P型埋层10a，所述第一P型埋层10a和所述局部场氧化层4的底部相隔一段距离；在所述源端深阱注入区2a中形成有第二P型埋层10b，所述第二P型埋层10b的深度和所述第一P型埋层10a的深度相同；所述第一P型埋层10a和所述第二P型埋层10b用于对所述漂移区进行纵向耗尽、降低所述漂移区的表面电场强度。
第三N型注入区11形成于所述深阱非注入区2c中并位于所述深阱非注入区2c中的底部区域，较佳为，所述第三N型注入区11为一N型阱区，采用N型阱区注入实现。所述第三N型注入区11的顶部和所述深阱非注入区2c的顶部相隔一段距离。
如图3所示，是图2中的寄生PNP示意图，所述P阱3、所述N型深阱的所述源端深阱注入区2a、所述深阱非注入区2c、所述第三N型注入区11和所述P型硅衬底1形成寄生PNP三极管，所述第三N型注入区11的掺杂浓度大于所述深阱非注入区2c的掺杂浓度，所述第三N型注入区11的掺杂浓度越高，所述寄生PNP三极管的基区的掺杂浓度越高、宽度也越大，这样能使所述寄生PNP三极管的集电极和发射极的穿通电压越高，本发明实施例通过所述第三N型注入区11的设置能使所述寄生PNP三极管的集电极和发射极的穿通电压为40V以上。所以本发明实施例通过设置所述深阱非注入区2c能使器件的击穿电压达到700V以上，而通过所述第三N型注入区11的设置，能够消除所述深阱非注入区2c的掺杂浓度过低而使所述寄生PNP三极管的C-E穿通电压较小的影响，使得寄生PNP三极管的C-E穿通电压能达到40V以上，使得本发明实施例器件能够应用于源端电压为40V以上、漏端电压为700V以上的场合。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (4)

1.一种NLDMOS器件，其特征在于，包括：
形成于P型硅衬底上的N型深阱，所述N型深阱包括源端深阱注入区、漏端深阱注入区和深阱非注入区，所述源端深阱注入区和所述漏端深阱注入区的N型杂质都由相同的离子注入形成，所述深阱非注入区位于所述源端深阱注入区和所述漏端深阱注入区之间，所述深阱非注入区的N型杂质由所述源端深阱注入区和所述漏端深阱注入区的N型杂质横向扩散形成；所述深阱非注入区的掺杂浓度小于所述源端深阱注入区或所述漏端深阱注入区的掺杂浓度，所述源端深阱注入区和所述漏端深阱注入区之间的间距越大、所述深阱非注入区的掺杂浓度越小；
P阱，形成于所述源端深阱注入区中；
源区，由形成于所述P阱中的N+区组成；
P阱引出区，由形成于所述P阱中的P+区组成；
漏区，由形成于所述漏端深阱注入区中的N+区组成；
在所述漏区和所述P阱之间的所述硅衬底表面形成有局部场氧化层，所述局部场氧化层的第一侧延伸到所述深阱非注入区上，所述深阱非注入区的掺杂浓度越小、所述局部场氧化层的第一侧的电场强度越小、NLDMOS器件的击穿电压越高；所述漏区和所述局部场氧化层的第二侧自对准；
栅极结构，包括依次形成于所述硅衬底表面的栅介质层和多晶硅栅，所述栅极结构覆盖部分所述P阱并延伸到所述深阱非注入区以及所述局部场氧化层上方，被所述栅极结构所述覆盖的所述P阱的表面用于形成沟道；由位于所述漏区和所述P阱之间的所述N型深阱组成漂移区；
在所述漏端深阱注入区中形成有第一P型埋层，所述第一P型埋层和所述局部场氧化层的底部相隔一段距离；在所述源端深阱注入区中形成有第二P型埋层，所述第二P型埋层的深度和所述第一P型埋层的深度相同；所述第一P型埋层和所述第二P型埋层用于对所述漂移区进行纵向耗尽、降低所述漂移区的表面电场强度；
第三N型注入区形成于所述深阱非注入区中并位于所述深阱非注入区中的底部区域，所述第三N型注入区的顶部和所述深阱非注入区的顶部相隔一段距离，所述P阱、所述N型深阱和所述P型硅衬底形成寄生PNP三极管，所述第三N型注入区的掺杂浓度大于所述深阱非注入区的掺杂浓度，所述第三N型注入区的掺杂浓度越高、所述寄生PNP三极管的集电极和发射极的穿通电压越高。
2.如权利要求1所述的NLDMOS器件，其特征在于：所述NLDMOS器件的击穿电压为700V以上。
3.如权利要求1所述的NLDMOS器件，其特征在于：所述寄生PNP三极管的集电极和发射极的穿通电压为40V以上。
4.如权利要求1所述的NLDMOS器件，其特征在于：所述第三N型注入区为一N型阱区。
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