CN105957880B - 高压n型ldmos器件及工艺方法 - Google Patents

高压n型ldmos器件及工艺方法 Download PDF

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CN105957880B
CN105957880B CN201610269875.0A CN201610269875A CN105957880B CN 105957880 B CN105957880 B CN 105957880B CN 201610269875 A CN201610269875 A CN 201610269875A CN 105957880 B CN105957880 B CN 105957880B
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段文婷
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

本发明公开了一种高压N型LDMOS器件,在P型衬底中具有分为第一及第二两段的N型深阱,第一N型深阱中包含有P阱,P阱中具有LDMOS器件的源区及重掺杂P型区;第二N型深阱位于场氧之下且包含有LDMOS器件的漏区;源区与场氧之间的硅表面具有栅氧化层及覆盖在栅氧化层之上的多晶硅栅极,靠近漏端的场氧之上还覆盖漏端多晶硅场板;所述的第一N型深阱及第二N型深阱中还具有P型注入层,且P型注入层在第二N型深阱中分为两段或者多段,靠近源区的P型注入层与第一N型深阱中的P型注入层具有相同的杂质注入剂量,第二N型深阱中靠近漏区的P型注入层的杂质注入剂量大于靠近源区的P型注入层。本发明还公开了所述高压N型LDMOS器件的工艺方法。

Description

高压N型LDMOS器件及工艺方法
技术领域
本发明涉及半导体器件,特别是指一种高压N型LDMOS器件。本发明还涉及所述高压N型LDMOS器件的工艺方法。
背景技术
耐压500V的LDMOS既具有分立器件高压大电流特点,又汲取了低压集成电路高密度智能逻辑控制的优点,单芯片实现原来多个芯片才能完成的功能,大大缩小了面积,降低了成本,提高了能效,符合现代电力电子器件小型化,智能化,低能耗的发展方向。击穿电压作为衡量500V器件的关键参数而显得尤为重要。普通500V的N型LDMOS器件结构如图1所示,包含两段的N型深阱102,其漂移区的P型注入层105(或者又称为Ptop层,下同)起到加速漂移区耗尽的作用,使击穿电压增加。
从图2所示的仿真的耗尽区看到,Ptop层靠近源端处并没有完全耗尽,因为漂移区耗尽是从P阱与N型深阱形成的PN结处开始耗尽,漂移区Ptop层近源端处距离PN结比漏端处近,因此耗尽需要的浓度比漏端处低。由于现在的结构整个Ptop层浓度相同,在漏端Ptop层完全耗尽的情况下,源端Ptop层并没有完全耗尽,使得器件的击穿电压还存在优化的空间。
发明内容
本发明所要解决的技术问题在于提供一种高压N型LDMOS器件,具有较高的击穿电压。
本发明还要解决的技术问题在于提供所述高压N型LDMOS器件的工艺方法。
为解决上述问题,本发明所述的高压N型LDMOS器件,在P型衬底中具有N型深阱,在剖视角度上,所述N型深阱分为第一N型深阱及第二N型深阱两段,第一N型深阱中包含有P阱,P阱中具有LDMOS器件的源区及重掺杂P型区;第二N型深阱位于场氧之下且包含有LDMOS器件的漏区;
源区与场氧之间的硅表面具有栅氧化层及覆盖在栅氧化层之上的多晶硅栅极,靠近漏端的场氧之上还覆盖漏端多晶硅场板;
所述的第一N型深阱及第二N型深阱中还具有P型注入层,且P型注入层在第二N型深阱中分为两段或者多段,靠近源区的P型注入层与第一N型深阱中的P型注入层具有相同的杂质注入剂量,第二N型深阱中靠近漏区的P型注入层的杂质注入剂量大于靠近源区的P型注入层,即越靠近漏区的P型注入层杂质注入剂量越高。
为解决上述问题,本发明所述一种高压N型LDMOS器件的工艺方法,包含如下的工艺步骤:
步骤1,在P型衬底上离子注入形成N型深阱;
步骤2,光刻打开场氧区域,刻蚀场氧区,生长场氧;
步骤3,光刻打开阱注入区,离子注入形成P阱;
步骤4,进行两次或两次以上的P型注入层注入,越靠近漏端注入剂量越高;
步骤5,生长栅氧化层,淀积多晶硅并刻蚀形成多晶硅栅极以及漏端多晶硅场板;
步骤6,进行源区及漏区注入,以及P阱中重掺杂P型区注入;
步骤7,淀积层间介质,刻蚀接触孔,淀积金属引出各电极。
所述步骤1中形成的N型深阱分为两部分,分别是用于包含源区及P阱的第一N型深阱和用于形成漏区漂移区的第二N型深阱。
所述步骤2中场氧形成与第二N型深阱之上。
所述步骤3中P阱形成于第一N型深阱中,作为N型LDMOS器件的本底区。
所述步骤4中进行两次或两次以上的P型注入层注入,以形成两段或多段的P型注入层,注入剂量往漏端方向逐渐提高。
本发明所述的高压N型LDMOS器件,通过将P型注入层分段形成,注入剂量越靠近漏区逐渐提高,使得器件的靠近源区的P型注入层也能完全耗尽,增大耗尽区面积,提高器件的击穿电压。本发明所述的工艺方法简单易于实施。
附图说明
图1是传统结构的高压N型LDMOS器件的结构示意图。
图2是传统结构的高压N型LDMOS器件的仿真示意图。
图3是本发明高压N型LDMOS器件的结构示意图。
图4~9是本发明高压N型LDMOS器件形成工艺示意图。
图10A、10B是本发明与传统结构LDMOS击穿电压仿真对比图。
图11是本发明工艺流程图。
附图标记说明
101—P型衬底,102—N型深阱,103—场氧,104—P阱,105、105a、105b—P型注入层(Ptop层),106—栅氧化层,107—多晶硅栅极(漏端多晶硅场板),108a—N型重掺杂区(漏端),108b—N型重掺杂区(源端),109—P型重掺杂区,110—层间介质,111—金属。
具体实施方式
本发明所述的高压N型LDMOS器件,如图3所示,在P型衬底101中具有N型深阱102,在剖视角度上,所述N型深阱102分为第一N型深阱(图中左侧)及第二N型深阱(图中右侧)两段,第一N型深阱中包含有P阱104,P阱104中具有LDMOS器件的源区及重掺杂P型区;第二N型深阱位于场氧103之下且包含有LDMOS器件的漏区108a。
源区108b与场氧103之间的硅表面具有栅氧化层106及覆盖在栅氧化层106之上的多晶硅栅极107,靠近漏端的场氧之上还覆盖漏端多晶硅场板107(与多晶硅栅极同步刻蚀形成,同一材质)。
所述的第一N型深阱及第二N型深阱中还具有P型注入层105,且P型注入层在第二N型深阱中分为两段或者多段,靠近源区的P型注入层与第一N型深阱中的P型注入层具有相同的杂质注入剂量,即图3中第一N型深阱中的105a与第二N型深阱中的105a具有相同的杂质注入剂量。第二N型深阱中靠近漏区的P型注入层105b的杂质注入剂量大于靠近源区的P型注入层105a,即越靠近漏区的P型注入层杂质注入剂量越高。
为解决上述问题,本发明所述一种高压N型LDMOS器件的工艺方法,包含如下的工艺步骤:
步骤1,在P型衬底上离子注入形成N型深阱。形成的N型深阱102分为左右两部分,如图4所示,分别是用于包含源区及P阱的左侧的第一N型深阱和用于形成漏区漂移区的右侧的第二N型深阱。
步骤2,光刻打开场氧区域,刻蚀场氧区,在第二N型深阱之上生长场氧103,如图5所示。
步骤3,如图6所示,光刻打开阱注入区,在第一N型深阱102中离子注入形成P阱4,作为N型LDMOS器件的本底区。
步骤4,进行两次或两次以上的P型注入层注入,以形成两段或多段的P型注入层,如图7所示,图中第一N型深阱中P型注入层105a与右侧第二N型深阱中的P型注入层105a为同一剂量注入,右侧P型注入层105b具有更高的注入剂量。注入剂量往漏区方向逐渐提高。具体进行多少次P型注入层可根据器件特性需要灵活设定调整。对于本实施例采用两段式P型注入层,105a的注入剂量为1E11~1E14cm-2,105b的注入剂量为2E11~5E14cm-2
步骤5,生长栅氧化层106,淀积多晶硅并刻蚀形成多晶硅栅极107以及漏端多晶硅场板,如图8所示。
步骤6,如图9所示,进行源区108b及漏区108a注入,以及P阱中重掺杂P型区109注入,重掺杂P型区109将P阱引出。
步骤7,淀积层间介质110,刻蚀接触孔,淀积金属111并刻蚀形成图案引出各电极,所述N型LDMOS器件制作完成,如图3所示。
对本发明的高压LDMOS器件进行击穿电压测试,其测试曲线如图10A及图10B所示,图10A为传统结构的LDMOS器件击穿电压仿真测试曲线,其击穿电压为594V,而图10B本发明结构的LDMOS的击穿电压达到了640V,比传统结构提高了8%。
以上仅为本发明的优选实施例,并不用于限定本发明。对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (5)

1.一种高压N型LDMOS器件的工艺方法,其特征在于:包含如下的工艺步骤:
步骤1,在P型衬底上离子注入形成N型深阱;
步骤2,光刻打开场氧区域,刻蚀场氧区,生长场氧;
步骤3,光刻打开阱注入区,离子注入形成P阱;
步骤4,进行两次或两次以上的P型注入层注入,越靠近漏端注入剂量越高;
步骤5,生长栅氧化层,淀积多晶硅并刻蚀形成多晶硅栅极以及漏端多晶硅场板;
步骤6,进行源区及漏区注入,以及P阱中重掺杂P型区注入;
步骤7,淀积层间介质,刻蚀接触孔,淀积金属引出各电极。
2.如权利要求1所述的高压N型LDMOS器件的工艺方法,其特征在于:所述步骤1中形成的N型深阱分为两部分,分别是用于包含源区及P阱的第一N型深阱和用于形成漏区漂移区的第二N型深阱。
3.如权利要求2所述的高压N型LDMOS器件的工艺方法,其特征在于:所述步骤2中场氧形成与第二N型深阱之上。
4.如权利要求2所述的高压N型LDMOS器件的工艺方法,其特征在于:所述步骤3中P阱形成于第一N型深阱中,作为N型LDMOS器件的本底区。
5.如权利要求1所述的高压N型LDMOS器件的工艺方法,其特征在于:所述步骤4中进行两次或两次以上的P型注入层注入,以形成两段或多段的P型注入层,注入剂量往漏端方向逐渐提高。
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