CN103178087A - 超高压ldmos器件结构及制备方法 - Google Patents

超高压ldmos器件结构及制备方法 Download PDF

Info

Publication number
CN103178087A
CN103178087A CN2011104411108A CN201110441110A CN103178087A CN 103178087 A CN103178087 A CN 103178087A CN 2011104411108 A CN2011104411108 A CN 2011104411108A CN 201110441110 A CN201110441110 A CN 201110441110A CN 103178087 A CN103178087 A CN 103178087A
Authority
CN
China
Prior art keywords
trap
deep
high voltage
drift region
ultra
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011104411108A
Other languages
English (en)
Other versions
CN103178087B (zh
Inventor
宁开明
董科
马栋
朱东园
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CN201110441110.8A priority Critical patent/CN103178087B/zh
Publication of CN103178087A publication Critical patent/CN103178087A/zh
Application granted granted Critical
Publication of CN103178087B publication Critical patent/CN103178087B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种超高压LDMOS器件结构，包括源端、漏端、高压漂移区和栅极沟道，源端有衬底阱，高压漂移区表面有反型层，该LDMOS中还设计有两个物理上相连的深阱，分别用于放置衬底阱和反型层，两深阱的间隙位于LOCOS鸟嘴附近。本发明还公开了上述结构的LDMOS的制备方法，包括设计深阱的光刻掩膜版、光刻、离子注入、去胶和热推阱等工艺步骤。本发明通过将源端的深阱与高压漂移区的深阱分离，并在离子注入后通过推阱使其连在一起，并使其间隙位于LOCOS鸟嘴下方，从而改善了LOCOS附近的电场分布，降低了其峰值电场，达到了N型和P型电荷平衡，在不增加工艺步骤和成本的基础上，实现了提高器件反向击穿电压的目的。

Description

超高压LDMOS器件结构及制备方法
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及超高压LDMOS器件的结构及制备工艺。
背景技术
超高压LDMOS器件(laterally diffused metal oxide semiconductor，横向双扩散金属氧化物半导体晶体管)是一种双扩散结构的功率器件，其结构如图1所示。这项技术是在相同的源/漏区域注入两次，一次注入浓度较大的砷(As)，另一次注入浓度较小的硼(B)，注入之后再进行一个高温推进过程，由于硼扩散比砷快，所以在栅极边界下会沿着横向扩散更远，形成一个有浓度梯度的沟道——P阱(PW)，沟道长度由这两次横向扩散的距离之差决定。为了增加击穿电压，在有源区和漏区之间有一个漂移区。LDMOS中的漂移区是该类器件设计的关键。由于漂移区的杂质浓度比较低，当LDMOS接高压时，LDMOS的多晶会扩展到漂移区的场氧上面，充当场极板，即大部分电压都会降落在漂移区，这样就降低了沟道处的电压，从而实现了器件的超高击穿电压。
当前，先进的超高压隔离型NLDMOS一般是将器件整体放到一个N型深阱(DNW)里，同时在漂移区表面增加P型埋层(P buried)结构，如图1所示。通过调节PW和DNW的相对距离或P型埋层的杂质浓度，来实现电荷平衡和超高击穿电压。当漏(Drain)端电压增加时，P型埋层向DNW上下两个方向耗尽，而且沿着向源(Source)端的方向耗尽。因此，加在漏端的电压虽然很大，但是到达源端的电压很小。当漏端加到700多伏的时候，PW和DNW的这个PN结才能发生雪崩击穿。但是，由于场氧边缘都是电场集中的位置，LOCOS(局部氧化硅)鸟嘴下的表面电场最强，LDMOS的多晶扩展到漂移区的场氧上面的场极板很难弱化漂移区的表面电场，这时，LOCOS鸟嘴下的N型杂质就很难被耗尽了，这样击穿电压就会变小，器件就容易被击穿。
发明内容
本发明要解决的技术问题是提供一种超高压LDMOS器件结构，它可以提高超高压LDMOS器件的击穿电压。
为解决上述技术问题，本发明的隔离型超高压LDMOS器件结构，包括源端、漏端、高压漂移区和栅极沟道，其中，源端有衬底阱，该衬底阱的杂质类型与衬底相同；高压漂移区表面有用于耐压的反型层，该反型层的杂质类型与高压漂移区相反；该LDMOS中还有两个物理上相连的深阱，分别用于放置所述衬底阱和所述反型层，两深阱的间隙位于栅极下方的局部氧化硅的鸟嘴附近。
本发明要解决的另一技术问题是提供上述结构的超高压LDMOS器件的制备工艺方法。
为解决上述技术问题，本发明的超高压LDMOS器件的制备方法，包括以下步骤：
1)设计深阱的掩膜版，将放置源端衬底阱的深阱和放置高压漂移区的反型层的深阱分离；
2)在衬底上涂布光刻胶，曝光，打开深阱；
3)通过离子注入工艺，在深阱中注入杂质离子；
4)去除光刻胶；
5)热推阱，使两个深阱在物理上相连；后续按常规工艺完成LDMOS的制备。
本发明通过将源端的深阱与漏端漂移区的深阱分离，降低了LOCOS鸟嘴附近的峰值电场，达到了N型和P型电荷平衡，从而在不增加工艺步骤和成本的基础上，提高了器件的击穿电压。
附图说明
图1是传统超高压NLDMOS器件的断面结构示意图。
图2是传统超高压NLDMOS器件的DNW掩膜版示意图。其中，(a)为俯视图；(b)为侧视图。
图3是本发明实施例的超高压N LDMOS器件的断面结构示意图。
图4是本发明实施例的超高压N LDMOS器件的DNW掩膜版示意图。其中，(a)为俯视图；(b)为侧视图。
具体实施方式
为对本发明的技术内容、特点与功效有更具体的了解，现以超高压N型LDMOS器件为例，结合图示的实施方式，对本发明的技术方案详述如下：
如图3所示，本发明实施例的超高压LDMOS器件，具有两个N型深阱(DNW)，其中，一个DNW中放置LDMOS器件源端的P阱(PW)，另一个DNW中放置漏端耐压用的P型埋层(Pburied)；两个深N阱中间用P型衬底(PSUB)隔开。
上述结构的超高压LDMOS器件的制备方法为：
步骤1，设计LDMOS器件的DNW的掩膜版，将传统的DNW注入图形(如图2所示)更改为如图4所示的图形。
步骤2，在P型衬底上涂布光刻胶，曝光，打开DNW。
步骤3，通过离子注入工艺，在DNW中注入磷(P)离子。离子注入的能量为50～200KeV，剂量为1E12～1E13/cm2。
步骤4，去除光刻胶。
步骤5，在1200℃下，通氮气，推阱400～500分钟，使DNW边缘处的杂质浓度变淡。注入推阱后，两个深阱物理上连在一起。
后续工艺步骤按照常规的制备工艺流程进行，直至完成超高压LDMOS器件的制备，得到如图3所示的结构。
上述实施例中，通过调整DNW的结构，采用两个DNW，以及调节两个DNW之间的距离及相对位置，使两个DNW之间的空隙在LOCOS鸟嘴附近，由于两个DNW是靠推阱连在一起的，这样就降低了LOCOS鸟嘴下面DNW的杂质浓度，使LOCOS鸟嘴附近的N型杂质更容易被耗尽，从而改变了电场强度，降低了器件的临界电场，并尽可能地由表面移到体内，最终实现提高器件耐压能力的目的。

Claims (6)

1.超高压LDMOS器件结构，包括源端、漏端、高压漂移区和栅极沟道，其中，源端有衬底阱，该衬底阱的杂质类型与衬底相同；高压漂移区表面有用于耐压的反型层，该反型层的杂质类型与高压漂移区相反；其特征在于，该LDMOS中有两个物理上相连的深阱，分别用于放置所述衬底阱和所述反型层，两深阱的间隙位于栅极下方的局部氧化硅的鸟嘴附近。
2.权利要求1所述结构的超高压LDMOS器件的制备方法，其特征在于，包括以下步骤：
1)设计深阱的掩膜版，将放置源端衬底阱的深阱和放置高压漂移区的反型层的深阱分离；
2)在衬底上涂布光刻胶，曝光，打开深阱；
3)通过离子注入工艺，在深阱中注入杂质离子；
4)去除光刻胶；
5)热推阱，使两个深阱在物理上相连；后续按常规工艺完成LDMOS的制备。
3.根据权利要求2所述的方法，其特征在于，所述深阱为N型深阱。
4.根据权利要求3所述的方法，其特征在于，步骤3)，所述杂质离子是磷离子。
5.根据权利要求4所述的方法，其特征在于，步骤3)，离子注入条件为：注入能量100～200KeV，注入剂量1E12～1E13/cm2。
6.根据权利要求2所述的方法，其特征在于，步骤5)，推阱的条件为：温度1200℃，通氮气，时间400～500分钟。
CN201110441110.8A 2011-12-26 2011-12-26 超高压ldmos器件结构及制备方法 Active CN103178087B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110441110.8A CN103178087B (zh) 2011-12-26 2011-12-26 超高压ldmos器件结构及制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110441110.8A CN103178087B (zh) 2011-12-26 2011-12-26 超高压ldmos器件结构及制备方法

Publications (2)

Publication Number Publication Date
CN103178087A true CN103178087A (zh) 2013-06-26
CN103178087B CN103178087B (zh) 2016-02-10

Family

ID=48637836

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110441110.8A Active CN103178087B (zh) 2011-12-26 2011-12-26 超高压ldmos器件结构及制备方法

Country Status (1)

Country Link
CN (1) CN103178087B (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465653A (zh) * 2014-12-31 2015-03-25 上海华虹宏力半导体制造有限公司 高压静电保护结构
CN104617149A (zh) * 2015-01-30 2015-05-13 上海华虹宏力半导体制造有限公司 隔离型nldmos器件及其制造方法
CN104617148A (zh) * 2015-01-30 2015-05-13 上海华虹宏力半导体制造有限公司 隔离型nldmos器件及其制造方法
CN104681610A (zh) * 2013-12-03 2015-06-03 上海华虹宏力半导体制造有限公司 Nldmos器件
CN105185834A (zh) * 2015-10-19 2015-12-23 杭州士兰微电子股份有限公司 复合高压半导体器件
CN107301975A (zh) * 2016-04-14 2017-10-27 世界先进积体电路股份有限公司 半导体装置及其制造方法
CN109244142A (zh) * 2018-09-29 2019-01-18 深圳市南硕明泰科技有限公司 一种ldmos及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844275A (en) * 1994-09-21 1998-12-01 Fuji Electric Co., Ltd. High withstand-voltage lateral MOSFET with a trench and method of producing the same
CN1222768A (zh) * 1997-11-28 1999-07-14 日本电气株式会社 半导体器件
US6211552B1 (en) * 1999-05-27 2001-04-03 Texas Instruments Incorporated Resurf LDMOS device with deep drain region
KR20100046354A (ko) * 2008-10-27 2010-05-07 주식회사 동부하이텍 Ｌｄｍｏｓ 트랜지스터 및 그의 제조 방법
CN101924131A (zh) * 2009-06-11 2010-12-22 上海华虹Nec电子有限公司 横向扩散mos器件及其制备方法
CN102130153A (zh) * 2010-12-22 2011-07-20 东南大学 绝缘体上硅的n型横向绝缘栅双极晶体管及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844275A (en) * 1994-09-21 1998-12-01 Fuji Electric Co., Ltd. High withstand-voltage lateral MOSFET with a trench and method of producing the same
CN1222768A (zh) * 1997-11-28 1999-07-14 日本电气株式会社 半导体器件
US6211552B1 (en) * 1999-05-27 2001-04-03 Texas Instruments Incorporated Resurf LDMOS device with deep drain region
KR20100046354A (ko) * 2008-10-27 2010-05-07 주식회사 동부하이텍 Ｌｄｍｏｓ 트랜지스터 및 그의 제조 방법
CN101924131A (zh) * 2009-06-11 2010-12-22 上海华虹Nec电子有限公司 横向扩散mos器件及其制备方法
CN102130153A (zh) * 2010-12-22 2011-07-20 东南大学 绝缘体上硅的n型横向绝缘栅双极晶体管及其制备方法

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681610B (zh) * 2013-12-03 2017-08-08 上海华虹宏力半导体制造有限公司 Nldmos器件
CN104681610A (zh) * 2013-12-03 2015-06-03 上海华虹宏力半导体制造有限公司 Nldmos器件
CN104465653B (zh) * 2014-12-31 2017-06-06 上海华虹宏力半导体制造有限公司 高压静电保护结构
CN104465653A (zh) * 2014-12-31 2015-03-25 上海华虹宏力半导体制造有限公司 高压静电保护结构
CN104617148B (zh) * 2015-01-30 2017-08-08 上海华虹宏力半导体制造有限公司 隔离型nldmos器件及其制造方法
CN104617148A (zh) * 2015-01-30 2015-05-13 上海华虹宏力半导体制造有限公司 隔离型nldmos器件及其制造方法
CN104617149A (zh) * 2015-01-30 2015-05-13 上海华虹宏力半导体制造有限公司 隔离型nldmos器件及其制造方法
CN104617149B (zh) * 2015-01-30 2018-06-19 上海华虹宏力半导体制造有限公司 隔离型nldmos器件及其制造方法
CN105185834A (zh) * 2015-10-19 2015-12-23 杭州士兰微电子股份有限公司 复合高压半导体器件
CN105185834B (zh) * 2015-10-19 2018-01-26 杭州士兰微电子股份有限公司 复合高压半导体器件
CN107301975A (zh) * 2016-04-14 2017-10-27 世界先进积体电路股份有限公司 半导体装置及其制造方法
CN107301975B (zh) * 2016-04-14 2020-06-26 世界先进积体电路股份有限公司 半导体装置及其制造方法
CN109244142A (zh) * 2018-09-29 2019-01-18 深圳市南硕明泰科技有限公司 一种ldmos及其制造方法

Also Published As

Publication number Publication date
CN103178087B (zh) 2016-02-10

Similar Documents

Publication Publication Date Title
CN103367445B (zh) 带有积累增益植入物的横向双扩散金属氧化物半导体
CN103178087B (zh) 超高压ldmos器件结构及制备方法
CN104992977B (zh) Nldmos器件及其制造方法
CN102412126B (zh) 超高压ldmos的工艺制作方法
CN102412162B (zh) 提高nldmos击穿电压的方法
CN104659090B (zh) Ldmos器件及制造方法
CN112397567A (zh) 一种具有p型横向变掺杂区的高压resurf ldmos器件
CN103390545A (zh) 改善沟槽型nmos漏源击穿电压的方法及其结构
CN103208519B (zh) 与5伏cmos工艺兼容的nldmos结构及其制法
CN103035525B (zh) 高压隔离n型ldmos器件的制造方法
CN102983161B (zh) 非埋层的双深n型阱高压隔离n型ldmos及制造方法
CN109119458B (zh) 隔离结构及工艺方法
CN104282763B (zh) 射频横向双扩散场效应晶体管制作方法
CN103022125A (zh) Bcd工艺中的nldmos器件及制造方法
CN103107191B (zh) 高压p型ldmos结构及其制造方法
CN103811402B (zh) 一种超高压bcd工艺的隔离结构制作工艺方法
CN102088031B (zh) Nldmos器件及其制造方法
CN109616511B (zh) 一种纵向多重pn结的vdmos分压环的设计方法
CN103123935A (zh) Nldmos器件及其制造方法
CN103199110B (zh) 一种nldmos器件及其制造方法
CN106169506B (zh) Ddd mos器件结构及其制造方法
CN104900695A (zh) 功率结型场效应管及其制造方法
CN112420804A (zh) 一种具有p型双重补偿结构的高压resurf ldmos器件
CN105576021B (zh) Nldmos器件及其制造方法
CN103094341A (zh) 低导通电阻的超高压nldmos器件及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

Effective date: 20140107

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI

TA01 Transfer of patent application right

Effective date of registration: 20140107

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Applicant before: Shanghai Huahong NEC Electronics Co., Ltd.

C14 Grant of patent or utility model
GR01 Patent grant