CN102088031B - Nldmos器件及其制造方法 - Google Patents

Nldmos器件及其制造方法 Download PDF

Info

Publication number
CN102088031B
CN102088031B CN 200910188704 CN200910188704A CN102088031B CN 102088031 B CN102088031 B CN 102088031B CN 200910188704 CN200910188704 CN 200910188704 CN 200910188704 A CN200910188704 A CN 200910188704A CN 102088031 B CN102088031 B CN 102088031B
Authority
CN
China
Prior art keywords
oxygen district
drift region
type
type structure
oxygen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN 200910188704
Other languages
English (en)
Other versions
CN102088031A (zh
Inventor
吴孝嘉
罗泽煌
韩广涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Corp
Original Assignee
CSMC Technologies Corp
Wuxi CSMC Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Corp, Wuxi CSMC Semiconductor Co Ltd filed Critical CSMC Technologies Corp
Priority to CN 200910188704 priority Critical patent/CN102088031B/zh
Priority to PCT/CN2010/079412 priority patent/WO2011066802A1/en
Publication of CN102088031A publication Critical patent/CN102088031A/zh
Application granted granted Critical
Publication of CN102088031B publication Critical patent/CN102088031B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

一种NLDMOS器件，包括浮置-P型结构，第一场氧区，第二场氧区，N型漂移区，第一场氧区和第二场氧区位于N型漂移区之上相对设置，所述浮置-P型结构位于N型漂移区的中部，所述的第一场氧区和第二场氧区不是连在一起，两者之间的有源区的宽度配合注入浮置-P型结构的长度。采用本发明的结构，不但可以提高半导体器件的击穿电压，而且有效地降低了导通电阻，同时减小了对高能注入的需求，降低了对工艺机台的限制，生产中容易实现。

Description

NLDMOS器件及其制造方法
【技术领域】
本发明涉及一种NLDMOS(N型横向双扩散金属氧化物半导体)器件，尤其涉及一种具有较高击穿电压和较低导通电阻的NLDMOS及其制造方法。
【背景技术】
随着半导体器件操作电压的不断提高，为了获得更高的器件耐压及较小的导通电阻，就引入了Super Junction(超结)概念。以NLDMOS(N型横向双扩散金属氧化物半导体)为例，首先为了获得较小的导通电阻而形成了浓度较高的N型漂移区，由于漂移区浓度较高使器件击穿值偏低，这时在N型漂移区内形成一定的P型区域。该P型区域一般是在漂移区的表面，沿沟道方向呈条状分布。通过引入的P型杂质与漂移区的N型杂质达到电荷平衡，以增强漂移区的耗尽，提高器件的击穿电压。但是由于该P型区是通过小能量注入到漂移区表面，电流只能从其下方的漂移区流过。而且为使其能够在纵向上耗尽整个漂移区，P型区的结深就不能太浅，因此必须经过一定的热过程推阱形成，这样就会使得N型漂移区杂质浓度受到P型杂质的影响而降低，抬高了导通电阻。而且经过热过程形成的P型区由于横扩使其尺寸增大，同样减小了电流流经的路径，再次抬高了导通电阻。
【发明内容】
有鉴于此，有必要针对NLDMOS器件导通电阻较大和击穿电压较小的问题，提供一种能提高击穿电压和降低导通电阻的NLDMOS器件。
此外，还有必要提供一种提高击穿电压和降低导通电阻的NLDMOS器件的制造方法。
一种NLDMOS器件，包括浮置-P型结构，第一场氧区，第二场氧区，N型漂移区，第一场氧区和第二场氧区位于N型漂移区之上相对设置，所述浮置-P型结构位于N型漂移区的中部沿着N型漂移区的沟道方向，所述的第一场氧区和第二场氧区之间的有源区的宽度不小于浮置-P型结构的长度，浮置-P型在N型漂移区的中部。
优选地，所述浮置-P型结构的数量不少于两个。
优选地，所述浮置-P型结构在版图上为条状，横截面为长方形。
优选地，所述浮置-P型结构的横截面为圆形。
优选地，所述第一场氧区和所述第二场氧区长度不一样。
一种NLDMOS器件制造方法，所述NLDMOS器件包括浮置-P型结构，第一场氧区，第二场氧区，N型漂移区，第一场氧区和第二场氧区位于N型漂移区之上相对设置，包括五个步骤：
步骤一：采用常规的外延生产工艺在埋氧层上形成外延层；
步骤二：采用常规的MOS工艺的进行阱注入，形成所述的N型漂移区；
步骤三：通过生长形成所述第一场氧区和所述第二场氧区，所述第一场氧区和第二场氧区之间就是有源区，该有源区尺寸配合将要注入的浮置-P型结构的长度；
步骤四：注入源栅和漏区；
步骤五：透过所述第一场氧区和所述第二场氧区之间的有源区将浮置-P型结构植入所述N型漂移区的中部。
优选地，所述浮置-P型结构的注入能量为200Kev～2000Kev。
采用上述结构，可以提高NLDMOS器件的击穿电压和降低导通电阻，降低了制作过程中对光刻胶厚度的要求，以及对高能注入机的要求。
【附图说明】
图1是本发明实施例NLDMOS器件结构示意图。
图2是图1沿着A-A’方向的截面示意图。
【具体实施方式】
如图1所示，是本发明的NLDMOS器件的结构示意图。该NLDMOS器件包括衬底引出101，源区引出103，栅极引出105，第一场氧区107，第二场氧区109，漏端引出111，高压N阱做成的N型漂移区113，浮置-P型结构(浮置P结构)115，埋氧层117，高压P阱做成的衬底119，N型漂移区113位于埋氧层117之上，衬底119和N型漂移区113相邻位于埋氧层117之上，浮置-P型结构115置于N型漂移区113之内。
根据各部分杂质浓度的调整，上述NLDMOS器件的击穿电压范围可达100V～1000V。
浮置-P型结构115沿着N型漂移区113沟道的方向位于其中部，浮置-P型结构115的数量不限于一个，可以有两个以上(如图2所示)。浮置-P型结构115在版图上为条状，横截面为长方形。浮置-P型结构115通过大能量注入到N型漂移区113的中部，注入能量为200Kev～2000Kev，注入能量可根据N型漂移区113的杂质分布及外延工艺的厚度作适当调整。浮置-P型结构115的剂量需要和N型漂移区113形成电荷平衡。浮置-P型结构115位于N型漂移区113的中部，可以在横向和纵向上耗尽N型杂质，有利于N型漂移区113的耗尽，提高器件的击穿电压，降低导通电阻。并且，电流可以在浮置-P型结构115的上方和下方的N型漂移区113沿着沟道流过，电流流经的路径较大。采用上述结构，漂移区的杂质浓度还可以适当提高，以继续降低电阻。
浮置-P型结构115横截面不限于长方形，只要有利于和N型漂移区耗尽的其他形状也可以，如圆形。
第一场氧区107和第二场氧区109在N型漂移区113之上相对设置，第一场氧区107和第二场氧区109两者没有完全覆盖N型漂移区113，因此，两者之间仍然是有源区。两者之间的有源区的宽度配合注入浮置-P型结构115的长度。第一场氧区107和第二场氧区109的长度可以不一样。
传统做法中，100V以上的LDMOS器件整个漂移区都被场氧区覆盖，由于浮置-P型结构要植入N型漂移区的中部，因此它必须用很高的能量注入，这就要求注入机必须能够做高能注入，同时光刻胶要足够厚，以阻挡浮置-P型注入到其它区域。在本实施方式中，第一场氧区107和第二场氧区109两者之间做成有源区，此有源区区域的氧化层较薄，方便了浮置-P型结构115的注入，因此降低了对注入机的能量和光刻胶厚度的要求，从而可以形成宽度及间距更小的浮置-P型结构，浮置-P型结构注入峰值更深，在生产中容易实现。
根据本发明的一种实施方式，上述NLDMOS器件的制造方法包括：
步骤一：采用常规的外延生产工艺在埋氧层上形成外延层；
步骤二：采用常规的MOS工艺的进行阱注入，形成所述的N型漂移区；
步骤三：通过生长形成所述第一场氧区和所述第二场氧区，所述第一场氧区和第二场氧区之间就是有源区，该有源区尺寸配合将要注入的浮置-P型结构的长度；
步骤四：注入源栅和漏区；
步骤五：透过所述第一场氧区和所述第二场氧区之间的有源区将浮置-P型结构植入所述N型漂移区的中部。
本发明的实施例的器件是在SOI硅片(绝缘体硅片)上做的，故有埋氧层。本领域的技术人员应当明了采用SOI硅片是为了增强器件的隔离效果，不能理解为对本发明的限制。
以上五个步骤只是给出了主要的步骤，本领域的技术人员应该对其中未提及公知细节明了。
本发明实施例的浮置-P型结构的注入在源漏的注入之后，使浮置-P型结构经受更少的热过程，避免了P型杂质扩散导致N型杂质浓度降低，及浮置-P型结构尺寸变大等因素抬高导通电阻。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (7)

1.一种NLDMOS器件，包括浮置-P型结构，第一场氧区，第二场氧区，N型漂移区，第一场氧区和第二场氧区位于N型漂移区之上相对设置，其特征在于：所述浮置-P型结构位于N型漂移区的中部沿着N型漂移区的沟道方向，所述的第一场氧区和第二场氧区之间是有源区，所述有源区的宽度不小于浮置-P型结构的长度，浮置-P型在N型漂移区的中部。
2.如权利要求1所述的NLDMOS器件，其特征在于：所述浮置-P型结构的数量不少于两个。
3.如权利要求1所述的NLDMOS器件，其特征在于：所述浮置-P型结构在版图上为条状，横截面为长方形。
4.如权利要求1所述的NLDMOS器件，其特征在于：所述浮置-P型结构的横截面为圆形。
5.如权利要求1所述的NLDMOS器件，其特征在于：所述第一场氧区和所述第二场氧区长度不一样。
6.一种NLDMOS器件制造方法，所述NLDMOS器件包括浮置-P型结构，第一场氧区，第二场氧区，N型漂移区，第一场氧区和第二场氧区位于N型漂移区之上相对设置，其特征在于：
步骤一：采用常规的外延生产工艺在埋氧层上形成外延层；
步骤二：采用常规的MOS工艺的进行阱注入，形成所述的N型漂移区；
步骤三：通过生长形成所述第一场氧区和所述第二场氧区，所述第一场氧区和第二场氧区之间就是有源区，该有源区尺寸配合将要注入的浮置-P型结构的长度；
步骤四：注入源栅和漏区；
步骤五：透过所述第一场氧区和所述第二场氧区之间的有源区将浮置-P型结构植入所述N型漂移区的中部；
所述浮置-P型结构的植入步骤在源漏的注入步骤之后进行。
7.如权利要求6所述的NLDMOS器件制造方法，其特征在于：所述浮置-P型结构的注入能量为200Kev～2000Kev。
CN 200910188704 2009-12-03 2009-12-03 Nldmos器件及其制造方法 Active CN102088031B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN 200910188704 CN102088031B (zh) 2009-12-03 2009-12-03 Nldmos器件及其制造方法
PCT/CN2010/079412 WO2011066802A1 (en) 2009-12-03 2010-12-03 N type lateral double diffused metal oxide semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200910188704 CN102088031B (zh) 2009-12-03 2009-12-03 Nldmos器件及其制造方法

Publications (2)

Publication Number Publication Date
CN102088031A CN102088031A (zh) 2011-06-08
CN102088031B true CN102088031B (zh) 2013-04-17

Family

ID=44099741

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200910188704 Active CN102088031B (zh) 2009-12-03 2009-12-03 Nldmos器件及其制造方法

Country Status (2)

Country Link
CN (1) CN102088031B (zh)
WO (1) WO2011066802A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102280481B (zh) * 2011-08-01 2016-04-20 上海华虹宏力半导体制造有限公司 横向双扩散金属氧化物半导体器件及其制造方法
CN104241358B (zh) * 2013-06-19 2017-02-08 上海华虹宏力半导体制造有限公司 射频ldmos器件及其制造方法
CN115831757B (zh) * 2023-02-08 2023-04-28 合肥晶合集成电路股份有限公司 半导体结构的制作方法以及半导体结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1779987A (zh) * 2005-10-14 2006-05-31 西安电子科技大学 可集成的高压p型ldmos晶体管结构及其制备方法
CN101465378A (zh) * 2007-12-20 2009-06-24 夏普株式会社 半导体器件及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19839970C2 (de) * 1998-09-02 2000-11-02 Siemens Ag Randstruktur und Driftbereich für ein Halbleiterbauelement sowie Verfahren zu ihrer Herstellung
JP2001274414A (ja) * 2000-03-24 2001-10-05 Toshiba Corp 電力用半導体素子およびその駆動方法
US7535057B2 (en) * 2005-05-24 2009-05-19 Robert Kuo-Chang Yang DMOS transistor with a poly-filled deep trench for improved performance
DE102006024504B4 (de) * 2006-05-23 2010-09-02 Infineon Technologies Austria Ag Leistungshalbleiterbauelement mit vertikaler Gatezone und Verfahren zur Herstellung desselben
CN101488526A (zh) * 2009-02-27 2009-07-22 东南大学 N型绝缘体上硅的横向双扩散金属氧化物半导体晶体管
CN101593774B (zh) * 2009-06-10 2012-05-23 苏州博创集成电路设计有限公司 P型绝缘体上硅的横向双扩散金属氧化物半导体晶体管

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1779987A (zh) * 2005-10-14 2006-05-31 西安电子科技大学 可集成的高压p型ldmos晶体管结构及其制备方法
CN101465378A (zh) * 2007-12-20 2009-06-24 夏普株式会社 半导体器件及其制造方法

Also Published As

Publication number Publication date
WO2011066802A1 (en) 2011-06-09
CN102088031A (zh) 2011-06-08

Similar Documents

Publication Publication Date Title
CN103367445B (zh) 带有积累增益植入物的横向双扩散金属氧化物半导体
CN101510561B (zh) 超结纵向双扩散金属氧化物半导体管
CN101399288B (zh) 一种ldmos芯片的轻掺杂漂移区结构形成方法
CN102184944B (zh) 一种横向功率器件的结终端结构
CN102044563A (zh) Ldmos器件及其制造方法
CN107204372A (zh) 一种优化终端结构的沟槽型半导体器件及制造方法
CN101916729B (zh) 具有多层超结结构的绝缘体上硅ldmos器件制作方法
CN103178087B (zh) 超高压ldmos器件结构及制备方法
CN101916780A (zh) 一种具有多层超结结构的ldmos器件
CN104716177A (zh) 一种改善漏电的射频ldmos器件及其制造方法
CN106206735A (zh) Mosfet及其制造方法
CN106098777A (zh) 一种分裂栅积累型dmos器件
CN103035730A (zh) 射频ldmos器件及其制造方法
CN105914231B (zh) 电荷存储型igbt及其制造方法
CN104659090B (zh) Ldmos器件及制造方法
CN105977302A (zh) 一种具有埋层结构的槽栅型mos
CN102088031B (zh) Nldmos器件及其制造方法
CN103681817B (zh) Igbt器件及其制作方法
CN102130176B (zh) 一种具有缓冲层的soi超结ldmos器件
CN110047930A (zh) Vdmos器件
CN102157377B (zh) 超结vdmos器件及其制造方法
CN206976353U (zh) 一种优化终端结构的沟槽型半导体器件
CN102646712B (zh) 一种ldmos器件及其制造方法
KR101315699B1 (ko) 초접합 트렌치 구조를 갖는 파워 모스펫 및 그 제조방법
CN104716179A (zh) 一种具有深孔的ldmos器件及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170926

Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8

Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd.

Address before: 214000 No. 5 Hanjiang Road, national hi tech Industrial Development Zone, Wuxi, Jiangsu, China

Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd.

Patentee before: Wuxi CSMC Semiconductor Co., Ltd.