CN101399288B - 一种ldmos芯片的轻掺杂漂移区结构形成方法 - Google Patents
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Abstract
一种LDMOS芯片的轻掺杂漂移区结构及形成方法,首先在LDD掺杂前结构的上表面覆盖一层薄膜层,形成覆盖薄膜层后的LDD附近结构,再通过物理化学方法在LDD附近结构形成离子注入阻挡层进而形成LDD掺杂前结构,阻挡层其厚度从靠近栅区一侧到靠近漏区一侧逐渐减小,最后对LDMOS芯片器件的表面进行N型杂质的离子注入,最终形成一个纵向和横向同时近似线性增加的LDD结构。本发明的LDD在横向和纵向同时形成浓度梯度,使LDD掺杂浓度从靠近栅侧到靠近漏侧线性上升,与常规LDMOS相比,本发明可在保持漏极电阻基本不变的情况下提高器件击穿电压,或者在保持器件击穿电压基本不变的同时大大减小漏极电阻,提高了LDMOS器件频率和功率性能。
Description
技术领域
本发明涉及一种半导体芯片结构,尤其涉及一种LDMOS芯片的轻掺杂漂移区的新结构形成方法,主要应用于通信、雷达等领域。
背景技术
横向双扩散金属氧化物半导体(LDMOS)器件由于具有多方面优点,在通信、雷达等领域有广泛的应用。为了获得较大的输出功率和较高的可靠性,通常要求源漏区有较高的反向击穿电压。常规的做法是在MOS管漏极的一侧制作一个轻掺杂漂移区(LDD),用于降低漏区的掺杂浓度,扩展电离层宽度以获得较高的反向击穿电压。
图1为常规LDMOS芯片结构,包括源极1、P+衬底2、P型双次扩散区3、N型源区4、金属硅化物和栅极5、栅多晶硅6、栅氧7、常规轻掺杂漂移区(LDD)8、P型外延9、漏极10、N型漏区11等,P型双次扩散区3在栅氧7下部分形成沟道区,LDD 8位于沟道区和N型漏区11之间。图2为常规LDMOS芯片的LDD8附近芯片横向净掺杂浓度分布图,图中12为Y轴坐标横向净掺杂浓度cm-3,13为常规结构净掺杂浓度曲线,14为沟道区,15(16)为常规LDD靠近栅侧,17为N型区域,18为P型区域,19为LDD区域,20(22)为常规LDD靠近漏侧,21为N型漏区,23为净掺杂浓度零点;从图2中可以看出,从常规LDD靠近栅侧15(16)到常规LDD靠近漏侧20(22),常规LDD的掺杂浓度是均匀分布的。因此,在常规LDD附近电场分布呈现一个近似三角形,如图3所示,图中24为Y轴坐标E电场V/cm2,27为常规LDD三角形电场,25(26、28、29)为常规LDMOS结构结电场覆盖区域,从图3中可以看出,结击穿电压大小可采用结电场下覆盖图形(25、26、28、29所围区域)的面积表征,该面积可近似为常规LDD三角形电场27的面积。对于选定的半导体材料,其起始点电场是相同的,即图3所示25处高度是不可以改变的。由于材料击穿时能承担电场是由于其禁带宽度决定的,而常规LDD三角形电场27斜边(25-28)的斜率是随着LDD掺杂浓度的变化而变化的,LDD掺杂浓度越低斜率绝对值越大,常规LDD三角形电场27的面积越大,LDMOS器件击穿电压越高;反之亦然。但是LDD掺杂浓度的降低将导致LDD杂质总量减少,从而引起源漏导通电阻变大,导致LDMOS器件的高频增益急剧降低,器件频率和功率特性变差。因此减小漏极电阻和提高器件击穿电压,是常规LDD结构LDMOS芯片很难调和的一对矛盾。
如图4A所示,常规LDMOS芯片LDD形成方法是在硅外延片上通过氧化、腐蚀、离子注入、扩散、退火等各种微电子工艺形成结构41,然后对结构41进行N型杂质(如砷As)的离子注入40,注入的能量和剂量根据器件参数要求而定,最后进行杂质的退火激活等,即可形成图4B所示的常规LDD结构8。
发明内容
本发明解决的问题是:克服现有技术的不足,提供一种LDMOS芯片的轻掺杂漂移区结构形成方法,本发明在减小漏极电阻的同时提高了器件击穿电压,改善了LDMOS器件的频率和功率特性,有效解决了LDMOS芯片减小漏极电阻和提高器件击穿电压之间的矛盾。
本发明的技术解决方案是:一种LDMOS芯片的轻掺杂漂移区结构形成方法,其特征在于包括以下步骤:
第一步:在待掺杂的轻掺杂漂移区的上表面覆盖一层薄膜层,形成覆盖薄膜层后的轻掺杂漂移区附近结构,所述薄膜层采用二氧化硅,厚度为几百纳米的量级;
第二步:通过物理化学方法在轻掺杂漂移区附近结构形成离子注入阻挡层,所述阻挡层其厚度从靠近栅区一侧到靠近漏区一侧逐渐减小,进而形成轻掺杂漂移区掺杂前结构;
第三步:对LDMOS芯片器件的表面进行N型杂质的离子注入,使轻掺杂漂移区的掺杂浓度在纵向和横向同时形成近似线性增加的浓度梯度,所述阻挡层去除或保留,所述的纵向为从LDMOS芯片上表面到下表面直至衬底下方,所述的横向为从靠近栅区一侧到靠近漏区一侧。
本发明与现有技术相比的优点在于:
(1)本发明中的LDD并非均匀掺杂,而是在横向和纵向形成浓度梯度,使LDD掺杂浓度从靠近栅侧到靠近漏侧线性上升,从而解决了常规LDD结构LDMOS芯片减小漏极电阻和提高器件击穿电压的矛盾,与常规LDD结构LDMOS器件相比,可以在保持漏极电阻基本不变的情况下提高器件击穿电压,或者在保持器件击穿电压基本不变的同时大大减小漏极电阻,从而提高LDMOS器件频率和功率性能。
(2)本发明LDD的形成方法不同于常规的LDD形成方法,相对于常规的形成方法,本发明通过调整阻挡层厚度,被注入杂质离子经过不同的阻挡层厚度后,达到单晶硅内的深度和浓度是不等的,因此从靠近栅侧到靠近漏侧厚度逐渐减小的阻挡层使得掺杂浓度在纵向和横向同时形成一个浓度梯度。从而优化电离层中正离子分布并调整寄生的分布电阻来达到提高了器件击穿电压的同时,减小漏极电阻,改善了LDMOS器件的频率和功率特性,有效解决了LDMOS芯片提高器件击穿电压和减小漏极电阻之间的矛盾。
附图说明
图1为常规LDMOS芯片结构剖面图;
图2为常规LDMOS芯片LDD附近横向净掺杂浓度分布图;
图3为常规LDMOS芯片LDD附近横向电场分布示意图;
图4为常规LDMOS芯片LDD形成示意图,其中4A为形成前结构和掺杂示意图,4B为形成后的结构;
图5为采用本发明的LDMOS芯片结构剖面图;
图6为采用本发明的LDMOS芯片LDD附近横向净掺杂浓度分布图;
图7为采用本发明的LDMOS芯片LDD附近横向电场分布示意图;
图8为采用本发明LDMOS芯片的LDD形成示意图,其中8A为覆盖薄膜层示意图,8B为形成的掺杂阻挡层和掺杂示意图,8C为形成后的结构。
具体实施方式
如图5所示,本发明的结构包括源极1、P+衬底2、P型双次扩散区3、N型源区4、金属硅化物和栅极5、栅多晶硅6、栅氧7、常规轻掺杂漂移区(LDD)30、P型外延9、漏极10、N型漏区11等,P型双次扩散区3在栅氧7下部分形成沟道区,LDD 30位于沟道区和N型漏区11之间,本发明的LDMOS芯片结构特点是在沟道区和N型漏区11之间形成的LDD 30其掺杂浓度是非均匀的,掺杂浓度在纵向(从芯片上表面到下表面直至陈底下方)和横向(靠近栅区一侧到靠近漏区一侧)同时形成一个浓度梯度。如图6所示,图中12为Y轴坐标横向净掺杂浓度cm-3,31为本发明净掺杂浓度曲线,14为沟道区,32(33)为本发明LDD靠近栅侧,17为N型区域,18为P型区域,19为本发明LDD区域;34(35)为本发明LDD靠近漏侧;21为N型漏区;23为净掺杂浓度零点,从图6中可以看出本发明LDD的掺杂浓度从靠近栅侧32(33)到靠近漏侧34(35)是线性上升的。如果在源极和漏极之间加上电压,LDD将会被电离。而本发明的LDD 30中被电离的正离子是线性增加的,这样就使LDD30从靠近栅侧32(33)到靠近漏侧34(35)之间的电场基本相等,从而使LDD30电场下的面积达到最大,如图7中的四边形31所示。同样由于LDMOS芯片器件的击穿电压可以用LDD 30电场下的面积(36、37、38、39所围区域)表征,该区域面积又近似等于四边形31的面积。因此,由于LDD 30电场下的面积的增加,LDMOS器件的击穿电压上升,同时因为图6中LDD 30右侧的浓度是不断上升的,整个LDD 30中的杂质总量比常规做法下LDD 8的杂质总量要高许多,在LDMOS器件开启时,由于杂质总量从靠近栅的一侧到靠近漏的一侧(LDD 30)是不断提高,可动电荷不断地上升,电导率不断地提高,从而,LDD 30的分布电阻是从左到右不断地下降的,从而起到有效减小LDD30串连电阻的作用。因此根据不同LDMOS器件对击穿电压和导通电阻的不同要求,合理设计LDD浓度梯度,便可以得到非常理想的结果。
本发明LDD结构的形成方法与常规的LDD形成方法不同。
第一步是本发明在通过常规方法形成图4A中的结构41后,并不马上对LDD进行N型杂质(如砷As)的离子注入,而是如图8A所示,通过淀积、生长、溅射、蒸发等各种方式在结构41的上表面覆盖一层薄膜层42,形成覆盖薄膜层42后的LDD附近结构43。其中薄膜层42可以为介质或有机材料薄膜,如二氧化硅、氮化硅、光刻胶等,对薄膜层42的主要要求是为了不影响器件特性应该容易去除且不容易对器件造成污染,薄膜层42的厚度可以视材料对离子注入掩蔽能力的不同而不同,并根据LDMOS器件参数对击穿电压和导通电阻的不同要求而变化,比如阻挡层为二氧化硅的情形下,厚度一般在几百纳米的量级。
第二步是通过对薄膜层42进行选择性刻蚀、腐蚀等各种物理化学方法,形成如图8B所示的离子注入阻挡层44,从而形成本发明LDD掺杂前结构46。阻挡层44的厚度是非均匀的,从靠近栅区的一侧到靠近漏区的一侧厚度逐渐减小,为近似三角形结构。
第三步是对整个器件的表面进行N型杂质(如砷As)的离子注入45,注入杂质的能量和剂量均应大于常规LDD离子注入40的能量和剂量,具体的数值根据器件参数特性对击穿和导通电阻要求的不同而不同。由于阻挡层44对注入离子(如砷)的阻挡作用,注入杂质离子经过不同的阻挡层厚度后,达到单晶硅内的深度和浓度是不等的,因此从靠近栅侧到靠近漏侧厚度逐渐减小的阻挡层44使得LDD的掺杂浓度在纵向和横向同时形成一个浓度梯度,并从靠近栅区的一侧到靠近漏区的一侧近似线性增加,从而最终完成如图8C所示LDD结构30。LDD30上面的阻挡层44可根据材料性质或后面工艺的要求选择去除或保留。
本发明未详细描述内容为本领域技术人员公知技术。
Claims (1)
1.一种LDMOS芯片的轻掺杂漂移区结构形成方法,其特征在于包括以下步骤:
第一步:在待掺杂的轻掺杂漂移区的上表面覆盖一层薄膜层,形成覆盖薄膜层后的轻掺杂漂移区附近结构,所述薄膜层采用二氧化硅,厚度为几百纳米的量级;
第二步:通过物理化学方法在轻掺杂漂移区附近结构形成离子注入阻挡层,所述阻挡层其厚度从靠近栅区一侧到靠近漏区一侧逐渐减小,进而形成轻掺杂漂移区掺杂前结构;
第三步:对LDMOS芯片器件的表面进行N型杂质的离子注入,使轻掺杂漂移区的掺杂浓度在纵向和横向同时形成近似线性增加的浓度梯度,所述阻挡层去除或保留,所述的纵向为从LDMOS芯片上表面到下表面直至衬底下方,所述的横向为从靠近栅区一侧到靠近漏区一侧。
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CN102097482B (zh) * | 2010-12-31 | 2012-07-18 | 杭州电子科技大学 | 集成双纵向沟道soi ldmos器件单元 |
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TWI467766B (zh) * | 2012-08-31 | 2015-01-01 | Nuvoton Technology Corp | 金氧半場效電晶體及其製造方法 |
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