TWI463661B - 高壓元件及其製造方法 - Google Patents

高壓元件及其製造方法 Download PDF

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TWI463661B
TWI463661B TW100108936A TW100108936A TWI463661B TW I463661 B TWI463661 B TW I463661B TW 100108936 A TW100108936 A TW 100108936A TW 100108936 A TW100108936 A TW 100108936A TW I463661 B TWI463661 B TW I463661B
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TW201240083A (en
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Tsung Yi Huang
Chien Hao Huang
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Richtek Technology Corp
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Description

高壓元件及其製造方法
本發明係有關一種高壓元件及其製造方法，特別是指一種增強崩潰防護電壓之高壓元件及其製造方法。
第1A與第1B圖分別顯示先前技術之雙擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)元件剖視圖與立體圖，如第1A與第1B圖所示，於P型基板11中形成絕緣區12，以定義元件區100，絕緣區12例如為淺溝槽絕緣(shallow trench isolation,STI)結構或區域氧化(local oxidation of silicon,LOCOS)結構。於元件區100中，形成閘極13、漂移區14、汲極15、與源極16。其中，漂移區14、汲極15、源極16係由微影技術或以部分或全部之閘極13、絕緣區12為遮罩，以定義各區域，並分別以離子植入技術，將N型雜質，以加速離子的形式，植入定義的區域內。其中，汲極15與源極16分別位於閘極13兩側下方，漂移區14位於汲極15側且部分位於閘極13下方。DDDMOS元件為高壓元件，亦即其係設計供應用於較高的操作電壓下，但當DDDMOS元件需要與一般較低操作電壓之元件整合於同一基板上時，為配合較低操作電壓之元件製程，需要以相同的離子植入參數來製作DDDMOS元件和低壓元件，使得DDDMOS元件的離子植入參數受到限制，因而降低了DDDMOS元件崩潰防護電壓，限制了元件的應用範圍。若不犧牲DDDMOS元件崩潰防護電壓，則必須增加製程步驟，另行以不同離子植入參數的步驟來製作DDDMOS元件，但如此一來將提高製造成本，才能達到所欲的崩潰防護電壓。
第2A與第2B圖顯示先前技術之橫向擴散(lateral diffused metal oxide semiconductor,LDMOS)元件剖視圖與立體圖，與第1A與第1B圖之先前技術相較，第2A與第2B圖所顯示之LDMOS元件另具有本體區17、本體極18，且其閘極13有一部分位於絕緣區12上。同樣地，當LDMOS元件需要與一般較低操作電壓之元件整合於同一基板上時，因受限於整合製程，而降低了LDMOS元件崩潰防護電壓，限制了元件的應用範圍，若不犧牲LDMOS元件崩潰防護電壓，則也必須增加製程步驟，提高製造成本，才能達到所欲的崩潰防護電壓。
有鑑於此，本發明即針對上述先前技術之不足，提出一種高壓元件及其製造方法，在不增加製程步驟的情況下，提高元件操作之崩潰防護電壓，增加元件的應用範圍，並可整合於低壓元件之製程。
本發明目的在提供一種高壓元件及其製造方法。
為達上述之目的，就其中一個觀點言，本發明提供了一種高壓元件形成於一第一導電型基板中，該基板利用絕緣區以定義一元件區，該高壓元件包含：一漂移區，位於該元件區中，其具有第二導電型雜質摻雜，且該漂移區由上視圖視之，分別在橫向與縱向上，第二導電型雜質之濃度分布大致具有週期性的變化；位於該基板表面上，元件區中之一閘極；以及位於該元件區中，該閘極兩側之第二導電型源極、與第二導電型汲極。
在其中一種實施型態中，該漂移區可包括第一漂移區與第二漂移區，分別介於該源極與該閘極之間，以及該汲極與該閘極之間。
在其中一種較佳實施型態中，該基板中可更包含另一元件，其具有第二導電型井區，其中，該漂移區係利用與該第二導電型井區相同之光罩與離子植入製程步驟所形成。
在另一種較佳實施型態中，該漂移區之第二導電型雜質之濃度分布宜呈複數迴圈圖案，該複數迴圈圖案大致環繞同一中心，且迴圈圖案之角落為完整或不完整。
就另一觀點，本發明也提供了一種高壓元件製造方法，包含：提供一基板，並於其中形成第一導電型井區以及絕緣區以定義元件區；於該元件區中形成一漂移區，其具有第二導電型雜質摻雜，且該漂移區由上視圖視之，分別在橫向與縱向上，第二導電型雜質之濃度分布大致具有週期性的變化；於該基板表面上，元件區中，形成一閘極；以及於該元件區中，該閘極兩側，形成第二導電型源極、與第二導電型汲極，且以該漂移區隔開該源極與該汲極。
在其中一種較佳實施型態中，形成該漂移區之步驟宜包括：利用一光罩，於該基板上形成由上視圖視之，於橫向與縱向上大致具有周期變化圖案之光阻結構；利用離子植入技術，將第二導電型雜質，以加速離子形式，植入該基板中；以及利用熱擴散技術，使第二導電型雜質擴散，形成該漂移區。
在其中一種實施型態中，該光罩宜具有至少一迴圈圖案，且該迴圈圖案之角落可完整或不完整。
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。
請參閱第3A-3E圖，顯示本發明的第一個實施例，第3A圖顯示本發明應用於DDDMOS元件之立體示意圖。需先說明的是，為顯示發明重點，將閘極13與基板11分開顯示，以方便了解。如第3A圖所示，於基板11中，形成絕緣區12以定義元件區100，其中基板11例如為P型但不限於為P型(亦可以為N型)；絕緣區12例如為STI結構或區域氧化LOCOS結構。於元件區100中，形成閘極13、漂移區14a、汲極15、與源極16；其中，汲極15與源極16例如為N型但不限於為N型(亦可以為P型)。漂移區14a為第二導電型雜質摻雜，例如為N型但不限於為N型(亦可以為P型)，與先前技術不同的是，由上視圖第3B圖視之，漂移區14a分別在橫向與縱向上，其第二導電型雜質之濃度分布，大致具有週期性的變化，如圖中漂移區14a之複數矩形同心迴圈所示意，矩形同心迴圈中格線區域示意第二導電型雜質濃度較高之區域；而格線區域間之灰色區域示意第二導電型雜質濃度較低之區域。此種安排方式的優點包括：在元件參數上，可提高DDDMOS元件的崩潰防護電壓；在製程上，當本實施例DDDMOS元件整合於低壓元件製程時，可利用一張光罩與一組離子植入製程，例如但不限於為低壓元件製程中之第二導電型井區光罩，與第二導電型井區離子植入製程，來完成雜質之濃度分布具有週期性變化的漂移區14a，而不需要另外新增光罩或製程步驟，故可降低製造成本。
請繼續參閱第3C圖，顯示本實施例形成漂移區14a之剖視示意圖，如第3C圖所示，於基板11上，利用一張光罩之一段微影製程，形成光阻結構14c，以定義離子植入的區域；此光阻結構14c大致上複製了光罩上的圖案，由上視圖視之，其具有矩形同心迴圈圖案。利用離子植入技術，將第二導電型雜質，以加速離子植入方式植入由光阻結構14c所定義的區域，如圖中虛線箭頭所示意，使基板11中形成如圖中14b之第二導電型雜質分布區域。經過多道的熱製程之後，因第二導電型雜質分布區域14b中第二導電型雜質擴散，其擴散的範圍，如第3D圖中虛線箭頭所示，以形成漂移區14a。由於光阻結構14c由上視圖視之，其具有甜甜圈形的迴圈圖案，因此在漂移區14a中，第二導電型雜質的濃度分布，例如為第3E圖所示，在橫向上與縱向上(橫軸x表示位置、縱軸N表示濃度)，皆有週期性的變化。
漂移區14a中第二導電型雜質之濃度分布，在橫向與縱向上，大致具有週期性的變化，但不限於為如圖中漂移區14a之複數矩形同心迴圈所示意；舉例而言，亦可以如第4A圖(其中迴圈角落部分不完整而與第3B圖具有完整角落的圖案不同)、或第4B圖之大致環繞同一中心之圓形甜甜圈形的迴圈、或第4C圖之圖案所示意者，等等。總之，僅需在橫向與縱向上，大致具有週期性的變化即可，而其形狀與排列方式可以任意變化。
第5A-5B圖顯示本發明的另一個實施例，第5A圖顯示本發明應用於LDMOS元件之立體示意圖。需先說明的是，為顯示發明重點，將閘極13與基板11分開顯示，以方便了解。如第5A圖所示，於基板11中，形成絕緣區12以定義元件區100，其中基板11例如為P型但不限於為P型；絕緣區12例如為STI結構或區域氧化LOCOS結構。於元件區100中，形成閘極13、漂移區14a、汲極15、源極16、本體區17、與本體極18；其中，汲極15與源極16例如為N型但不限於為N型；而本體區17與本體極18例如為P型但不限於為P型。與先前技術不同的是，由上視圖第5B圖視之，漂移區14a分別在橫向與縱向上，其第二導電型雜質之濃度分布，大致具有週期性的變化，如圖中漂移區14a之複數矩形同心迴圈所示意，矩形同心迴圈中格線區域示意第二導電型雜質濃度較高之區域；而格線區域間之灰色區域示意第二導電型雜質濃度較低之區域。此種安排方式的優點包括：在元件參數上，可提高LDMOS元件的崩潰防護電壓；在製程上，當本實施例LDMOS元件整合於低壓元件製程時，可利用一張光罩與一道離子植入製程來完成雜質之濃度分布具有週期性變化的漂移區14a，而不需要另外新增光罩或製程步驟，故可降低製造成本。
漂移區14a中第二導電型雜質之濃度分布，在橫向與縱向上，大致具有週期性的變化，但不限於為如第5B圖中漂移區14a之複數矩形同心迴圈所示意，亦可以如第5C圖所示之圖案所示意，當然亦可以為其他任意規則或不規則的排列形式，只要在橫向與縱向上，第二導電型雜質之濃度分布，大致具有週期性的變化即可。
請參閱第6A-6B圖，顯示本發明的另一個實施例，第6A圖顯示本發明應用於DDDMOS元件之立體示意圖。與第一個實施例不同的是，本實施例應用於對稱型的DDDMOS。如第6A與6B圖所示，漂移區14a除了形成於汲極15與閘極13間的基板11中之外，於源極16與閘極13間的基板11中，亦可形成另一漂移區14a。同樣地，此另一漂移區14a亦可以應用本發明概念，利用同一道微影製程，在橫向與縱向上，使第二導電型雜質之濃度分布，大致具有週期性的變化。
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如深井區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術；又如，所謂週期性的變化，並不表示必須絕對無誤差地雜質濃度週期性變化，而應視為可容許有微幅的偏離；再如，迴圈圖案除矩形、圓形外，亦可為其他形狀如六角形、八角形等。本發明的範圍應涵蓋上述及其他所有等效變化。
11．．．基板
12．．．絕緣區
13．．．閘極
14,14a．．．漂移區
15．．．汲極
16．．．源極
17．．．本體區
18．．．本體極
100．．．元件區
x．．．橫向或縱向位置
N．．．漂移區14a中第二導電型雜質濃度
第1A圖顯示先前技術之DDDMOS元件剖視圖。
第1B圖顯示先前技術之DDDMOS元件立體圖。
第2A圖顯示先前技術之LDMOS元件剖視圖。
第2B圖顯示先前技術之LDMOS元件立體圖。
第3A-3E圖顯示本發明的第一個實施例。
第4A、4B、與4C圖舉例示意本發明實施例之漂移區中第二導電型雜質之濃度分布。
第5A-5B圖顯示本發明的另一個實施例。
第5C圖舉例示意本發明實施例之漂移區中第二導電型雜質之濃度分布。
第6A-6B圖顯示本發明的另一個實施例。
11．．．基板
12．．．絕緣區
13．．．閘極
14a．．．漂移區
15．．．汲極
16．．．源極
17．．．本體區
18．．．本體極
100．．．元件區

Claims (10)

  1. 一種高壓元件，形成於一第一導電型基板中，該基板利用絕緣區以定義一元件區，該高壓元件包含：一漂移區，位於該元件區中該基板表面下，其具有第二導電型雜質摻雜，且該漂移區由上視圖視之，分別在橫向與縱向上，第二導電型雜質之濃度分布大致具有週期性的變化；位於該基板表面上，元件區中之一閘極；以及位於該元件區中該基板表面下，該閘極兩側之第二導電型源極、與第二導電型汲極；其中該漂移區由上視圖視之，完全位於該源極與該汲極之間，該漂移區具有：複數第一子區，且該第一子區之第二導電型雜質摻雜具有第一濃度；以及複數第二子區，與該複數第一子區在橫向與縱向上，交錯排列連接，且該第二子區之第二導電型雜質摻雜具有第二濃度；其中該第一濃度與第二濃度在橫向與縱向上交錯排列，產生該週期性的變化。
  2. 如申請專利範圍第1項所述之高壓元件，其中該漂移區包括第一漂移區與第二漂移區，分別介於該源極與該閘極之間，以及該汲極與該閘極之間。
  3. 如申請專利範圍第1項所述之高壓元件，其中該基板中更包含另一元件，其具有第二導電型井區，其中，該漂移區係利用與該第二導電型井區相同之光罩與離子植入製程步驟所形成。
  4. 如申請專利範圍第1項所述之高壓元件，其中複數第一子區與該複數第二子區呈複數迴圈圖案，該複數迴圈圖案大致 環繞同一中心，且迴圈圖案之角落為完整或不完整。
  5. 一種高壓元件製造方法，包含：提供一基板，並於其中形成第一導電型井區以及絕緣區以定義元件區；於該元件區中該基板表面下形成一漂移區，其具有第二導電型雜質摻雜，且該漂移區由上視圖視之，分別在橫向與縱向上，第二導電型雜質之濃度分布大致具有週期性的變化；於該基板表面上，元件區中，形成一閘極；以及於該元件區中該基板表面下，該閘極兩側，形成第二導電型源極、與第二導電型汲極，且以該漂移區隔開該源極與該汲極；其中該漂移區由上視圖視之，完全位於該源極與該汲極之間，該漂移區具有：複數第一子區，且該第一子區之第二導電型雜質摻雜具有第一濃度；以及複數第二子區，與該複數第一子區在橫向與縱向上，交錯排列連接，且該第二子區之第二導電型雜質摻雜具有第二濃度；其中該第一濃度與第二濃度在橫向與縱向上交錯排列，產生該週期性的變化。
  6. 如申請專利範圍第5項所述之高壓元件製造方法，其中該漂移區包括第一漂移區與第二漂移區，分別介於該源極與該閘極之間，以及該汲極與該閘極之間。
  7. 如申請專利範圍第5項所述之高壓元件製造方法，其中該基板中更包含另一元件，其具有第二導電型井區，其中，形成該漂移區之步驟係利用與該第二導電型井區相同之光罩與離子植入製程步驟所形成。
  8. 如申請專利範圍第5項所述之高壓元件製造方法，其中該形成該漂移區之步驟包括：利用一光罩，於該基板上形成由上視圖視之，於橫向與縱向上大致具有周期變化圖案之光限結構；利用離子植入技術，將第二導電型雜質，以加速離子形式，植入該基板中，以形成該複數第一子區；以及利用熱擴散技術，使第二導電型雜質擴散，以形成該複數第二子區。
  9. 如申請專利範圍第8項所述之高壓元件製造方法，其中該複數第一子區與該複數第二子區呈複數迴圈圖案。
  10. 如申請專利範圍第9項所述之高壓元件製造方法，其中該迴圈圖案之角落不完整。
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