TWI614892B - 高壓元件及其製造方法 - Google Patents

高壓元件及其製造方法 Download PDF

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TWI614892B
TWI614892B TW106100554A TW106100554A TWI614892B TW I614892 B TWI614892 B TW I614892B TW 106100554 A TW106100554 A TW 106100554A TW 106100554 A TW106100554 A TW 106100554A TW I614892 B TWI614892 B TW I614892B
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drain
ldd
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TW201826536A (zh
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蔡宗穎
游焜煌
黃宗義
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立錡科技股份有限公司
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Priority to TW106100554A priority Critical patent/TWI614892B/zh
Priority to US15/490,662 priority patent/US9853100B1/en
Priority to CN201710252497.XA priority patent/CN108288645A/zh
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Abstract

本發明提出一種高壓元件及其製造方法。高壓元件包含：半導體基板、絕緣結構、閘極、本體區、井區、源極與汲極、以及輕摻雜擴散(lightly doped diffusion, LDD)區。其中，絕緣結構形成於半導體基板之上表面上，用以定義元件區。輕摻雜擴散區形成於元件區中之井區上，於橫向上，輕摻雜擴散區介於閘極與汲極之間，且輕摻雜擴散區不與汲極鄰接。

Description

高壓元件及其製造方法
本發明有關於一種高壓元件及其製造方法，特別是指一種能夠提高不導通操作時之崩潰防護電壓的高壓元件及其製造方法。
第1A與1B圖分別顯示一種習知高壓元件100的剖視示意圖與上視示意圖。其中，所謂的高壓元件，係指於正常操作時，施加於汲極的電壓高於5V；一般而言，高壓元件的汲極與閘極間，具有漂移區12a(如第1A圖中虛線範圍所示意)，將汲極與閘極分隔，且漂移區之橫向長度根據正常操作時所承受的操作電壓而調整。如第1A與1B圖所示，LDMOS元件100包含：井區12、隔絕氧化區13、場氧化區14、本體區16、閘極17、源極18、與汲極19。其中，井區12的導電型為N型，形成於基板11上，隔絕氧化區13為區域氧化(local oxidatiowof silicon,LOCOS)結構，以定義操作區13a，作為高壓元件100操作時主要的作用區。操作區13a的範圍由第1B圖中，粗黑虛線框所示意。閘極17覆蓋部分場氧化區14。為使高壓元件100的導通電阻下降，可減少隔絕氧化區13與場氧化區14的厚度，但如此一來，高壓元件100的崩潰防護電壓將會下降，限制了高壓元件100的應用範圍；而為使高壓元件100的耐壓(withstand voltage)提高，可增加隔絕氧化區13與場氧化區14的厚度，但如此一來，高壓元件100的導通電阻將會提高，操作的速度降低，降低元件的性能。
有鑑於此，本發明提出一種能夠提高不導通操作時之崩潰防護電壓但不影響導通電阻的高壓元件及其製造方法。
就其中一觀點言，本發明提供了一種高壓元件，包含：一半導體基板，於一垂直方向上，具有相對之一上表面與一下表面；一絕緣結構，形成於該上表面上，用以定義一元件區；一閘極，形成於該半導體基板的該上表面上之該元件區中；一本體區，具有一第一導電型，形成於該上表面下之該元件區中，且部分該本體區位於該閘極正下方；一井區，具有一第二導電型，形成於該上表面下之該元件區中，該井區於一橫向上與該本體區鄰接，而形成一接面，且該接面位於該閘極正下方；一源極與一汲極，具有該第二導電型，形成於該上表面下之該元件區中，分別位於該閘極下方之外部靠近該本體區側與遠離該本體區側，且該汲極與該閘極間，由該井區分開；以及一輕摻雜擴散(lightly doped diffusion,LDD)區，具有該第一導電型，形成於該上表面下之該元件區中之該井區上，於該橫向上，該LDD區介於該閘極與該汲極之間，且該LDD區不與該汲極鄰接。
就另一觀點言，本發明提供了一種高壓元件製造方法，包含：提供一半導體基板，於一垂直方向上，其具有相對之一上表面與一下表面；形成一絕緣結構於該上表面上，用以定義一元件區；形成一閘極於該半導體基板的該上表面上之該元件區中；形成一本體區於該上表面下之該元件區中，該本體區具有一第一導電型，且部分該本體區位於該閘極正下方；形成一井區於該上表面下之該元件區中，該井區具有一第二導電型，且該井區於一橫向上與該本體區鄰接，而形成一接面，且該接面位於該閘極正下方；形成一源極與一汲極於該上表面下之該元件區中，該源極與該汲極具有該第二導電型，分別位於該閘極下方之外部靠近該本體區側與遠離該本體區側，且該汲極與該閘極間，由該井區分開；以及形成一輕摻雜擴散(lightly doped diffusion,LDD)區於該上表面 下之該元件區中之該井區上，該LDD區具有該第一導電型，於該橫向上，該LDD區介於該閘極與該汲極之間，且該LDD區不與該汲極鄰接。
在一種較佳的實施型態中，該高壓元件更包含一場氧化區，形成於該上表面上之該元件區中，且部分該場氧化區位於該閘極正下方，且其他部分之場氧化區位於該閘極與該汲極之間。
在一種較佳的實施型態中，該LDD區在橫向上的兩側與該場氧化區鄰接。
在一種較佳的實施型態中，該LDD區由剖視圖視之，其深度自該半導體基板的該上表面開始沿著該垂直方向而向下計算，不深於該場氧化區。
在一種較佳的實施型態中，該高壓元件更包含一輕摻雜井區，具有該第二導電型，形成於該上表面下之該元件區中，該輕摻雜井區於該橫向上的兩側與該井區連接，且該輕摻雜井區之第二導電型雜質濃度低於該井區之第二導電型雜質濃度。
在一種較佳的實施型態中，該LDD區完全不位於該閘極正下方。
在一種較佳的實施型態中，該LDD區於導通及不導通操作時浮接。
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
100,200,300,400,500,600,700‧‧‧高壓元件
11,21‧‧‧半導體基板
12,22‧‧‧井區
12a‧‧‧漂移區
13,23‧‧‧絕緣結構
13a,23a‧‧‧操作區
14,24‧‧‧場氧化區
16,26‧‧‧本體區
17,27‧‧‧閘極
18,28‧‧‧源極
19,29‧‧‧汲極
21a‧‧‧上表面
21b‧‧‧下表面
22a‧‧‧輕摻雜井區
25‧‧‧LDD區
25a,26a‧‧‧光阻層
PN0,PN1,PN2‧‧‧PN接面
第1A與1B圖分別顯示一種先前技術高壓元件100的剖視示意圖與上視示意圖。
第2A-2I圖顯示本發明的第一個實施例。
第3A-3I圖顯示本發明的第二個實施例。
第4A-4I圖顯示本發明的第三個實施例。
第5A-5B圖顯示本發明的第四個實施例。
第6A-6B圖顯示本發明的第五個實施例。
第7圖顯示本發明的第六個實施例。
第8圖示出本發明相較於先前技術能夠提高不導通操作時的崩潰防護電壓的電性示意圖。
第9A-9B圖分別示出先前技術與本發明之撞擊游離分析分佈圖。
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一較佳實施例的詳細說明中，將可清楚的呈現。本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。
請參考第2A-2I圖，其顯示本發明的第一個實施例。如第2A圖所示，首先提供一半導體基板21，其例如但不限於為P型矽基板。如第2A圖所示，半導體基板21於一垂直方向(如圖中實線箭頭所示意)上，具有相對之一上表面21a與一下表面21b。接著，如第2B圖所示，形成井區22於上表面21a下，井區22例如但不限於具有N型導電型。接著，如第2C圖所示，形成絕緣結構23於上表面21a(如圖中虛線所示意)上，以此定義元件區23a。在一實施例中，絕緣結構23例如但不限於可為圖示之區域氧化(local oxidation of silicon,LOCOS)結構。在另一實施例中，絕緣結構23亦可為其他形式的隔離結構，例如但不限於可為一淺溝槽絕緣(shallow trench isolation,STI)結構。
第2D圖顯示對應剖視示意圖第2C圖之上視示意圖。如圖所示，絕緣結構23例如但不限於為一環型結構，以定義環型結構中的元件區23a。接下 來，請參閱第2E圖，例如利用光阻層26a為遮罩，將P型雜質摻雜至上表面21a下之元件區23a中，以形成本體區26。其中，可利用例如但不限於離子植入技術，將P型雜質，以加速離子的形式，如第2E圖中虛線箭號所示意，植入元件區23a中，以形成本體區26。
接著，如第2F圖所示，例如利用光阻層25a為遮罩，將P型雜質摻雜至上表面21a下之元件區23a中，以形成輕摻雜擴散(lightly doped diffusion,LDD)區25。其中，可利用例如但不限於離子植入技術，將P型雜質，以加速離子的形式，如第2F圖中虛線箭號所示意，植入元件區23a中，以形成LDD區25。
接下來，如第2G圖所示，形成閘極27於半導體基板21的上表面21a上之元件區23a中。如圖所示，部分本體區26位於閘極27正下方。此外，井區22形成於上表面21a下之元件區23a中，井區22於橫向(如圖中虛線箭號所示意)上與本體區26鄰接，而形成PN接面PN0，且PN接面PN0位於閘極27正下方。
接下來，如第2H圖所示，形成源極28與汲極29，源極28與汲極29例如但不限於具有N型導電型，形成於上表面21a下之元件區23a中，分別位於閘極27下方之外部靠近本體區26側與遠離本體區26側，且汲極29與閘極27間，由井區22分開。形成源極28與汲極29之步驟，例如但不限於利用絕緣結構23與閘極27為遮罩，或/且由微影技術定義範圍，將N型雜質摻雜至半導體基板21以形成位於半導體基板21的上表面21a下之元件區23a中，閘極27下方之外部之源極28與汲極29。其中，本實施例可利用例如但不限於離子植入技術，將N型雜質，以加速離子的形式，植入半導體基板21中，以形成源極28與汲極29(未示出)。
第2I圖顯示第2H圖之上視示意圖，如圖所示，LDD區25，例如但不限於具有P型導電型，於橫向上(如圖中虛線箭號所示意)，LDD區25介於閘極27與汲極29之間，且LDD區25不與汲極29鄰接。
本發明與先前技術最主要的不同點乃是在於：本發明在上表面21a下之本體區26與汲極29之間，加入LDD區25，使得高壓元件200在不導通操作中，形成較大的空乏區，以降低電場強度，以提高高壓元件200承受的電壓，也就是提高高壓元件200不導通操作的崩潰防護電壓。
以上第2A-2I圖雖係以N型元件為例來加以說明，但相同概念當然也可適用於P型元件，只要相應改變摻雜區即可。
請參考第3A-3I圖，其顯示本發明的第二個實施例。類似地，本實施例亦係以N型高壓元件為例說明。
本實施例的製程步驟或結構大致上與第一個實施例的製程步驟或結構相似，惟差異在於：相較於第一個實施例，本實施例高壓元件300更包含場氧化區24；且在第一實施例之高壓元件200製造方法的步驟中，LDD區25係由獨立的微影製程步驟所定義離子植入步驟的雜質摻雜範圍，而本施例之高壓元件300製造方法的步驟中，LDD區25由與井區22同一個微影製程步驟所定義離子植入步驟的雜質摻雜範圍。
如第3A圖所示，首先提供半導體基板21，其例如但不限於為P型矽基板。如第3A圖所示，半導體基板21於一垂直方向(如圖中實線箭頭所示意)上，具有相對之一上表面21a與一下表面21b。接著，如第3B圖所示，例如但不限於在同一製程步驟中，形成絕緣結構23與場氧化區24於上表面21a上。絕緣結構23用以此定義元件區23a。場氧化區24形成於上表面21a上之元件區23中，且部分場氧化區24位於之後的製程步驟所形成的閘極27正下方，且其他部分之場氧化區24位於閘極27與之後的製程步驟所形成的汲極29之間。須注意的是，場氧化區24同時定義之後的製程步驟所形成的LDD區25之範圍。在一實施例中，絕緣結構23例如但不限於可為圖示之區域氧化(local oxidation of silicon,LOCOS)結 構。在另一實施例中，絕緣結構23亦可為其他形式的隔離結構，例如但不限於可為淺溝槽絕緣(shallow trench isolation,STI)結構。
第3C圖顯示對應剖視示意圖第3B圖之上視示意圖。如圖所示，絕緣結構23例如但不限於為一環型結構，以定義環型結構中的元件區23a。接下來，如第3D圖所示，形成閘極27於半導體基板21的上表面21a上之元件區23a中。如圖所示，部分場氧化區24位於閘極27正下方，且其他部分之場氧化區24位於閘極27與後續的製程步驟所形成的汲極29之間。
接著，如第3E圖所示，形成井區22於上表面21a下，井區22例如但不限於具有N型導電型。接著，利用與井區22相同的遮罩，例如但不限於包含閘極27、絕緣結構23、與場氧化區24；當然，也可以根據實際的需要，加上光阻層(未示出)作為遮罩，此為本領域中具有通常知識者所熟知，在此不予贅述。如第3F圖所示，例如將P型雜質摻雜至上表面21a下之元件區23a中，以形成輕摻雜擴散(lightly doped diffusion,LDD)區25。其中，可利用例如但不限於離子植入技術，將P型雜質，以加速離子的形式，如第2F圖中虛線箭號所示意，植入元件區23a中，以形成LDD區25。由於LDD區25之P型雜質濃度，遠低於源極28與汲極29之N型雜質濃度，因此如圖所示，即使在源極28與汲極29摻雜了與LDD區25之P型雜質同樣的雜質，對源極28與汲極29來說，是可以被忽略的。
接下來，請參閱第3G圖，例如利用光阻層26a為遮罩，將P型雜質摻雜至上表面21a下之元件區23a中，以形成本體區26。其中，可利用例如但不限於離子植入技術，將P型雜質，以加速離子的形式，如第3G圖中虛線箭號所示意，植入元件區23a中，以形成本體區26。其中部分本體區26位於閘極27正下方。此外，井區22形成於上表面21a下之元件區23a中，井區22於橫向(如圖中虛線箭號所示意)上與本體區26鄰接，而形成PN接面PN0，且PN接面PN0位於閘極27正下方。
接下來，如第3H圖所示，形成源極28與汲極29，源極28與汲極29例如但不限於具有N型導電型，形成於上表面21a下之元件區23a中，分別位於閘極27下方之外部靠近本體區26側與遠離本體區26側，且汲極29與閘極27間，由井區22分開。形成源極28與汲極29之步驟，例如但不限於利用絕緣結構23、場氧化區24與閘極27為遮罩，或/且由微影技術定義範圍，將N型雜質摻雜至半導體基板21，以形成位於半導體基板21的上表面21a下之元件區23a中，閘極27下方之外部之源極28與汲極29。其中，本實施例可利用例如但不限於離子植入技術，將N型雜質，以加速離子的形式，植入半導體基板21中，以形成源極28與汲極29(未示出)。
第3I圖顯示第3H圖之上視示意圖，如圖所示，LDD區25，例如但不限於具有P型導電型，於橫向上(如圖中虛線箭號所示意)，LDD區25介於閘極27與汲極29之間，且LDD區25不與汲極29鄰接。此外，值得注意的是，本發明與第一個實施例尚具有下述的差異：如第3H與3I圖所示，本實施例之LDD區25，在橫向上的兩側與場氧化區24鄰接。此外，LDD區25由剖視圖第3I圖視之，其深度自半導體基板21的上表面21a開始沿著垂直方向而向下計算，不深於場氧化區24。
以上第3A-3I圖雖係以N型元件為例來加以說明，但相同概念當然也可適用於P型元件，只要相應改變摻雜區即可。
請參考第4A-4I圖，其顯示本發明的第三個實施例。類似地，本實施例亦係以N型高壓元件為例說明。
本實施例的製程步驟或結構大致上與第二個實施例的製程步驟或結構相似，本實施例高壓元件400與第二個實施例中的高壓元件300差異在於：相較於第二個實施例，本實施之絕緣結構23與場氧化區24係為STI結構，顯示根據本發明，絕緣結構23與場氧化區24也可以為STI結構。其他製程步驟與第二個 實施例相同，因此，本實施例與第二個實施例的製程步驟相似的部分就不再贅述。
請參考第5A與5B圖，其顯示本發明的第四個實施例。第5A與5B圖分別顯示高壓元件500的剖視示意圖與上視示意圖。本實施例顯示結構大致上與第一個實施例的結構相似，本實施例高壓元件500與第一個實施例中的高壓元件200差異在於：相較於第一個實施例，本實施之本體區26環繞井區22，顯示根據本發明，本體區26與井區22之安排可以有此變化。其他結構與第一個實施例相同，因此，本實施例與第一個實施例的相似的部分就不再贅述。
請參考第6A與6B圖，其顯示本發明的第五實施例。第6A與6B圖分別顯示高壓元件600的剖視示意圖與上視示意圖。本實施例顯示結構大致上與第一個實施例的結構相似，本實施例高壓元件600與第一個實施例中的高壓元件200差異在於：相較於第一個實施例，本實施之LDD區25之數量為複數，顯示根據本發明，LDD區25之數量安排可以有此變化。其他結構與第一個實施例相同，因此，本實施例與第一個實施例的相似的部分就不再贅述。
請參考第7圖，其顯示本發明的第六實施例。第7圖顯示高壓元件700的剖視示意圖。本實施例顯示結構大致上與第三個實施例的結構相似，本實施例高壓元件700與第三個實施例中的高壓元件400差異在於：相較於第三個實施例，本實施之高壓元件700更包含輕摻雜井區22a，其具有例如但不限於為N導電型，形成於上表面21a下之元件區23a中，輕摻雜井區22a於橫向上的兩側與井區22連接，且輕摻雜井區22a之N型雜質濃度低於井區22之N型雜質濃度。此外，根據本發明，輕摻雜井區22a之數量安排可以有此變化。形成輕摻雜井區22a的方法，可以在形成井區22時，以遮罩阻擋輕摻雜井區22a的範圍，以阻擋離子植入步驟中，加速離子植入輕摻雜井區22a的範圍，如此一來，輕摻雜井區22a的雜質摻雜濃度，低於井區22的雜質摻雜濃度，就可以達到輕摻雜井區22a的功 能，即幫助形成空乏區，又可以降低製造成本。除此之外，其他結構與第三個實施例相同，因此，本實施例與第三個實施例的相似的部分就不再贅述。
請參考第8圖，其示出本發明相較於先前技術能夠提高不導通操作時之崩潰防護電壓的示意圖。根據第8圖所示，本發明之高壓元件，相較於先前技術，具有較高的崩潰防護電壓。
此外，請參考第9A與9B圖，其分別示出先前技術與本發明的撞擊游離分析分佈圖的示意圖。根據第9A與9B圖所示，本發明之高壓元件在不導通操作的情況下，操作區中的PN接面PN2；相較於先前技術之高壓元件在不導通操作的情況下，操作區中的PN接面PN1，其位置在垂直方向上較高，也就是距離上表面較近，容易產生空乏區，以減緩不導通操作時的電場，進而提高高壓元件可承受的電壓，即提高崩潰防護電壓。
需說明的是，前述所有根據本發明之實施例中，一種較佳的實施方式，是安排LDD區25完全不位於閘極27正下方。也就是說，從上視圖視之，LDD區25完全與閘極27的任何部分重疊。此外，根據本發明，於高壓元件操作時(包含導通與不導通操作)，一種較佳的實施方式，是將LDD區25浮接(floating)。
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如深井區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術。凡此種種，皆可根據本發明的教示類推而得。此外，所說明之各個實施例，並不限於單獨應用，亦可以組合應用，例如但不限於將兩實施例併用。舉例而言，第7圖顯示之輕摻雜井區22a，可以應用於所有的實施例中。因此，本發明的範圍應涵蓋上述及其他所 有等效變化。此外，本發明的任一實施型態不必須達成所有的目的或優點，因此，請求專利範圍任一項也不應以此為限。
200‧‧‧高壓元件
21‧‧‧半導體基板
21a‧‧‧上表面
21b‧‧‧下表面
22‧‧‧井區
23‧‧‧絕緣結構
23a‧‧‧操作區
25‧‧‧LDD區
26‧‧‧本體區
27‧‧‧閘極
28‧‧‧源極
29‧‧‧汲極

Claims (10)

  1. 一種高壓元件，包含：一半導體基板，於一垂直方向上，具有相對之一上表面與一下表面；一絕緣結構，形成於該上表面上，用以定義一元件區；一閘極，形成於該半導體基板的該上表面上之該元件區中；一本體區，具有一第一導電型，形成於該上表面下之該元件區中，且部分該本體區位於該閘極正下方；一井區，具有一第二導電型，形成於該上表面下之該元件區中，該井區於一橫向上與該本體區鄰接，而形成一接面，且該接面位於該閘極正下方；一源極與一汲極，具有該第二導電型，形成於該上表面下之該元件區中，分別位於該閘極下方之外部靠近該本體區側與遠離該本體區側，且該汲極與該閘極間，由該井區分開；一輕摻雜擴散(lightly doped diffusion,LDD)區，具有該第一導電型，形成於該上表面下之該元件區中之該井區上，於該橫向上，該LDD區介於該閘極與該汲極之間，且該LDD區不與該汲極鄰接；以及一場氧化區，形成於該上表面上之該元件區中，且部分該場氧化區位於該閘極正下方，且其他部分之場氧化區位於該閘極與該汲極之間；其中該LDD區在橫向上的兩側與該場氧化區鄰接。
  2. 如申請專利範圍第1項所述之高壓元件，其中該LDD區由剖視圖視之，其深度自該半導體基板的該上表面開始沿著該垂直方向而向下計算，不深於該場氧化區。
  3. 一種高壓元件，包含：一半導體基板，於一垂直方向上，具有相對之一上表面與一下表面；一絕緣結構，形成於該上表面上，用以定義一元件區； 一閘極，形成於該半導體基板的該上表面上之該元件區中；一本體區，具有一第一導電型，形成於該上表面下之該元件區中，且部分該本體區位於該閘極正下方；一井區，具有一第二導電型，形成於該上表面下之該元件區中，該井區於一橫向上與該本體區鄰接，而形成一接面，且該接面位於該閘極正下方；一源極與一汲極，具有該第二導電型，形成於該上表面下之該元件區中，分別位於該閘極下方之外部靠近該本體區側與遠離該本體區側，且該汲極與該閘極間，由該井區分開；一輕雜擴散(lightly doped diffusion,LDD)區，具有該第一導電型，形成於該上表面下之該元件區中之該井區上，於該橫向上，該LDD區介於該閘極與該汲極之間，且該LDD區不與該汲極鄰接；以及一輕摻雜井區，具有該第二導電型，形成於該上表面下之該元件區中，該輕摻雜井區於該橫向上的兩側與該井區連接，且該輕摻雜井區之第二導電型雜質濃度低於該井區之第二導電型雜質濃度。
  4. 如申請專利範圍第1或3項所述之高壓元件，其中該LDD區完全不位於該閘極正下方。
  5. 一種高壓元件，包含：一半導體基板，於一垂直方向上，具有相對之一上表面與一下表面；一絕緣結構，形成於該上表面上，用以定義一元件區；一閘極，形成於該半導體基板的該上表面上之該元件區中；一本體區，具有一第一導電型，形成於該上表面下之該元件區中，且部分該本體區位於該閘極正下方；一井區，具有一第二導電型，形成於該上表面下之該元件區中，該井區於一橫向上與該本體區鄰接，而形成一接面，且該接面位於該閘極正下方； 一源極與一汲極，具有該第二導電型，形成於該上表面下之該元件區中，分別位於該閘極下方之外部靠近該本體區側與遠離該本體區側，且該汲極與該閘極間，由該井區分開；以及一輕雜擴散(lightly doped diffusion,LDD)區，具有該第一導電型，形成於該上表面下之該元件區中之該井區上，於該橫向上，該LDD區介於該閘極與該汲極之間，且該LDD區不與該汲極鄰接；其中該LDD區於導通及不導通操作時浮接。
  6. 一種高壓元件製造方法，包含：提供一半導體基板，於一垂直方向上，其具有相對之一上表面與一下表面；形成一絕緣結構於該上表面上，用以定義一元件區；形成一閘極於該半導體基板的該上表面上之該元件區中；形成一本體區於該上表面下之該元件區中，該本體區具有一第一導電型，且部分該本體區位於該閘極正下方；形成一井區於該上表面下之該元件區中，該井區具有一第二導電型，且該井區於一橫向上與該本體區鄰接，而形成一接面，且該接面位於該閘極正下方；形成一源極與一汲極於該上表面下之該元件區中，該源極與該汲極具有該第二導電型，分別位於該閘極下方之外部靠近該本體區側與遠離該本體區側，且該汲極與該閘極間，由該井區分開；形成輕雜擴散(lightly doped diffusion,LDD)區於該上表面下之該元件區中之該井區上，該LDD區具有該第一導電型，於該橫向上，該LDD區介於該閘極與該汲極之間，且該LDD區不與該汲極鄰接；以及 形成一場氧化區於該上表面上之該元件區中，且部分該場氧化區位於該閘極正下方，且其他部分之場氧化區位於該閘極與該汲極之間；其中該LDD區在橫向上的兩側與該場氧化區連接。
  7. 如申請專利範圍第6項所述之高壓元件製造方法，其中該LDD區由剖視圖視之，其深度自該半導體基板的該上表面開始沿著該垂直方向而向下計算，不深於該場氧化區。
  8. 一種高壓元件製造方法，包含：提供一半導體基板，於一垂直方向上，其具有相對之一上表面與一下表面；形成一絕緣結構於該上表面上，用以定義一元件區；形成一閘極於該半導體基板的該上表面上之該元件區中；形成一本體區於該上表面下之該元件區中，該本體區具有一第一導電型，且部分該本體區位於該閘極正下方；形成一井區於該上表面下之該元件區中，該井區具有一第二導電型，且該井區於一橫向上與該本體區鄰接，而形成一接面，且該接面位於該閘極正下方；形成一源極與一汲極於該上表面下之該元件區中，該源極與該汲極具有該第二導電型，分別位於該閘極下方之外部靠近該本體區側與遠離該本體區側，且該汲極與該閘極間，由該井區分開；形成輕雜散(lightly doped diffusion,LDD)區於該上表面下之該元件區中之該井區上，該LDD區具有該第一導電型，於該橫向上，該LDD區介於該閘極與該汲極之間，且該LDD區不與該汲極鄰接；以及 形成一輕摻雜井區，具有該第二導電型，形成於該上表面下之該元件區中，該輕摻雜井區於該橫向上的兩側與該井區連接，且該輕摻雜井區之第二導電型雜質濃度低於該井區之第二導電型雜質濃度。
  9. 如申請專利範圍第6或8項所述之高壓元件製造方法，其中該LDD區完全不位於該閘極正下方。
  10. 一種高壓元件製造方法，包含：提供一半導體基板，於一垂直方向上，其具有相對之一上表面與一下表面；形成一絕緣結構於該上表面上，用以定義一元件區；形成一閘極於該半導體基板的該上表面上之該元件區中；形成一本體區於該上表面下之該元件區中，該本體區具有一第一導電型，且部分該本體區位於該閘極正下方；形成一井區於該上表面下之該元件區中，該井區具有一第二導電型，且該井區於一橫向上與該本體區鄰接，而形成一接面，且該接面位於該閘極正下方；形成一源極與一汲極於該上表面下之該元件區中，該源極與該汲極具有該第二導電型，分別位於該閘極下方之外部靠近該本體區側與遠離該本體區側，且該汲極與該閘極間，由該井區分開；以及形成輕雜散lightly doped diffusion,LDD)區於該上表面下之該元件區中之該井區上，該LDD區具有該第一導電型，於該橫向上，該LDD區介於該閘極與該汲極之間，且該LDD區不與該汲極鄰接；其中該LDD區於導通及不導通操作時浮接。
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TW201340215A (zh) * 2012-03-22 2013-10-01 Richtek Technology Corp 高壓元件及其製造方法

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TWI644441B (zh) * 2018-05-04 2018-12-11 立錡科技股份有限公司 高壓元件及其製造方法
TWI730300B (zh) * 2018-05-25 2021-06-11 大陸商矽力杰半導體技術（杭州）有限公司 橫向擴散金屬氧化物半導體裝置的製造方法及半導體裝置
TWI659539B (zh) * 2018-06-28 2019-05-11 立錡科技股份有限公司 高壓元件及其製造方法
TWI677094B (zh) * 2018-08-06 2019-11-11 立錡科技股份有限公司 高壓元件及其製造方法

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