CN103811547B - 降低ldmos器件峰值电场的版图结构及方法 - Google Patents

降低ldmos器件峰值电场的版图结构及方法 Download PDF

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CN103811547B
CN103811547B CN201210460902.4A CN201210460902A CN103811547B CN 103811547 B CN103811547 B CN 103811547B CN 201210460902 A CN201210460902 A CN 201210460902A CN 103811547 B CN103811547 B CN 103811547B
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宁开明
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Abstract

本发明公开了一种降低LDMOS器件峰值电场的版图结构及方法，所述LDMOS器件包括第一导电类型的硅衬底，在硅衬底上形成具有与第一导电类型相反的第二导电类型的深阱；深阱中形成有场氧化层，场氧化层下方形成第一导电类型的埋层，埋层位于深阱的顶部或内部；LDMOS器件的源区由第二导电类型的第一掺杂区组成，该第一掺杂区形成于第一导电类型的阱区内，漏端由第二导电类型的第二掺杂区组成，该第二掺杂区形成于深阱中，所述埋层至少在靠近源区的一侧与深阱交替分布。本发明的埋层与深阱交错形成若干PN结，该PN结产生一个自建电场，该自建电场消弱了漏端电压产生的电场，降低了靠近源端的鸟嘴处的电场强度，提高了器件的耐压水平。

Description

降低LDMOS器件峰值电场的版图结构及方法
技术领域
本发明涉及半导体器件结构，具体属于一种降低LDMOS器件峰值电场的版图结构及方法。
背景技术
随着节能减排的意识逐渐深入人心，以及智能电网项目的开展，功率半导体(PowerIntegrated Circuit，简称PIC)特别是超高压功率半导体在用电和配电领域的市场前景将非常广阔，如LED市电照明、高效马达驱动、配电网的改造、电能的AC/DC转换等。在所有的功率半导体器件中，LDMOS（Lateral Double Diffused MOSFET，即横向双扩散金属氧化物半导体场效应管）高压器件具有工作电压高、工艺相对简单、开关频率高的特性，并且LDMOS器件的漏极、源极和栅极都位于其表面，易于同低压CMOS(Complementary MetalOxide Semiconductor，即互补型金属氧化物半导体)及BJT（Bipolar JunctionTransistor，即双极晶体管）等器件在工艺上相兼容，特别是在AC/DC,DC/DC转换等电路中可以进行器件集成，因而LDMOS器件受到广泛关注，被认为特别适合用作高压集成电路和功率集成电路中的高压功率器件。从1979年J.A.Appels提出著名的RESURF(Reduce SurfaceField，即降低表面电场技术)原理以来，LDMOS器件得到了迅速的发展。
现有技术中一种常规的LDMOS器件，如图1所示为该LDMOS器件的截面示意图，图2所示为该器件的横向断面示意图，它是一种Double RESURF LDMOS器件，以N型为例，包括P型硅衬底1，在硅衬底1上形成N型深阱2，该N型深阱2构成漂移区；N型深阱2中形成有场氧化层7，该场氧化层7下方形成有P型埋层3，该埋层3位于N型深阱2的顶部并与场氧化层7纵向接触。P型硅衬底1中形成有P型阱区4，P型阱区4与N型深阱2横向接触，P型阱区4由P+掺杂区6引出，源端由第一N+掺杂区5形成，第一N+第一掺杂区5和P+掺杂区6横向相连形成位于P型阱区4内的源区，N型深阱2中形成由N+第二掺杂区9组成的漏区。靠近漏区一侧的场氧化层7鸟嘴处和另一侧场氧化层7上形成有多晶场板8。其中，靠近源区一侧的多晶场板8一部分位于P型阱区4上，其下方为沟道区，另一部分位于场氧化层7上，调节下方的电场。N+第一掺杂区5和P+掺杂区6通过金属场板11引出源极，N+第二掺杂区9通过金属场板11与靠近漏区一侧的场氧化层7鸟嘴处的多晶场板8相连。
现有技术中，靠近源端的场氧化层7鸟嘴边界的电场比较集中，容易发生击穿，导致器件失效。并且，该处是场氧与栅氧的边界，电场较强，在源端加入电压时，会导致器件的热载流子效应(Hot carrier Effect,简称HCE)加大，不利于器件的可靠性。因此降低该处的电场，不但可以提高器件的击穿电压，而且还可以提高器件的可靠性。
发明内容
本发明要解决的技术问题是提供一种降低LDMOS器件峰值电场的版图结构及方法，可以降低LDMOS器件中靠近源端的场氧鸟嘴处的峰值电场，防止击穿，提高器件的耐压水平。
为解决上述技术问题，本发明提供一种降低LDMOS器件峰值电场的版图结构，所述LDMOS器件包括具有第一导电类型的硅衬底，在硅衬底上形成具有与第一导电类型相反的第二导电类型的深阱，所述深阱构成漂移区；深阱中形成有场氧化层，场氧化层下方形成具有第一导电类型的埋层，所述埋层位于深阱的顶部或内部；所述LDMOS器件的源区由具有第二导电类型的第一掺杂区组成，该第一掺杂区形成于具有第一导电类型的阱区内，所述阱区位于场氧化层的一侧，所述漏端由具有第二导电类型的第二掺杂区组成，该第二掺杂区形成于所述深阱中且位于场氧化层的另一侧，所述埋层至少在靠近源区的一侧与深阱交替间隔分布。
优选的，所述埋层为连续的条状结构，间隔分布在深阱顶部或内部，其一端靠近源区，另一端靠近漏端。
优选的，所述埋层为分段结构，间隔分布在深阱顶部或内部。
优选的，所述埋层靠近源区的一侧为多指结构，与深阱间隔分布。
进一步的，所述第一掺杂区所在的阱区位于硅衬底中，该阱区与深阱横向接触。或者，所述第一掺杂区所在的阱区位于深阱中。或者，所述第一掺杂区所在的阱区位于一具有第二导电类型的深阱区中，该深阱区位于硅衬底中，并与深阱横向接触。
在上述结构中，第一导电类型为P型，则第二导电类型为N型，相反的，第一导电类型为N型，第二导电类型则为P型。
本发明还提供了降低LDMOS器件峰值电场的方法，所述LDMOS器件包括具有第一导电类型的硅衬底，在硅衬底上形成具有与第一导电类型相反的第二导电类型的深阱，所述深阱构成漂移区；深阱中形成有场氧化层，场氧化层下方形成具有第一导电类型的埋层，所述埋层位于深阱的顶部或内部；所述LDMOS器件的源区由具有第二导电类型的第一掺杂区组成，该第一掺杂区形成于具有第一导电类型的阱区内，所述阱区位于场氧化层的一侧，所述漏端由具有第二导电类型的第二掺杂区组成，该第二掺杂区形成于所述深阱中且位于场氧化层的另一侧，所述埋层与深阱至少在靠近源区的一侧（即靠近源区的场氧化层鸟嘴处）形成自建电场，该自建电场与漏端电压所形成的电场相垂直。
本发明通过LDMOS器件的版图设计，使埋层与深阱交错形成若干对PN结，器件本身由于漏端电压产生一个电场，该PN结产生一个基本垂直于该电场的自建电场，该自建电场消弱了漏端电压产生的电场，从而降低了靠近源端的鸟嘴处的电场强度。本发明仅仅改善了LDMOS器件的版图，在没有增加额外的制造成本前提下，有效地提高了器件的耐压水平。
附图说明
图1是现有的NLDMOS器件的截面示意图；
图2是图1中NLDMOS器件的横向断面示意图；
图3是本发明第一实施例的截面示意图；
图4是图3所示器件的横向断面示意图及电场分布图；
图5是本发明第二实施例的横向断面示意图及电场分布图；
图6是本发明第三实施例的横向断面示意图及电场分布图；
图7是本发明第四实施例的横向断面示意图及电场分布图。
具体实施方式
下面结合附图与具体实施方式对本发明作进一步详细的说明。
本发明提供的降低LDMOS器件峰值电场的方法，所述LDMOS器件包括具有第一导电类型的硅衬底，在硅衬底上形成具有与第一导电类型相反的第二导电类型的深阱，所述深阱构成漂移区；深阱中形成有场氧化层，场氧化层下方形成具有第一导电类型的埋层，所述埋层位于深阱的顶部或内部；所述LDMOS器件的源区由具有第二导电类型的第一掺杂区组成，该第一掺杂区形成于具有第一导电类型的阱区内，所述阱区位于场氧化层的一侧，所述漏端由具有第二导电类型的第二掺杂区组成，该第二掺杂区形成于所述深阱中且位于场氧化层的另一侧，所述埋层与深阱至少在靠近源区的一侧（即靠近源区的场氧化层鸟嘴处）形成自建电场，该自建电场与漏端电压所形成的电场相垂直。
基于上述方法，降低LDMOS器件峰值电场的版图结构，以NLDMOS器件为例，第一实施例如图3、图4所示，包括P型硅衬底1，在硅衬底1上形成N型深阱2，所述深阱2构成漂移区；深阱2中形成有场氧化层7，场氧化层7下方形成P型埋层3，所述埋层3位于深阱2的顶部，在纵向上与场氧化层7接触。NLDMOS器件的源区由N型的第一掺杂区5组成，该第一掺杂区5形成于位于场氧化层7一侧的P型阱区4内，所述阱区4形成于硅衬底1中并与深阱2横向接触，所述漏端由N型的第二掺杂区9组成，该第二掺杂区9形成于所述深阱2中且位于场氧化层7的另一侧。靠近漏端一侧的场氧化层7鸟嘴处和另一侧场氧化层7上形成有多晶场板8，其中靠近源区一侧的多晶场板8一部分位于P型阱区4上，其下方为沟道区，另一部分位于场氧化层7上以调节下方的电场。定义从源区到漏端的方向为X方向，硅衬底顶面到底面的方向为Y方向，同时垂直于X方向和Y方向的则为Z方向，如图3、图4所示，在该实施例中，埋层3靠近源区的一侧（靠近鸟嘴处）沿Z方向为多指结构，该多指结构与深阱形成交错分布构成多对PN结，该PN结会在Z方向产生自建电场，这个自建电场垂直于漏端电压产生的电场，因此降低了漏端电压在靠近源区一侧的鸟嘴处的电场。
第二实施例如图5所示，该P型埋层3的版图与第一实施例相同，区别之处在于该实施例的NLDMOS为源端隔离型结构，其源区及阱区4位于深阱2中。第三实施例与第二实施例原理相同，也为源端隔离型结构，如图6所示，不同之处在于漏端位于N型深阱2中，而源区及阱区4则位于另一N型深阱中，两个深阱经过一系列的热过程最终连在一起。
第四实施例如图7所示，埋层3为多个连续的条状结构，其间隔地分布在深阱2中，该条状结构的埋层沿X方向的长度可以相同，也可以不同，各埋层在Z方向上的间距可以相等也可以不等。当然，该埋层也可以根据实际情况设置为分段式结构。
前述结构中，采用相反的导电类型就可以得到PLDMOS器件的版图结构。当然，上述实施例中的埋层3也可以位于深阱2的内部，只要其与深阱2部分交错分布形成自建电场即可。
本发明通过LDMOS器件的版图设计，在深阱中注入埋层，并使埋层与深阱交错形成一对对PN结，PN结在Z方向产生自建电场，而器件本身由于漏端电压沿着X方向产生一个电场，Z方向的自建电场与X方向的电场互相垂直，消弱了X方向的电场，从而降低了鸟嘴处的电场，有效地提高了器件的耐压水平。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员可对埋层的版图结构做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (5)

1.一种降低LDMOS器件峰值电场的方法，所述LDMOS器件包括具有第一导电类型的硅衬底，在硅衬底上形成具有与第一导电类型相反的第二导电类型的深阱，所述深阱构成漂移区；深阱中形成有场氧化层，场氧化层下方形成具有第一导电类型的埋层，所述埋层位于深阱的顶部或内部；所述LDMOS器件的源区由具有第二导电类型的第一掺杂区组成，该第一掺杂区形成于具有第一导电类型的阱区内，所述阱区位于场氧化层的一侧，LDMOS器件的漏端由具有第二导电类型的第二掺杂区组成，该第二掺杂区形成于所述深阱中且位于场氧化层的另一侧，其特征在于，所述埋层靠近源区的一侧为多指结构，与深阱间隔分布，所述埋层与深阱至少在靠近源区的一侧形成自建电场，该自建电场与漏端电压所形成的电场相垂直。
2.一种降低LDMOS器件峰值电场的版图结构，所述LDMOS器件包括具有第一导电类型的硅衬底，在硅衬底上形成具有与第一导电类型相反的第二导电类型的深阱，所述深阱构成漂移区；深阱中形成有场氧化层，场氧化层下方形成具有第一导电类型的埋层，所述埋层位于深阱的顶部或内部；所述LDMOS器件的源区由具有第二导电类型的第一掺杂区组成，该第一掺杂区形成于具有第一导电类型的阱区内，所述阱区位于场氧化层的一侧，LDMOS器件的漏端由具有第二导电类型的第二掺杂区组成，该第二掺杂区形成于所述深阱中且位于场氧化层的另一侧，其特征在于，所述埋层靠近源区的一侧为多指结构，与深阱间隔分布。
3.根据权利要求2所述的降低LDMOS器件峰值电场的版图结构，其特征在于，所述第一掺杂区所在的阱区位于硅衬底中，该阱区与深阱横向接触。
4.根据权利要求2所述的降低LDMOS器件峰值电场的版图结构，其特征在于，所述第一掺杂区所在的阱区位于深阱中。
5.根据权利要求2所述的降低LDMOS器件峰值电场的版图结构，其特征在于，所述第一掺杂区所在的阱区位于一具有第二导电类型的深阱区中，该深阱区位于硅衬底中，并与深阱横向接触。
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