CN108155240A - 一种SiC VDMOS器件 - Google Patents

一种SiC VDMOS器件 Download PDF

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CN108155240A
CN108155240A CN201711400450.XA CN201711400450A CN108155240A CN 108155240 A CN108155240 A CN 108155240A CN 201711400450 A CN201711400450 A CN 201711400450A CN 108155240 A CN108155240 A CN 108155240A
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vdmos devices
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罗小蓉
廖天
张凯
方健
杨霏
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Abstract

本发明属于功率半导体技术领域，涉及一种SiC VDMOS器件。本发明相较于传统结构，特点是栅极结构覆盖的P阱区是多次间断分布的，被N型高阻材料隔离开。传统平面MOSFET正向导通是通过P阱区表面形成反型层沟道，从而形成源极到漏极的电子通路；通过P阱区多次间断分布，使得正向导通时不仅P阱区表面形成反型层沟道，间断P阱区之间的N型高阻材料表面也会形成积累型沟道，使得源漏之间形成一条低电阻通路，降低了器件的导通电阻Ron。

Description

一种SiC VDMOS器件
技术领域
本发明属于功率半导体技术领域，涉及一种SiC VDMOS器件。
背景技术
SiC(碳化硅)材料由于具有禁带宽度大、临界击穿电场高和高热导率等特点，使得SiC器件在高温、高压、高频、大功率、强辐照等领域中独具优势，并且作为唯一一种能够热氧化生成SiO2的宽禁带半导体材料，使得SiC MOSFET器件制造成为可能。
当器件应用在大功率环境中时，如何降低器件的导通电阻，提高器件的电流能力成为学者关注的问题。SiC VDMOS的反型层迁移率小于积累层迁移率，因此，在制作平面栅SiC VDMOS器件时，为了降低器件的导通电阻，文献Praveen M.Shenoy，B.Jayant Baliga，【The Planar 6H-SiC ACCUFET:A New High-Voltage Power MOSFET Structure】提出了一种全积累型平面MOSFET(如说明书附图1所示)。该结构通过在栅极结构下方形成全积累型沟道，降低了导通电阻。但是为了保护MOSFET的栅氧化层电场，该结构需要在体内形成P+区域，增加了工艺难度。
发明内容
本发明为了解决上述问题，提出一种具有反型层沟道和积累型沟道的SiC VDMOS器件。
本发明的技术方案是：一种SiC VDMOS器件，在N型衬底1上形成N型高阻半导体材料2；在N型高阻半导体材料2表面形成P型阱区7，所述P型阱区7上表面的中心区域形成P型体接触区5，P型体接触区5的外侧形成N型源区6，N型源区6和P型体接触区5的共同引出端为源极；
其特征在于，沿器件纵向方向，所述P型阱区7是间断分布的，由N型高阻半导体材料2隔离开；所述器件纵向方向为同时与器件水平方向和垂直方向垂直的第三维方向；
在P型阱区7和N型高阻半导体材料2上表面形成栅极结构，所述栅极结构包括栅极绝缘材料3和位于栅极绝缘材料3上的导电材料4，所述导电材料4引出端为栅极；栅极之下，P型阱区7表面形成反型层沟道，N型高阻半导体材料2表面形成积累型沟道。
进一步的，所述SiC VDMOS器件具有方形元胞结构，所述P阱区7以P体接触区5和N源区6为中线，在中线两侧呈对称间断分布。
进一步的，所述SiC VDMOS器件具有条形元胞结构，所述P阱区7以P体接触区5和N源区6为中线，在中线两侧呈对称间断分布。
进一步的，所述SiC VDMOS器件具有条形元胞结构，所述P阱区7以P体接触区5和N源区6为中线，在中线两侧呈交错分布。
本发明的有效增益为，降低了器件的导通电阻，改善了BV和Ron的折衷关系。
附图说明
图1为ACCUFET结构示意图；
图2为实施例1三维结构示意图；
图3为实施例1俯视图；
图4为实施例2三维结构示意图；
图5为实施例2俯视图；
图6为实施例3三维结构示意图；
图7为实施例3俯视图；
具体实施方式
下面结合附图和实施例，详细描述本发明的技术方案：
实施例1
如图2、3所示，本例为条形元胞MOSFET，在N型衬底1上形成N型高阻半导体材料2；在N型高阻半导体材料2表面形成P型阱区7，所述P型阱区7上表面的中心区域形成P型体接触区5，P型体接触区5的外侧形成N型源区6，N型源区6和P型体接触区5的共同引出端为源极；
其特征在于，P型阱区7是间断分布的，由N型高阻半导体材料2隔离开；
在P型阱区7和N型高阻半导体材料2上表面形成栅极结构，所述栅极结构包括栅极绝缘材料3和位于栅极绝缘材料3上的导电材料4，所述导电材料4引出端为栅极。栅极之下，P型阱区7表面形成反型层沟道，N型高阻半导体材料2表面形成积累型沟道。
本例的工作原理为：
当栅极加正电压时，P阱区表面形成反型层沟道同时N型高阻材料表面形成积累型沟道，形成了源漏之间的低阻通道，降低了器件的导通电阻Ron。
实施例2
如图4、5所示，本例为条形元胞，与实施例1相比，P阱之间的距离更加优化，在器件耐压时能优化栅氧化层电场，提高器件的可靠性。
实施例3
如图6、7所示，与实施例1、实施例2的区别在于本例为方形元胞，相比于条形元胞，相同面积下方形元胞的沟道数量更多，进一步降低了导通电阻Ron。

Claims (4)

1.一种SiC VDMOS器件，在N型衬底(1)上形成N型高阻半导体材料(2)；在N型高阻半导体材料(2)表面形成P型阱区(7)，所述P型阱区(7)上表面的中心区域形成P型体接触区(5)，P型体接触区(5)的外侧形成N型源区(6)，N型源区(6)和P型体接触区(5)的共同引出端为源极；
其特征在于，沿器件纵向方向，所述P型阱区(7)是间断分布的，由N型高阻半导体材料(2)隔离开；所述器件纵向方向为同时与器件水平方向和垂直方向垂直的第三维方向；
在P型阱区(7)和N型高阻半导体材料(2)上表面形成栅极结构，所述栅极结构包括栅极绝缘材料(3)和位于栅极绝缘材料(3)上的导电材料(4)，所述导电材料(4)引出端为栅极；栅极之下，P型阱区(7)表面形成反型层沟道，N型高阻半导体材料(2)表面形成积累型沟道。
2.根据权利要求1所述的一种SiC VDMOS器件，其特征在于，所述SiC VDMOS器件具有方形元胞结构，所述P阱区(7)以P体接触区(5)和N源区(6)为中线，在中线两侧呈对称间断分布。
3.根据权利要求1所述的一种SiC VDMOS器件，其特征在于，所述SiC VDMOS器件具有条形元胞结构，所述P阱区(7)以P体接触区(5)和N源区(6)为中线，在中线两侧呈对称间断分布。
4.根据权利要求1所述的一种SiC VDMOS器件，其特征在于，所述SiC VDMOS器件具有条形元胞结构，所述P阱区(7)以P体接触区(5)和N源区(6)为中线，在中线两侧呈交错分布。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117038708A (zh) * 2023-09-28 2023-11-10 绍兴中芯集成电路制造股份有限公司 沟槽型场效应晶体管及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61164263A (ja) * 1985-01-17 1986-07-24 Toshiba Corp 導電変調型ｍｏｓｆｅｔ
JPH04217372A (ja) * 1990-12-18 1992-08-07 Nippondenso Co Ltd 絶縁ゲート形トランジスタ及びその製造方法
CN103811547A (zh) * 2012-11-15 2014-05-21 上海华虹宏力半导体制造有限公司 降低ldmos器件峰值电场的版图结构及方法
US20150008448A1 (en) * 2013-07-02 2015-01-08 General Electric Company Metal-oxide-semiconductor (mos) devices with increased channel periphery and methods of manufacture
US20160181365A1 (en) * 2014-12-19 2016-06-23 General Electric Company Semiconductor devices having channel regions with non-uniform edge

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61164263A (ja) * 1985-01-17 1986-07-24 Toshiba Corp 導電変調型ｍｏｓｆｅｔ
JPH04217372A (ja) * 1990-12-18 1992-08-07 Nippondenso Co Ltd 絶縁ゲート形トランジスタ及びその製造方法
CN103811547A (zh) * 2012-11-15 2014-05-21 上海华虹宏力半导体制造有限公司 降低ldmos器件峰值电场的版图结构及方法
US20150008448A1 (en) * 2013-07-02 2015-01-08 General Electric Company Metal-oxide-semiconductor (mos) devices with increased channel periphery and methods of manufacture
US20160181365A1 (en) * 2014-12-19 2016-06-23 General Electric Company Semiconductor devices having channel regions with non-uniform edge

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117038708A (zh) * 2023-09-28 2023-11-10 绍兴中芯集成电路制造股份有限公司 沟槽型场效应晶体管及其制备方法
CN117038708B (zh) * 2023-09-28 2024-01-23 绍兴中芯集成电路制造股份有限公司 沟槽型场效应晶体管及其制备方法

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