WO2022111160A1 - 碳化硅器件的元胞结构、其制备方法及碳化硅器件 - Google Patents

碳化硅器件的元胞结构、其制备方法及碳化硅器件 Download PDF

Info

Publication number
WO2022111160A1
WO2022111160A1 PCT/CN2021/125473 CN2021125473W WO2022111160A1 WO 2022111160 A1 WO2022111160 A1 WO 2022111160A1 CN 2021125473 W CN2021125473 W CN 2021125473W WO 2022111160 A1 WO2022111160 A1 WO 2022111160A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
source region
gate
source
gate trench
Prior art date
Application number
PCT/CN2021/125473
Other languages
English (en)
French (fr)
Inventor
王亚飞
罗海辉
李诚瞻
陈喜明
罗烨辉
周才能
张文杰
Original Assignee
株洲中车时代半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株洲中车时代半导体有限公司 filed Critical 株洲中车时代半导体有限公司
Priority to EP21896662.0A priority Critical patent/EP4254503A1/en
Publication of WO2022111160A1 publication Critical patent/WO2022111160A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide

Definitions

  • the present disclosure relates to the technical field of semiconductor devices, in particular to a cell structure of a silicon carbide device, a preparation method thereof, and a silicon carbide device.
  • SiC silicon carbide
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • MOSFETs silicon carbide power devices
  • MOSFETs planar gate silicon carbide power devices
  • trench gate silicon carbide power devices can take advantage of the anisotropy of silicon carbide materials, use close to To obtain relatively high channel carrier mobility
  • the cell structure 100 of a conventional trench gate silicon carbide power device is shown in FIG. 1 , including a substrate 101 , a drift layer 102 , and a well region 103 , a first source region 104 , a second source region 105 , a gate dielectric layer 106 , a gate electrode 107 , an interlayer dielectric layer 108 , a source metal layer 109 and a drain metal layer 110 .
  • the electric field strength inside the dielectric layer is 2.5 times the peak value of the electric field inside the silicon carbide, and the silicon carbide
  • the material itself has a high critical breakdown electric field, which will lead to excessive electric field stress of the gate dielectric layer, thereby affecting the long-term reliability of the device, and even causing the device to fail.
  • the present disclosure provides a cell structure of a silicon carbide device, a preparation method thereof, and a silicon carbide device, which solve the problem that the gate dielectric layer of the silicon carbide device in the prior art is damaged due to electric field stress in the blocking state.
  • the present disclosure provides a cell structure of a silicon carbide device, including:
  • a gate trench located between two adjacent well regions; wherein the sidewall of the gate trench is in contact with the well region and the source region at the same time, and the depth of the gate trench is greater than the depth of the well region;
  • a second conductive type shielding region located in the drift layer and vertically spaced below the gate trench; wherein the top of the shielding region is connected to the bottom of the gate trench and the bottom of the well region touch.
  • the source region includes a first source region of a first conductivity type, and a second source region of a second conductivity type disposed in the first source region with a longitudinal interval;
  • both ends of the first source region are respectively in contact with the sidewalls of the gate trench on both sides, and the second source region is not in contact with the sidewalls of the gate trench.
  • the shielding regions under two adjacent gate trenches are arranged staggered.
  • it further includes:
  • the storage regions and the shielding regions are alternately arranged at intervals in the longitudinal direction, and the top of the storage region is in contact with the bottom of the gate trench and the bottom of the well region.
  • the shielding regions under two adjacent gate trenches are aligned and arranged.
  • the source region includes first source regions of the first conductivity type and second source regions of the second conductivity type alternately arranged in the longitudinal direction;
  • the second source region and the shielding region are laterally aligned, and both ends of the first source region and the second source region are respectively in contact with the sidewalls of the gate trenches on both sides.
  • the depth of the gate trench is 0.4 to 2.0 ⁇ m
  • the gate trench has a width of 0.15 to 3.0 ⁇ m.
  • the ion doping concentration of the shielding region is greater than 1E15cm ⁇ 3 ;
  • the depth of the shielding region is 0.2 to 5 ⁇ m.
  • it further includes:
  • a gate dielectric layer disposed on the sidewall and bottom of the gate trench and a gate filled in the gate trench;
  • a source metal layer located above the source region and electrically connected to the source region; wherein the gate is isolated from the source metal layer by an interlayer dielectric layer, and the shielding region passes through the well region and the source region is electrically connected to the source metal layer;
  • a drain metal layer under the substrate and in ohmic contact with the substrate is provided.
  • the present disclosure provides a method for preparing a cell structure of a silicon carbide device, including:
  • a gate trench is formed between two adjacent well regions; wherein the sidewall of the gate trench is in contact with the well region and the source region at the same time, and the depth of the gate trench is greater than the depth of the well region;
  • a second conductive type shielding region is formed in the drift layer under the gate trench by means of oblique ion implantation; wherein the top of the shielding region and the bottom of the gate trench are the same as the bottom of the gate trench.
  • the bottom of the well region contacts.
  • the source region includes a first source region of a first conductivity type, and a second source region of a second conductivity type vertically spaced in the first source region;
  • the step of forming the source region in the surface of the well region includes the following steps:
  • a first source region of a first conductivity type is formed in the surface of the well region; wherein, two ends of the first source region are respectively in contact with the sidewalls of the gate trenches on both sides;
  • first source region longitudinally spaced second source regions of a second conductivity type are formed; wherein the second source regions do not contact the sidewalls of the gate trenches.
  • the shielding regions under two adjacent gate trenches are arranged staggered.
  • the method preferably, after the step of forming the second conductive type shielding regions spaced vertically in the drift layer under the gate trenches by means of oblique ion implantation, the method also includes:
  • the storage regions and the shielding regions are alternately arranged at intervals in the longitudinal direction, and the top of the storage region is in contact with the bottom of the gate trench and the bottom of the well region.
  • the shielding regions under two adjacent gate trenches are arranged in alignment.
  • the source region includes a first source region of a first conductivity type and a second source region of a second conductivity type alternately arranged in a longitudinal direction; the source region is formed in the surface of the well region steps, including the following steps:
  • first source regions of the first conductivity type and second source regions of the second conductivity type are alternately arranged in the longitudinal direction;
  • the second source region and the shielding region are laterally aligned, and two ends of the first source region and the second source region are respectively in contact with the sidewalls of the gate trenches on both sides.
  • the method preferably, after the step of forming the second conductive type shielding regions spaced vertically in the drift layer under the gate trenches by means of oblique ion implantation, the method also includes:
  • a source metal layer electrically connected to the source region is formed over the source region; wherein the gate is isolated from the source metal layer by the interlayer dielectric layer, and the shield region is separated from the well by the well region and the source region are electrically connected to the source metal layer;
  • a drain metal layer in ohmic contact with the substrate is formed under the substrate.
  • the present disclosure provides a silicon carbide device including several cell structures of the silicon carbide device according to any one of the first aspects.
  • the shielding region is in contact with the bottom of the well region, and can be electrically connected to the source metal layer through the well region and the source region (second source region of the second conductivity type), thereby increasing the switching frequency of the device and reducing switching loss;
  • the shielding region arranged at a longitudinal interval at the bottom of the gate trench can separate the conductive region (the part of the trench without the shielding region at the bottom) and the electric field protection region (the part of the trench where the shielding region is provided at the bottom),
  • the formation process of the shielding region will not affect the ion doping concentration of the conductive region (trench surface), and will not affect the electrical characteristics such as the threshold voltage of the device, which is beneficial to the current sharing between cells;
  • FIG. 1 is a cross-sectional structural schematic diagram of a cell structure of a conventional silicon carbide device
  • FIG. 2 is a schematic top plan view of a cell structure of a silicon carbide device according to an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional structural diagram of a cell structure of a silicon carbide device according to an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic top plan view of a cell structure of another silicon carbide device according to an exemplary embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional structural diagram of a cell structure of another silicon carbide device according to an exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic top plan view of a cell structure of another silicon carbide device according to an exemplary embodiment of the present disclosure
  • FIG. 7 is a schematic cross-sectional structural diagram of a cell structure of another silicon carbide device according to an exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic top plan view of a cell structure of another silicon carbide device according to an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic cross-sectional structural diagram of a cell structure of another silicon carbide device according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic flowchart of a method for preparing a cell structure of a silicon carbide device according to an exemplary embodiment of the present disclosure
  • 11-15 are schematic cross-sectional structural diagrams formed by relevant steps of a method for fabricating a cell structure of a silicon carbide device according to an exemplary embodiment of the present disclosure
  • FIG. 16 is a schematic flowchart of another method for preparing a cell structure of a silicon carbide device according to an exemplary embodiment of the present disclosure
  • FIG. 17 is a schematic flowchart of another method for preparing a cell structure of a silicon carbide device according to an exemplary embodiment of the present disclosure
  • first,” “second,” “third,” etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections may not be should be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
  • spatially relative terms such as “above”, “above”, “below”, “below”, etc., may be used herein for convenience of description to describe The relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship term is intended to also include different orientations of the device in use and operation. For example, if the accompanying drawings The device in is turned over, then elements or features described as “below” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “under” and “under” “ may include both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, fabrication techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to fabrication. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
  • an embodiment of the present disclosure provides a cell structure 200 of a silicon carbide device, including a substrate 201 , a drift layer 202 , a well region 203 , a source region (not marked in the figure), and a shield region 206 , a gate trench (not marked in the figure), a gate dielectric layer 207 , a gate electrode 208 , an interlayer dielectric layer 209 , a source metal layer 210 and a drain metal layer 211 .
  • the substrate 201 , the drift layer 202 , the well region 203 , the interlayer dielectric layer 209 , the source metal layer 210 and the drain metal layer 211 are not shown in FIG. 2 .
  • the shapes and positions of the substrate 201, the drift layer 202, the well region 203, the interlayer dielectric layer 209, the source metal layer 210 and the drain metal layer 211 can be understood.
  • the substrate 201 is a silicon carbide substrate 201 of the first conductivity type.
  • the thickness of the substrate 201 is relatively thick, the ion doping concentration is relatively high, and the ion doping concentration is greater than 1E18 cm ⁇ 3 .
  • the drift layer 202 is a drift layer 202 of the first conductivity type, located above the substrate 201 , with an ion doping concentration of about 1E14 to 5E16 cm ⁇ 3 .
  • the ion doping concentration and thickness of the drift layer 202 need to be optimized according to the chip withstand voltage.
  • the well region 203 is a well region 203 of the second conductivity type, a plurality of well regions 203 are disposed in the surface of the drift layer 202 at intervals, and the upper surface of the well region 203 is flush with the upper surface of the drift layer 202 .
  • the ion doping concentration of the well region 203 is 1E16 to 1E18 cm ⁇ 3 , and the depth is 0.3 to 1.5 ⁇ m.
  • the source region is located in the surface of the well region 203 .
  • the source region includes a first source region 204 and a second source region 205 .
  • the first source region 204 is a source region of the first conductivity type, the first source region 204 is located in the surface of the well region 203 , the upper surface of the first source region 204 is flush with the upper surface of the well region 203 , and the first source region 204 Both ends of the gate electrode are in contact with the sidewalls of the gate trenches on both sides.
  • the width of the first source region 204 is equal to the width of the well region 203 , the depth of the first source region 204 is smaller than the depth of the well region 203 , the ion doping concentration of the first source region 204 is greater than 1E19 cm ⁇ 3 , and the depth is 0.2 to 0.5 ⁇ m.
  • the second source region 205 is a source region of the second conductivity type, the second source region 205 is disposed in the first source region 204 at intervals in the longitudinal direction (Y direction), and the upper surface of the second source region 205 is opposite to the upper surface of the well region 203 Flush, the second source region 205 is not in contact with the sidewall of the gate trench.
  • the width of the second source region 205 is smaller than the width of the first source region 204 , the depth of the second source region 205 is greater than the depth of the first source region 204 , but smaller than the depth of the well region 203 , the ion doping concentration of the second source region 205 .
  • the ion doping concentration of the well region 203 is greater than that of the well region 203 , the ion doping concentration of the second source region 205 is greater than 5E18 cm ⁇ 3 , and the depth is 0.3 to 1.5 ⁇ m.
  • the gate trench (not marked in the figure) is located between two adjacent well regions 203, and the sidewalls of the gate trench are in contact with the well region 203 and the first source region 204 in the source region at the same time.
  • the depth of the gate trench is greater than the depth of the well region 203 , the depth of the gate trench is 0.4 to 2.0 ⁇ m, and the width of the gate trench is 0.15 to 3.0 ⁇ m.
  • the gate dielectric layer 207 is uniformly disposed on the sidewall and bottom of the gate trench.
  • the gate dielectric layer 207 can be an oxide layer with a thickness of about 30nm to 1000nm, wherein the thickness of the dielectric layer at the bottom of the trench can be higher than that of the sidewall dielectric layer. thickness to improve the withstand voltage capability of the bottom of the gate dielectric layer 207 .
  • the gate 208 is a polysilicon gate of the first conductivity type, disposed in the gate trench, and its ion doping concentration is greater than 1E18cm ⁇ 3 .
  • the shielding region 206 is a doped region of the second conductivity type.
  • the shielding region 206 is located in the drift layer 202 and is spaced below the gate trench in the longitudinal direction (Y direction), and the top of the shielding region 206 is the bottom of the gate trench and the well.
  • the bottom of the region 203 is in contact, the ion doping concentration of the shielding region 206 is greater than 1E15 cm ⁇ 3 , and the junction depth (depth) of the shielding region 206 is 0.2 to 5 ⁇ m.
  • the shielding regions 206 under two adjacent gate trenches are aligned.
  • the shielding region 206 can greatly reduce the electric field stress of the gate dielectric layer 207 of the device in the blocking state, and greatly improve the long-term reliability of the device.
  • the top of the shielding region 206 is in contact with the bottom of the gate trench and the bottom of the well region 203, and the first source region 204 and the second source region 205 in the surface of the well region 203 are electrically connected to the source metal layer 210, so, The shielding region 206 is electrically connected (short-circuited) to the source metal layer 210 through the well region 203 and the second source region 205, which can increase the switching frequency of the device and reduce switching loss.
  • the trench gate (including the gate trench, the gate dielectric layer 207 and the gate 208 ) is in the shielded region.
  • the two sides of the trench gate will be A channel is formed to form a channel current (on-current), that is, the electric field protection region and the conductive region can be separated and set to achieve the effect of not only ensuring the on-current but also effectively reducing the electric field stress of the gate dielectric layer 207 in the blocking state.
  • the formation process of the shielding region 206 will not affect the ion doping concentration of the conductive region (trench surface), and will not affect the electrical characteristics such as the threshold voltage of the device, which is beneficial to the current sharing between cells.
  • the interlayer dielectric layer 209 is located above the gate electrode 208 , and the interlayer dielectric layer 209 isolates the gate electrode 208 from the source metal layer 210 .
  • the source metal layer 210 is located above the source region (including the first source region 204 and the second source region 205 ) and is electrically connected to the first source region 204 and the second source region 205 at the same time.
  • the source metal layer 210 may be a metal having low contact resistivity with SiC, such as aluminum, nickel, or the like.
  • the drain metal layer 211 is located under the substrate 201 and forms an ohmic contact with the substrate 201.
  • the drain metal can be a metal such as aluminum, nickel, etc., which has a low contact resistivity with SiC.
  • the silicon carbide device in this embodiment is a trench gate silicon carbide MOSFET device.
  • the first conductivity type and the second conductivity type are opposite.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • This embodiment provides a cell structure 200 of a silicon carbide device.
  • the gate dielectric layer 207 of the device in the blocking state can be greatly reduced
  • the electric field stress can greatly improve the long-term reliability of the device; the shielding region 206 is in contact with the bottom of the well region 203, and can be electrically connected to the source metal layer 210 through the well region 203 and the source region, thereby increasing the switching frequency of the device and reducing switching losses.
  • the shielding region 206 arranged at a vertical interval can separate the conductive region and the electric field protection region, and the formation process of the shielding region 206 will not affect the ion doping concentration of the conductive region, and will not produce electrical characteristics such as the threshold voltage of the device. influence, which is beneficial to the flow sharing between cells.
  • an embodiment of the present disclosure provides a cell structure 300 of a silicon carbide device, including a substrate 301 , a drift layer 302 , a well region 303 , a source region (not marked in the figure), and a shield region 306 , a gate trench (not marked in the figure), a gate dielectric layer 307 , a gate electrode 308 , an interlayer dielectric layer 309 , a source metal layer 310 and a drain metal layer 311 .
  • the substrate 301 , the drift layer 302 , the well region 303 , the interlayer dielectric layer 309 , the source metal layer 310 and the drain metal layer 311 are not shown in FIG. 4 .
  • the shapes and positions of the substrate 301 , the drift layer 302 , the well region 303 , the interlayer dielectric layer 309 , the source metal layer 310 and the drain metal layer 311 can be understood.
  • the substrate 301 is a silicon carbide substrate 301 of the first conductivity type.
  • the thickness of the substrate 301 is relatively thick, the ion doping concentration is relatively high, and the ion doping concentration is greater than 1E18 cm ⁇ 3 .
  • the drift layer 302 is a first conductivity type drift layer 302 located above the substrate 301 with an ion doping concentration of about 1E14 to 5E16 cm ⁇ 3 .
  • the ion doping concentration and thickness of the drift layer 302 need to be optimized according to the chip withstand voltage.
  • the well region 303 is a well region 303 of the second conductivity type, a plurality of well regions 303 are arranged in the surface of the drift layer 302 at intervals, and the upper surface of the well region 303 is flush with the upper surface of the drift layer 302 .
  • the ion doping concentration of the well region 303 is 1E16 to 1E18 cm ⁇ 3 , and the depth is 0.3 to 1.5 ⁇ m.
  • the source region is located within the surface of the well region 303 .
  • the source region includes a first source region 304 and a second source region 305 .
  • the first source region 304 is a source region of the first conductivity type, the first source region 304 is located in the surface of the well region 303 , the upper surface of the first source region 304 is flush with the upper surface of the well region 303 , and the first source region 304 Both ends of the gate electrode are in contact with the sidewalls of the gate trenches on both sides.
  • the width of the first source region 304 is equal to the width of the well region 303 , the depth of the first source region 304 is smaller than the depth of the well region 303 , the ion doping concentration of the first source region 304 is greater than 1E19 cm ⁇ 3 , and the depth is 0.2 to 0.5 ⁇ m.
  • the second source region 305 is a source region of the second conductivity type, the second source region 305 is disposed in the first source region 304 at intervals in the longitudinal direction (Y direction), and the upper surface of the second source region 305 is opposite to the upper surface of the well region 303 Flush, the second source region 305 is not in contact with the sidewall of the gate trench.
  • the width of the second source region 305 is smaller than the width of the first source region 304 , the depth of the second source region 305 is greater than the depth of the first source region 304 , but smaller than the depth of the well region 303 , the ion doping concentration of the second source region 305
  • the ion doping concentration of the well region 303 is greater than that of the well region 303
  • the ion doping concentration of the second source region 305 is greater than 5E18 cm ⁇ 3 and the depth is 0.3 to 1.5 ⁇ m.
  • the gate trench (not marked in the figure) is located between two adjacent well regions 303, and the sidewall of the gate trench is in contact with the well region 303 and the first source region 304 in the source region at the same time.
  • the depth of the gate trench is greater than the depth of the well region 303 , the depth of the gate trench is 0.4 to 2.0 ⁇ m, and the width of the gate trench is 0.15 to 3.0 ⁇ m.
  • the gate dielectric layer 307 is uniformly disposed on the sidewall and bottom of the gate trench.
  • the gate dielectric layer 307 can be an oxide layer with a thickness of about 30nm to 1000nm, wherein the thickness of the dielectric layer at the bottom of the trench can be higher than that of the sidewall dielectric layer. thickness to improve the withstand voltage capability of the bottom of the gate dielectric layer 307 .
  • the gate 308 is a polysilicon gate of the first conductivity type, disposed in the gate trench, and its ion doping concentration is greater than 1E18 cm ⁇ 3 .
  • the shielding region 306 is a doped region of the second conductivity type.
  • the shielding region 306 is located in the drift layer 302 and is spaced below the gate trench in the longitudinal direction (Y direction), and the top of the shielding region 306 is the bottom of the gate trench and the well.
  • the bottom of the region 303 is in contact, the ion doping concentration of the shielding region 306 is greater than 1E15 cm ⁇ 3 , and the junction depth (depth) of the shielding region 306 is 0.2 to 5 ⁇ m.
  • the shielding regions 306 under two adjacent gate trenches are staggered.
  • the shielding region 306 can greatly reduce the electric field stress of the gate dielectric layer 307 of the device in the blocking state, and greatly improve the long-term reliability of the device.
  • the top of the shielding region 306 is in contact with the bottom of the gate trench and the bottom of the well region 303, and the first source region 304 and the second source region 305 in the surface of the well region 303 are electrically connected to the source metal layer 310, so, The shielding region 306 is electrically connected (short-circuited) to the source metal layer 310 through the well region 303 and the second source region 305, which can increase the switching frequency of the device and reduce switching loss.
  • the trench gate (including the gate trench, the gate dielectric layer 307 and the gate 308) is in the shielded region.
  • a channel will not be formed on both sides of the trench gate, and no channel current (on current) will be generated, while in the part of the trench gate without the shielding region 306, the two sides of the trench gate will not be formed.
  • a channel is formed to form a channel current (on-current), that is, the electric field protection region and the conductive region can be separated and set, so as to ensure the on-current and effectively reduce the electric field stress of the gate dielectric layer 307 in the blocking state. A good compromise relationship.
  • the formation process of the shielding region 306 will not affect the ion doping concentration of the conductive region (trench surface), and will not affect the electrical characteristics such as the threshold voltage of the device, which is beneficial to the current sharing between cells.
  • the staggered shielding regions 306 in this embodiment make the electric field protection region and the conductive region alternately arranged in the entire silicon carbide device, and the shielding region 306 is used to shield the electric field to the surrounding area, which further reduces the At the same time, the electric field stress of the gate dielectric layer 307 increases the area of the conductive region and achieves a better trade-off relationship between the on-current and the blocking voltage.
  • the interlayer dielectric layer 309 is located above the gate electrode 308 , and the interlayer dielectric layer 309 separates the gate electrode 308 from the source metal layer 310 .
  • the source metal layer 310 is located above the source region (including the first source region 304 and the second source region 305 ) and is electrically connected to the first source region 304 and the second source region 305 at the same time.
  • the source metal layer 310 may be a metal having low contact resistivity with SiC, such as aluminum, nickel, or the like.
  • the drain metal layer 311 is located under the substrate 301 and forms an ohmic contact with the substrate 301.
  • the drain metal can be aluminum, nickel and other metals that have low contact resistivity with SiC.
  • the silicon carbide device in this embodiment is a trench gate silicon carbide MOSFET device.
  • the first conductivity type and the second conductivity type are opposite.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • This embodiment provides a cell structure 300 of a silicon carbide device.
  • the gate dielectric layer 307 of the device in the blocking state can be greatly reduced
  • the electric field stress can greatly improve the long-term reliability of the device; the shielding region 306 is in contact with the bottom of the well region 303, and can be electrically connected to the source metal layer 310 through the well region 303 and the source region, thereby increasing the switching frequency of the device and reducing switching losses.
  • the shielding region 306 arranged at vertical intervals can separate the conductive region and the electric field protection region. The formation process of the shielding region 306 will not affect the ion doping concentration of the conductive region, and will not produce electrical characteristics such as the threshold voltage of the device. influence, which is beneficial to the flow sharing between cells.
  • an embodiment of the present disclosure provides a cell structure 400 of a silicon carbide device, including a substrate 401 , a drift layer 402 , a well region 403 , a source region (not marked in the drawings), and a shield region 406 , a storage region 412 , a gate trench (not marked in the figure), a gate dielectric layer 407 , a gate electrode 408 , an interlayer dielectric layer 409 , a source metal layer 410 and a drain metal layer 411 .
  • the substrate 401 , the drift layer 402 , the well region 403 , the interlayer dielectric layer 409 , the source metal layer 410 and the drain metal layer 411 are not shown in FIG. 6 .
  • the shapes and positions of the substrate 401 , the drift layer 402 , the well region 403 , the interlayer dielectric layer 409 , the source metal layer 410 and the drain metal layer 411 can be understood.
  • the substrate 401 is a silicon carbide substrate 401 of the first conductivity type.
  • the thickness of the substrate 401 is relatively thick, the ion doping concentration is relatively high, and the ion doping concentration is greater than 1E18 cm ⁇ 3 .
  • the drift layer 402 is a first conductivity type drift layer 402 located above the substrate 401 with an ion doping concentration of about 1E14 to 5E16 cm ⁇ 3 .
  • the ion doping concentration and thickness of the drift layer 402 need to be optimized according to the chip withstand voltage.
  • the well region 403 is a well region 403 of the second conductivity type, a plurality of well regions 403 are disposed in the surface of the drift layer 402 at intervals, and the upper surface of the well region 403 is flush with the upper surface of the drift layer 402 .
  • the ion doping concentration of the well region 403 is 1E16 to 1E18 cm ⁇ 3 , and the depth is 0.3 to 1.5 ⁇ m.
  • the source region is located in the surface of the well region 403 .
  • the source region includes a first source region 404 and a second source region 405 .
  • the first source region 404 is a source region of the first conductivity type, the first source region 404 is located in the surface of the well region 403 , the upper surface of the first source region 404 is flush with the upper surface of the well region 403 , and the first source region 404 Both ends of the gate electrode are in contact with the sidewalls of the gate trenches on both sides.
  • the width of the first source region 404 is equal to the width of the well region 403 , the depth of the first source region 404 is smaller than that of the well region 403 , the ion doping concentration of the first source region 404 is greater than 1E19 cm ⁇ 3 , and the depth is 0.2 to 0.5 ⁇ m.
  • the second source region 405 is a source region of the second conductivity type, the second source region 405 is disposed in the first source region 404 at intervals in the longitudinal direction (Y direction), and the upper surface of the second source region 405 is opposite to the upper surface of the well region 403 Flush, the second source region 405 is not in contact with the sidewalls of the gate trenches.
  • the width of the second source region 405 is smaller than the width of the first source region 404 , the depth of the second source region 405 is greater than the depth of the first source region 404 , but smaller than the depth of the well region 403 , the ion doping concentration of the second source region 405
  • the ion doping concentration of the well region 403 is greater than that of the well region 403
  • the ion doping concentration of the second source region 405 is greater than 5E18 cm ⁇ 3
  • the depth is 0.3 to 1.5 ⁇ m.
  • a gate trench (not marked in the figure) is located between two adjacent well regions 403, and the sidewalls of the gate trench are in contact with the well region 403 and the first source region 404 in the source region at the same time.
  • the depth of the gate trench is greater than the depth of the well region 403 , the depth of the gate trench is 0.4 to 2.0 ⁇ m, and the width of the gate trench is 0.15 to 3.0 ⁇ m.
  • the gate dielectric layer 407 is uniformly disposed on the sidewall and bottom of the gate trench.
  • the gate dielectric layer 407 can be an oxide layer with a thickness of about 30nm to 1000nm, and the thickness of the dielectric layer at the bottom of the trench can be higher than that of the sidewall dielectric layer. thickness to improve the withstand voltage capability of the bottom of the gate dielectric layer 407 .
  • the gate 408 is a polysilicon gate of the first conductivity type, disposed in the gate trench, and its ion doping concentration is greater than 1E18 cm ⁇ 3 .
  • the shielding region 406 is a doped region of the second conductivity type.
  • the shielding region 406 is located in the drift layer 402 and is spaced below the gate trench in the longitudinal direction (Y direction), and the top of the shielding region 406 is the bottom of the gate trench and the well.
  • the bottom of the region 403 is in contact, the ion doping concentration of the shielding region 406 is greater than 1E15 cm ⁇ 3 , and the junction depth (depth) of the shielding region 406 is 0.2 to 5 ⁇ m.
  • the shielding regions 406 under two adjacent gate trenches are aligned or staggered (the staggered arrangement is not shown in the structural diagram).
  • the shielding region 406 can greatly reduce the electric field stress of the gate dielectric layer 407 of the device in the blocking state, and greatly improve the long-term reliability of the device.
  • the top of the shielding region 406 is in contact with the bottom of the gate trench and the bottom of the well region 403, and the first source region 404 and the second source region 405 in the surface of the well region 403 are electrically connected to the source metal layer 410, so, The shielding region 406 is electrically connected (short-circuited) to the source metal layer 410 through the well region 403 and the second source region 405, which can increase the switching frequency of the device and reduce switching loss.
  • the trench gate (including the gate trench, the gate dielectric layer 407 and the gate 408 ) is in the shielded region.
  • the two sides of the trench gate will be A channel is formed and a channel current (on current) is formed, that is, the electric field protection region and the conductive region can be separated and set to achieve the effect of not only ensuring the on current but also effectively reducing the electric field stress of the gate dielectric layer 407 in the blocking state.
  • the formation process of the shielding region 406 will not affect the ion doping concentration of the conductive region (trench surface), and will not affect the electrical characteristics such as the threshold voltage of the device, which is beneficial to the current sharing between cells.
  • the storage area 412 is a doping area of the first conductivity type, the storage area 412 is also located under the gate trench, the storage area 412 and the shielding area 406 are alternately arranged in the longitudinal direction (Y direction), and the storage area 412 is not connected to the shielding area 406.
  • the top of the storage region 412 is in contact with the bottom of the gate trench and the bottom of the well region 403 , and the ion doping concentration of the storage region 412 is greater than that of the substrate 201 .
  • the storage region 412 can enhance the conduction current capability of the conductive region, and based on the existence of the storage region 412, the area size of the conduction region can be further reduced, that is, the longitudinal distance between the shielding regions 406 can be further reduced, and the size of the conduction region can be further reduced. Affects the conduction current capability of the conduction region.
  • the interlayer dielectric layer 409 is located above the gate electrode 408 , and the interlayer dielectric layer 409 isolates the gate electrode 408 from the source metal layer 410 .
  • the source metal layer 410 is located above the source regions (including the first source region 404 and the second source region 405 ) and is electrically connected to the first source region 404 and the second source region 405 at the same time.
  • the source metal layer 410 may be a metal having low contact resistivity with SiC, such as aluminum, nickel, or the like.
  • the drain metal layer 411 is located under the substrate 401 and forms an ohmic contact with the substrate 401, and the drain metal can be a metal such as aluminum, nickel, etc., which has a low contact resistivity with SiC.
  • the silicon carbide device in this embodiment is a trench gate silicon carbide MOSFET device.
  • the first conductivity type and the second conductivity type are opposite.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • This embodiment provides a cell structure 400 of a silicon carbide device.
  • the gate dielectric layer 407 of the device in the blocking state can be greatly reduced
  • the electric field stress can greatly improve the long-term reliability of the device; the shielding region 406 is in contact with the bottom of the well region 403, and can be electrically connected to the source metal layer 410 through the well region 403 and the source region, thereby increasing the switching frequency of the device and reducing switching losses.
  • the shielding region 406 arranged at a vertical interval can separate the conductive region and the electric field protection region. The formation process of the shielding region 406 will not affect the ion doping concentration of the conductive region, and will not produce electrical characteristics such as the threshold voltage of the device. influence, which is beneficial to the flow sharing between cells.
  • an embodiment of the present disclosure provides a cell structure 500 of a silicon carbide device, including a substrate 501 , a drift layer 502 , a well region 503 , a source region (not marked in the figure), and a shield region 506 , a gate trench (not marked in the figure), a gate dielectric layer 507 , a gate electrode 508 , an interlayer dielectric layer 509 , a source metal layer 510 and a drain metal layer 511 .
  • the substrate 501 , the drift layer 502 , the well region 503 , the interlayer dielectric layer 509 , the source metal layer 510 and the drain metal layer 511 are not shown in FIG. 8 .
  • the shapes and positions of the substrate 501 , the drift layer 502 , the well region 503 , the interlayer dielectric layer 509 , the source metal layer 510 and the drain metal layer 511 can be understood.
  • the substrate 501 is a silicon carbide substrate 501 of the first conductivity type.
  • the thickness of the substrate 501 is relatively thick, the ion doping concentration is relatively high, and the ion doping concentration is greater than 1E18cm ⁇ 3 .
  • the drift layer 502 is a first conductivity type drift layer 502 located above the substrate 501 with an ion doping concentration of about 1E14 to 5E16 cm ⁇ 3 .
  • the ion doping concentration and thickness of the drift layer 502 need to be optimized according to the chip withstand voltage.
  • the well region 503 is a well region 503 of the second conductivity type, a plurality of well regions 503 are disposed in the surface of the drift layer 502 at intervals, and the upper surface of the well region 503 is flush with the upper surface of the drift layer 502 .
  • the ion doping concentration of the well region 503 is 1E16 to 1E18 cm ⁇ 3 , and the depth is 0.3 to 1.5 ⁇ m.
  • the source region is located in the surface of the well region 503.
  • the source region includes a first source region 504 and a second source region 505, which are alternately arranged in the longitudinal direction (Y direction).
  • the first source region 504 is a source region of the first conductivity type, the upper surface of the first source region 504 is flush with the upper surface of the well region 503, and the two ends of the first source region 504 are connected to the gate trenches on both sides. sidewall contact.
  • the width of the first source region 504 is equal to the width of the well region 503 , the depth of the first source region 504 is smaller than the depth of the well region 503 , the ion doping concentration of the first source region 504 is greater than 1E19 cm ⁇ 3 , and the depth is 0.2 to 0.5 ⁇ m.
  • the second source region 505 is a source region of the second conductivity type, the upper surface of the second source region 505 is flush with the upper surface of the well region 503 , the two ends of the second source region 505 are aligned with the gate trenches on both sides sidewall contact.
  • the width of the second source region 505 is equal to the width of the first source region 504 , the depth of the second source region 505 is greater than the depth of the first source region 504 but less than the depth of the well region 503 , the ion doping concentration of the second source region 505 The ion doping concentration of the well region 503 is greater than that of the well region 503 , the ion doping concentration of the second source region 505 is greater than 5E18 cm ⁇ 3 and the depth is 0.3 to 1.5 ⁇ m.
  • the silicon carbide device is a silicon carbide device with a body diode enhancement structure. Its body diode (not marked in the figure) has a higher on-current and better device performance.
  • the gate trench (not marked in the figure) is located between two adjacent well regions 503, and the sidewalls of the gate trench are in contact with the well region 503 and the first source region 504 in the source region at the same time.
  • the depth of the gate trench is greater than the depth of the well region 503 , the depth of the gate trench is 0.4 to 2.0 ⁇ m, and the width of the gate trench is 0.15 to 3.0 ⁇ m.
  • the gate dielectric layer 507 is uniformly arranged on the sidewall and bottom of the gate trench.
  • the gate dielectric layer 507 is an oxide layer with a thickness of about 30nm to 1000nm, wherein the thickness of the dielectric layer at the bottom of the trench can be higher than that of the sidewall dielectric layer. thickness to improve the withstand voltage capability of the bottom of the gate dielectric layer 507 .
  • the gate 508 is a polysilicon gate of the first conductivity type, disposed in the gate trench, and its ion doping concentration is greater than 1E18 cm ⁇ 3 .
  • the shielding region 506 is a doped region of the second conductivity type.
  • the shielding region 506 is located in the drift layer 502 and is spaced below the gate trench in the longitudinal direction (Y direction), and the top of the shielding region 506 is the bottom of the gate trench and the well.
  • the bottom of the region 503 is in contact, the ion doping concentration of the shielding region 506 is greater than 1E15 cm ⁇ 3 , and the junction depth (depth) of the shielding region 506 is 0.2 to 5 ⁇ m.
  • the shielding regions 506 under two adjacent gate trenches are aligned, and the shielding regions 506 are aligned with the second source region 505 in the lateral direction (X direction).
  • the shielding region 506 can greatly reduce the electric field stress of the gate dielectric layer 507 of the device in the blocking state, and greatly improve the long-term reliability of the device.
  • the top of the shielding region 506 is in contact with the bottom of the gate trench and the bottom of the well region 503, and the first source region 504 and the second source region 505 in the surface of the well region 503 are electrically connected to the source metal layer 510, so, The shielding region 506 is electrically connected (shorted) to the source metal layer 510 through the well region 503 and the second source region 505, which can increase the switching frequency of the device and reduce switching loss.
  • the trench gate (including the gate trench, the gate dielectric layer 507 and the gate 508 ) is in the shielded region.
  • the trench gate including the gate trench, the gate dielectric layer 507 and the gate 508 ) is in the shielded region.
  • no channel will be formed on both sides of the trench gate, and there will be no generation of channel current (on current), while in the part of the trench gate without the shielding region 506, the two sides of the trench gate will not be formed.
  • a channel is formed and a channel current (on current) is formed, that is, the electric field protection region and the conductive region can be separated and set, so as to ensure the on current and effectively reduce the electric field stress of the gate dielectric layer 507 in the blocking state.
  • the formation process of the shielding region 506 will not affect the ion doping concentration of the conductive region (trench surface), and will not affect the electrical characteristics such as the threshold voltage of the device, which is beneficial to the current sharing between cells.
  • the interlayer dielectric layer 509 is located above the gate electrode 508 , and the interlayer dielectric layer 509 isolates the gate electrode 508 from the source metal layer 510 .
  • the source metal layer 510 is located above the source regions (including the first source region 504 and the second source region 505 ) and is electrically connected to the first source region 504 and the second source region 505 at the same time.
  • the source metal layer 510 may be a metal having low contact resistivity with SiC, such as aluminum, nickel, or the like.
  • the drain metal layer 511 is located under the substrate 501 and forms an ohmic contact with the substrate 501.
  • the drain metal can be a metal such as aluminum, nickel, etc., which has a low contact resistivity with SiC.
  • the silicon carbide device in this embodiment is a trench gate silicon carbide MOSFET device.
  • the first conductivity type and the second conductivity type are opposite.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • This embodiment provides a cell structure 500 of a silicon carbide device.
  • the gate dielectric layer 507 of the device in the blocking state can be greatly reduced
  • the electric field stress can greatly improve the long-term reliability of the device; the shielding region 506 is in contact with the bottom of the well region 503, and can be electrically connected to the source metal layer 510 through the well region 503 and the source region, thereby increasing the switching frequency of the device and reducing switching losses.
  • the shielding region 506 arranged at vertical intervals can separate the conductive region and the electric field protection region, and the formation process of the shielding region 506 will not affect the ion doping concentration of the conductive region, and will not produce electrical characteristics such as the threshold voltage of the device. influence, which is beneficial to the flow sharing between cells.
  • FIG. 10 is a schematic flowchart of a method for fabricating a cell structure 200 of a silicon carbide device according to an embodiment of the present disclosure.
  • 11 to 15 are schematic cross-sectional structural diagrams formed by relevant steps of a method for fabricating a cell structure 200 of a silicon carbide device according to an embodiment of the present disclosure. Below, with reference to FIGS. 10 and 11 to 15 , the detailed steps of an exemplary method for fabricating the cell structure 200 of a silicon carbide device provided by an embodiment of the present disclosure will be described.
  • the preparation method of the cell structure 200 of the silicon carbide device in this embodiment includes the following steps:
  • Step S201 providing a silicon carbide substrate 201 of a first conductivity type.
  • the thickness of the substrate 201 is relatively thick, the ion doping concentration is relatively high, and the ion doping concentration is greater than 1E18 cm ⁇ 3 .
  • Step S202 as shown in FIG. 11 , a first conductivity type drift layer 202 is formed over the substrate 201 .
  • the drift layer 202 is a uniformly doped silicon carbide layer with an ion doping concentration of about 1E14 to 5E16 cm ⁇ 3 .
  • the ion doping concentration and thickness of the drift layer 202 need to be optimized according to the chip withstand voltage.
  • Step S203 forming a plurality of well regions 203 of the second conductivity type arranged at intervals in the surface of the drift layer 202 .
  • ions of the second conductivity type are implanted into the surface of the drift layer 202 to form a plurality of well regions 203 of the second conductivity type arranged at intervals.
  • the upper surface of the well region 203 is flush with the upper surface of the drift layer 202 .
  • the ion doping concentration of the well region 203 is 1E16 to 1E18 cm ⁇ 3 , and the depth is 0.3 to 1.5 ⁇ m.
  • Step S204 forming a source region in the surface of the well region 203 .
  • the source region includes a first source region 204 and a second source region 205 .
  • Step S204 specifically includes the following steps:
  • a first source region 204 of a first conductivity type is formed in the surface of the well region 203; wherein, two ends of the first source region 204 are respectively in contact with the sidewalls of the gate trenches on both sides;
  • first source region 204 longitudinally spaced second source regions 205 of the second conductivity type are formed; wherein the second source regions 205 are not in contact with the sidewalls of the gate trenches.
  • ions of the first conductivity type are implanted into the well region 203 to form a first source region 204 of the first conductivity type in the well region 203, and a photolithography process is used to selectively shield the first source region 204 with a photoresist.
  • a part of the surface of the source region 204 is implanted with ions of the second conductivity type into the first source region 204 by ion implantation, so as to form a second source region 205 of the second conductivity type in the first source region 204 .
  • the first source region 204 is a source region of the first conductivity type, the first source region 204 is located in the surface of the well region 203 , the upper surface of the first source region 204 is flush with the upper surface of the well region 203 , and the first source region 204 Both ends of the gate electrode are in contact with the sidewalls of the gate trenches on both sides.
  • the width of the first source region 204 is equal to the width of the well region 203 , the depth of the first source region 204 is smaller than the depth of the well region 203 , the ion doping concentration of the first source region 204 is greater than 1E19 cm ⁇ 3 , and the depth is 0.2 to 0.5 ⁇ m.
  • the second source region 205 is a source region of the second conductivity type, the second source region 205 is disposed in the first source region 204 at intervals in the longitudinal direction (Y direction), and the upper surface of the second source region 205 is opposite to the upper surface of the well region 203 Flush, the second source region 205 is not in contact with the sidewall of the gate trench.
  • the width of the second source region 205 is smaller than the width of the first source region 204 , the depth of the second source region 205 is greater than the depth of the first source region 204 , but smaller than the depth of the well region 203 , the ion doping concentration of the second source region 205 .
  • the ion doping concentration of the well region 203 is greater than that of the well region 203 , the ion doping concentration of the second source region 205 is greater than 5E18 cm ⁇ 3 , and the depth is 0.3 to 1.5 ⁇ m.
  • Step S205 forming a gate trench between two adjacent well regions 203 ; wherein the sidewall of the gate trench is in contact with the well region 203 and the source region at the same time, and the depth of the gate trench is greater than the depth of the well region 203 .
  • a region between two adjacent well regions 203 is etched to form a gate trench between two adjacent well regions 203 .
  • the sidewall of the gate trench is in contact with the well region 203 and the first source region 204 in the source region at the same time.
  • the depth of the gate trench is greater than the depth of the well region 203 , the depth of the gate trench is 0.4 to 2.0 ⁇ m, and the width of the gate trench is 0.15 to 3.0 ⁇ m.
  • the above steps of forming the well region 203, the first source region 204, the second source region 205 and the gate trench may also be: forming the well region 203 on the entire surface ⁇ forming the first source region 204 and the second source region 205 Source region 205 ⁇ etch to form gate trenches.
  • Step S206 as shown in FIG. 12 , forming second conductivity type shielding regions 206 spaced in the longitudinal direction (Y direction) in the drift layer 202 under the gate trench by means of oblique ion implantation; wherein, the top of the shielding region 206 is Contacts the bottom of the gate trench and the bottom of the well region 203 .
  • the upper surface of the source region (including the first source region 204 and the second source region 205) and part of the bottom and sidewalls of each gate trench are selectively shielded by photoresist.
  • ions of the second conductivity type can not only be implanted into the drift layer 202 at the bottom of the trench, but also ions of the second conductivity type can be implanted into the drift layer 202 next to the sidewall of the trench not covered by photoresist near the bottom , and then through the high temperature impurity activation annealing process, the second conductive type shielding regions 206 arranged at vertical intervals can be formed under the gate trench. The top of the shield region 206 is in contact with the bottom of the gate trench and the bottom of the well region 203 .
  • the shielding regions 206 under two adjacent gate trenches are aligned.
  • Step S207 as shown in FIG. 13 , a gate dielectric layer 207 is formed on the sidewall and bottom of the gate trench.
  • step S207 includes the following steps:
  • S207a performing sacrificial oxidation treatment on the surface of the drift layer 202, the sidewalls and the bottom of the gate trench;
  • S207b forming a gate dielectric layer 207 above the drift layer 202, sidewalls and bottom of the gate trench;
  • S207c The gate dielectric layer 207 above the drift layer 202 is etched away.
  • the sacrificial oxidation treatment includes the following steps:
  • the gate dielectric layer 207 is an oxide layer, similar to the sacrificial oxide layer, which is formed by thermal oxidation in an oxygen atmosphere at a high temperature (eg, 1300° C.).
  • the thickness of the gate dielectric layer 207 is about 30 nm to 1000 nm.
  • the thickness of the dielectric layer at the bottom of the trench may be higher than the thickness of the sidewall dielectric layer, so as to improve the withstand voltage capability of the bottom of the gate dielectric layer 207 .
  • the shielding region 206 can greatly reduce the electric field stress of the gate dielectric layer 207 of the device in the blocking state, and greatly improve the long-term reliability of the device.
  • Step S208 filling the gate trench with polysilicon to form the gate 208 .
  • the filled polysilicon is high-concentration doped polysilicon of the first conductivity type, and the ion doping concentration is greater than 1E18cm ⁇ 3 .
  • Step S209 as shown in FIG. 14 , an interlayer dielectric layer 209 covering the gate electrode 208 is formed over the gate electrode 208 .
  • an entire interlayer dielectric layer 209 is formed above the drift layer 202 first, and then only the interlayer dielectric layer 209 above the gate electrode 208 is left by etching.
  • Step S210 forming a source metal layer 210 electrically connected to the source region over the source region; wherein the gate 208 is isolated from the source metal layer 210 by the interlayer dielectric layer 209 , and the shielding region 206 is connected to the source metal layer 210 through the well region 203 and the source region.
  • the source metal layer 210 is electrically connected.
  • a source metal layer 210 is formed over the first source region 204 and the second source region 205 while being electrically connected to the first source region 204 and the second source region 205 .
  • the shielding region 206 is electrically connected (short-circuited) to the source metal layer 210 through the well region 203 and the second source region 205, which can increase the switching frequency of the device and reduce switching loss.
  • the trench gate (including the gate trench, the gate dielectric layer 207 and the gate 208 ) is in the shielded region. In the part of 206, a channel will not be formed on both sides of the trench gate, and there will be no generation of channel current (on current), while in the part of the trench gate without the shielding region 206, the two sides of the trench gate will not be formed.
  • a channel is formed to form a channel current (on-current), that is, the electric field protection region and the conductive region can be separated and set to achieve the effect of not only ensuring the on-current but also effectively reducing the electric field stress of the gate dielectric layer 207 in the blocking state.
  • on-current channel current
  • the formation process of the shielding region 206 will not affect the ion doping concentration of the conductive region (trench surface), and will not affect the electrical characteristics such as the threshold voltage of the device, which is beneficial to the current sharing between cells.
  • the source metal layer 210 may be a metal having low contact resistivity with SiC, such as aluminum, nickel, or the like.
  • Step S211 As shown in FIG. 15 , a drain metal layer 211 in ohmic contact with the substrate 201 is formed under the substrate 201 .
  • a drain metal layer 211 that is in ohmic contact with the substrate 201 is formed under the substrate 201 through a metallization process.
  • the drain metal layer 211 may be a metal having low contact resistivity with SiC, such as aluminum and nickel.
  • the whole preparation process has the advantages of simple manufacturing process, strong manufacturability and low manufacturing cost.
  • the first conductivity type and the second conductivity type are opposite.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • This embodiment provides a method for fabricating a cell structure 200 of a silicon carbide device.
  • the gate of the device in the blocking state can be greatly reduced.
  • the electric field stress of the dielectric layer 207 greatly improves the long-term reliability of the device; the shielding region 206 is in contact with the bottom of the well region 203, and can be electrically connected to the source metal layer 210 through the well region 203 and the source region, thereby increasing the switching frequency of the device, Reduce switching loss; the shielding region 206 arranged at vertical intervals can separate the conductive region and the electric field protection region.
  • the formation process of the shielding region 206 will not affect the ion doping concentration of the conductive region, and will not affect the threshold voltage of the device, etc.
  • the electrical characteristics have an effect, which is beneficial to the current sharing between cells.
  • the preparation process is simple, the manufacturability is strong, and the manufacturing cost is low.
  • this embodiment provides a method for preparing a cell structure 300 of a silicon carbide device.
  • the preparation method of the cell structure 300 of the silicon carbide device is similar to the preparation method of the cell structure 200 of the silicon carbide device in the fifth embodiment, and the difference is only in the position of the shielding region 306, so it is not repeated here.
  • FIG. 16 is a schematic flowchart of a method for fabricating a cell structure 400 of a silicon carbide device according to an embodiment of the present disclosure.
  • the preparation method of the cell structure 400 of the silicon carbide device in this embodiment includes the following steps:
  • Step S401 providing a silicon carbide substrate 401 of a first conductivity type.
  • the thickness of the substrate 401 is relatively thick, the ion doping concentration is relatively high, and the ion doping concentration is greater than 1E18 cm ⁇ 3 .
  • Step S402 forming a first conductivity type drift layer 402 over the substrate 401 .
  • the drift layer 402 is a uniformly doped silicon carbide layer with an ion doping concentration of about 1E14 to 5E16 cm ⁇ 3 .
  • the ion doping concentration and thickness of the drift layer 402 need to be optimized according to the chip withstand voltage.
  • Step S403 forming a plurality of second conductivity type well regions 403 arranged at intervals in the surface of the drift layer 402 .
  • ions of the second conductivity type are implanted into the surface of the drift layer 402 to form a plurality of well regions 403 of the second conductivity type arranged at intervals.
  • the upper surface of the well region 403 is flush with the upper surface of the drift layer 402 .
  • the ion doping concentration of the well region 403 is 1E16 to 1E18 cm ⁇ 3 , and the depth is 0.3 to 1.5 ⁇ m.
  • Step S404 forming a source region in the surface of the well region 403 .
  • the source region includes a first source region 404 of a first conductivity type, and a second source region 405 of a second conductivity type disposed in the first source region 404 with a longitudinal interval.
  • Step S404 specifically includes the following steps:
  • a first source region 404 of a first conductivity type is formed in the surface of the well region 403; wherein, two ends of the first source region 404 are respectively in contact with the sidewalls of the gate trenches on both sides;
  • the second source regions 405 of the second conductivity type are formed in the first source region 404 at intervals; wherein the second source regions 405 are not in contact with the sidewalls of the gate trenches.
  • ions of the first conductivity type are implanted into the well region 403 to form a first source region 404 of the first conductivity type in the well region 403, and a photolithography process is used to selectively shield the first source region 404 with a photoresist.
  • Part of the surface of the source region 404 is implanted with ions of the second conductivity type into the first source region 404 by ion implantation, so as to form a second source region 405 of the second conductivity type in the first source region 404 .
  • the first source region 404 is a source region of the first conductivity type, the first source region 404 is located in the surface of the well region 403 , the upper surface of the first source region 404 is flush with the upper surface of the well region 403 , and the first source region 404 Both ends of the gate electrode are in contact with the sidewalls of the gate trenches on both sides.
  • the width of the first source region 404 is equal to the width of the well region 403 , the depth of the first source region 404 is smaller than that of the well region 403 , the ion doping concentration of the first source region 404 is greater than 1E19 cm ⁇ 3 , and the depth is 0.2 to 0.5 ⁇ m.
  • the second source region 405 is a source region of the second conductivity type, the second source region 405 is disposed in the first source region 404 at intervals in the longitudinal direction (Y direction), and the upper surface of the second source region 405 is opposite to the upper surface of the well region 403 Flush, the second source region 405 is not in contact with the sidewalls of the gate trenches.
  • the width of the second source region 405 is smaller than the width of the first source region 404 , the depth of the second source region 405 is greater than the depth of the first source region 404 , but smaller than the depth of the well region 403 , the ion doping concentration of the second source region 405
  • the ion doping concentration of the well region 403 is greater than that of the well region 403
  • the ion doping concentration of the second source region 405 is greater than 5E18 cm ⁇ 3
  • the depth is 0.3 to 1.5 ⁇ m.
  • Step S405 forming a gate trench between two adjacent well regions 403 ; wherein the sidewall of the gate trench is in contact with the well region 403 and the source region at the same time, and the depth of the gate trench is greater than that of the well region 403 .
  • a region between two adjacent well regions 403 is etched to form a gate trench between two adjacent well regions 403 .
  • the sidewall of the gate trench is in contact with the well region 403 and the first source region 404 in the source region at the same time.
  • the depth of the gate trench is greater than the depth of the well region 403 , the depth of the gate trench is 0.4 to 2.0 ⁇ m, and the width of the gate trench is 0.15 to 3.0 ⁇ m.
  • the above-mentioned steps of forming the well region 403, the first source region 404, the second source region 405 and the gate trench may also be: forming the well region 403 on the entire surface ⁇ forming the first source region 404 and the second source region 405 Source region 405 ⁇ etch to form gate trenches.
  • Step S406 forming second conductivity type shielding regions 406 spaced in the longitudinal direction (Y direction) in the drift layer 402 under the gate trench by means of oblique ion implantation; wherein, the top of the shielding region 406 and the gate trench are formed. The bottom is in contact with the bottom of the well region 403 .
  • the upper surface of the source region (including the first source region 404 and the second source region 405) and part of the bottom and sidewalls of each gate trench are selectively shielded by photoresist.
  • ions can be implanted not only in the drift layer 402 at the bottom of the trench, but also in the drift layer 402 next to the sidewall of the trench near the bottom of the trench that is not covered by photoresist, and then activate the annealing process through high temperature impurities, that is, Vertically spaced second conductivity type shield regions 406 may be formed under the gate trenches. The top of the shield region 406 is in contact with the bottom of the gate trench and the bottom of the well region 403 .
  • the shielding regions 406 under two adjacent gate trenches are aligned or staggered.
  • Step S407 forming a first conductive type storage region 412 under the gate trench; wherein the storage region 412 and the shielding region 406 are alternately arranged at intervals in the longitudinal direction, and the top of the storage region 412 and the bottom of the gate trench and the well region 403 bottom contact.
  • the upper surface of the source region (including the first source region 404 and the second source region 405) and the shielding region 406 are selectively shielded by photoresist. Ions of the first conductivity type are implanted into the drift layer 402, or ions of the first conductivity type can be implanted into the drift layer 402 next to the sidewall of the trench not covered by photoresist near the bottom, and then the high temperature impurity activation annealing process is performed. , the first conductive type storage region 412 can be formed under the gate trench.
  • the storage regions 412 and the shielding regions 406 are alternately arranged at intervals in the longitudinal direction, the storage regions 412 are not in contact with the shielding regions 406 , and the tops of the storage regions 412 are in contact with the bottom of the gate trench and the bottom of the well region 403 .
  • the storage area 412 can enhance the conduction current capability of the conductive area. Based on the existence of the storage area 412, the area size of the conductive area can be further reduced, that is, the longitudinal distance between the shielding areas 406 can be further reduced, and the size of the conduction area can be further reduced. Affects the conduction current capability of the conduction region.
  • Step S408 forming a gate dielectric layer 407 on the sidewall and bottom of the gate trench.
  • step S408 includes the following steps:
  • S408a performing sacrificial oxidation treatment on the surface of the drift layer 402, the sidewalls and the bottom of the gate trench;
  • S408b forming a gate dielectric layer 407 above the drift layer 402, sidewalls and bottom of the gate trench;
  • the sacrificial oxidation treatment includes the following steps:
  • the gate dielectric layer 407 is an oxide layer. Similar to the sacrificial oxide layer, it is formed by thermal oxidation in an oxygen atmosphere at a high temperature (eg, 1300° C.). The thickness of the gate dielectric layer 407 is about 30 nm to 1000 nm. The thickness of the dielectric layer at the bottom of the trench may be higher than that of the sidewall dielectric layer, so as to improve the withstand voltage capability of the bottom of the gate dielectric layer 407 .
  • the shielding region 406 can greatly reduce the electric field stress of the gate dielectric layer 407 of the device in the blocking state, and greatly improve the long-term reliability of the device.
  • Step S409 filling the gate trench with polysilicon to form the gate 408 .
  • the filled polysilicon is high-concentration doped polysilicon of the first conductivity type, and the ion doping concentration is greater than 1E18cm ⁇ 3 .
  • Step S410 forming an interlayer dielectric layer 409 covering the gate electrode 408 over the gate electrode 408 .
  • an entire interlayer dielectric layer 409 is formed above the drift layer 402 first, and then only the interlayer dielectric layer 409 above the gate electrode 408 is left by etching.
  • Step S411 forming a source metal layer 410 electrically connected to the source region above the source region; wherein the gate 408 is isolated from the source metal layer 410 by the interlayer dielectric layer 409 , and the shielding region 406 is connected to the source metal layer 410 through the well region 403 and the source region.
  • the source metal layer 410 is electrically connected.
  • a source metal layer 410 is formed over the first source region 404 and the second source region 405 while being electrically connected to the first source region 404 and the second source region 405 .
  • the shielding region 406 Since the top of the shielding region 406 is in contact with the bottom of the gate trench and the bottom of the well region 403, and the first source region 404 and the second source region 405 in the surface of the well region 403 are electrically connected to the source metal layer 410, therefore, The shielding region 406 is electrically connected (short-circuited) to the source metal layer 410 through the well region 403 and the second source region 405, which can increase the switching frequency of the device and reduce switching loss.
  • the trench gate (including the gate trench, the gate dielectric layer 407 and the gate 408 ) is in the shielded region.
  • the two sides of the trench gate will be A channel is formed and a channel current (on current) is formed, that is, the electric field protection region and the conductive region can be separated and set to achieve the effect of not only ensuring the on current but also effectively reducing the electric field stress of the gate dielectric layer 407 in the blocking state.
  • the formation process of the shielding region 406 will not affect the ion doping concentration of the conductive region (trench surface), and will not affect the electrical characteristics such as the threshold voltage of the device, which is beneficial to the current sharing between cells.
  • the source metal layer 410 may be a metal having low contact resistivity with SiC, such as aluminum, nickel, or the like.
  • Step S412 forming a drain metal layer 411 under the substrate 401 in ohmic contact with the substrate 401 .
  • a drain metal layer 411 in ohmic contact with the substrate 401 is formed under the substrate 401 , and the drain metal layer 411 may be a metal having low contact resistivity with SiC, such as aluminum and nickel.
  • the whole preparation process has the advantages of simple manufacturing process, strong manufacturability and low manufacturing cost.
  • the first conductivity type and the second conductivity type are opposite.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • This embodiment provides a method for fabricating a cell structure 400 of a silicon carbide device.
  • the gate of the device in the blocking state can be greatly reduced.
  • the electric field stress of the dielectric layer 407 greatly improves the long-term reliability of the device; the shielding region 406 is in contact with the bottom of the well region 403, and can be electrically connected to the source metal layer 410 through the well region 403 and the source region, thereby increasing the switching frequency of the device, Reduce switching loss; the shielding region 406 arranged at vertical intervals can separate the conductive region and the electric field protection region.
  • the formation process of the shielding region 406 will not affect the ion doping concentration of the conductive region, and will not affect the threshold voltage of the device, etc.
  • the electrical characteristics have an effect, which is beneficial to the current sharing between cells.
  • the preparation process is simple, the manufacturability is strong, and the manufacturing cost is low.
  • FIG. 17 is a schematic flowchart of a method for fabricating a cell structure 500 of a silicon carbide device according to an embodiment of the present disclosure.
  • the preparation method of the cell structure 500 of the silicon carbide device in this embodiment includes the following steps:
  • Step S501 providing a silicon carbide substrate 501 of a first conductivity type.
  • the thickness of the substrate 501 is relatively thick, the ion doping concentration is relatively high, and the ion doping concentration is greater than 1E18cm ⁇ 3 .
  • Step S502 forming a first conductivity type drift layer 502 over the substrate 501 .
  • the drift layer 502 is a uniformly doped silicon carbide layer with an ion doping concentration of about 1E14 to 5E16 cm ⁇ 3 .
  • the ion doping concentration and thickness of the drift layer 502 need to be optimized according to the chip withstand voltage.
  • Step S503 forming a plurality of second conductivity type well regions 503 arranged at intervals in the surface of the drift layer 502 .
  • ions of the second conductivity type are implanted into the surface of the drift layer 502 to form a plurality of well regions 503 of the second conductivity type arranged at intervals.
  • the upper surface of the well region 503 is flush with the upper surface of the drift layer 502 .
  • the ion doping concentration of the well region 503 is 1E16 to 1E18 cm ⁇ 3 , and the depth is 0.3 to 1.5 ⁇ m.
  • Step S504 forming a source region in the surface of the well region 503 .
  • the source region includes first source regions 504 of the first conductivity type and second source regions 505 of the second conductivity type alternately arranged in the longitudinal direction.
  • ions of the first conductivity type and ions of the second conductivity type are selectively implanted in the well region 503 in sequence, and the first source region 504 of the first conductivity type and the first source region 504 of the second conductivity type are alternately arranged in the longitudinal direction in the surface of the well region 503 The second source region 505 .
  • the first source region 504 is a source region of the first conductivity type, the upper surface of the first source region 504 is flush with the upper surface of the well region 503 , and both ends of the first source region 504 are aligned with both ends of the well region 503 .
  • the width of the first source region 504 is equal to the width of the well region 503 , the depth of the first source region 504 is smaller than the depth of the well region 503 , the ion doping concentration of the first source region 504 is greater than 1E19 cm ⁇ 3 , and the depth is 0.2 to 0.5 ⁇ m.
  • the second source region 505 is a source region of the second conductivity type, the upper surface of the second source region 505 is flush with the upper surface of the well region 503 , and both ends of the second source region 505 are aligned with both ends of the well region 503 .
  • the width of the second source region 505 is equal to the width of the first source region 504 , the depth of the second source region 505 is greater than the depth of the first source region 504 but less than the depth of the well region 503 , the ion doping concentration of the second source region 505 The ion doping concentration of the well region 503 is greater than that of the well region 503 , the ion doping concentration of the second source region 505 is greater than 5E18 cm ⁇ 3 and the depth is 0.3 to 1.5 ⁇ m.
  • the formed silicon carbide device is a silicon carbide device with a body diode enhancement structure. Its body diode (not marked in the figure) has a higher on-current and better device performance.
  • Step S505 forming a gate trench between two adjacent well regions 503 ; wherein the sidewall of the gate trench is in contact with the well region 503 and the source region at the same time, and the depth of the gate trench is greater than that of the well region 503 .
  • a region between two adjacent well regions 503 is etched to form gate trenches between two adjacent well regions 503 .
  • the sidewalls of the gate trench are in contact with the well region 503 , the first source region 504 and the second source region 505 at the same time.
  • the depth of the gate trench is greater than the depth of the well region 503 , the depth of the gate trench is 0.4 to 2.0 ⁇ m, and the width of the gate trench is 0.15 to 3.0 ⁇ m.
  • the above steps of forming the well region 503, the first source region 504, the second source region 505 and the gate trench may also be: forming the well region 503 on the entire surface ⁇ forming the first source region 504 and the second source region 505 Source region 505 ⁇ etch to form gate trenches.
  • Step S506 forming second conductive type shielding regions 506 spaced in the longitudinal direction (Y direction) in the drift layer 502 under the gate trench by means of oblique ion implantation; wherein the top of the shielding region 506 and the gate trench are formed. The bottom is in contact with the bottom of the well region 503 , and the shielding region 506 is arranged in lateral alignment with the second source region 505 .
  • the upper surface of the source region (including the first source region 504 and the second source region 505) and part of the bottom and sidewalls of the gate trenches are selectively shielded by photoresist.
  • ions of the second conductivity type can be implanted not only in the drift layer 502 at the bottom of the trench, but also in the drift layer 502 next to the sidewall of the trench near the bottom of the trench not covered by photoresist.
  • the second conductive type shielding regions 506 spaced vertically can be formed under the gate trench. The top of the shield region 506 is in contact with the bottom of the gate trench and the bottom of the well region 503 .
  • the shielding regions 506 under two adjacent gate trenches are aligned.
  • Step S507 forming a gate dielectric layer 507 on the sidewall and bottom of the gate trench.
  • step S507 includes the following steps:
  • S507a performing sacrificial oxidation treatment on the surface of the drift layer 502, the sidewalls and the bottom of the gate trench;
  • S507b forming a gate dielectric layer 507 over the drift layer 502, sidewalls and bottom of the gate trench;
  • S507c The gate dielectric layer 507 above the drift layer 502 is etched away.
  • the sacrificial oxidation treatment includes the following steps:
  • the gate dielectric layer 507 is an oxide layer, similar to the sacrificial oxide layer, which is formed by thermal oxidation in the oxygen range at a high temperature (eg, 1300° C.).
  • the thickness of the gate dielectric layer 507 is about 30 to 1000 nm.
  • the thickness of the dielectric layer at the bottom of the trench may be higher than that of the sidewall dielectric layer, so as to improve the withstand voltage capability of the bottom of the gate dielectric layer 507 .
  • the shielding region 506 can greatly reduce the electric field stress of the gate dielectric layer 507 of the device in the blocking state, and greatly improve the long-term reliability of the device.
  • Step S508 filling the gate trench with polysilicon to form the gate 508 .
  • the filled polysilicon is high-concentration doped polysilicon of the first conductivity type, and the ion doping concentration is greater than 1E18cm ⁇ 3 .
  • Step S509 forming an interlayer dielectric layer 509 covering the gate electrode 508 over the gate electrode 508 .
  • an entire interlayer dielectric layer 509 is formed above the drift layer 502 first, and then only the interlayer dielectric layer 509 above the gate electrode 508 is left by etching.
  • Step S510 forming a source metal layer 510 electrically connected to the source region over the source region; wherein the gate 508 is isolated from the source metal layer 510 by the interlayer dielectric layer 509 , and the shielding region 506 is connected to the source metal layer 510 through the well region 503 and the source region.
  • the source metal layer 510 is electrically connected.
  • a source metal layer 510 is formed over the first source region 504 and the second source region 505 while being electrically connected to the first source region 504 and the second source region 505 .
  • the shielding region 506 is electrically connected (shorted) to the source metal layer 510 through the well region 503 and the second source region 505, which can increase the switching frequency of the device and reduce switching loss.
  • the trench gate (including the gate trench, the gate dielectric layer 507 and the gate 508 ) is in the shielded region.
  • the trench gate including the gate trench, the gate dielectric layer 507 and the gate 508 ) is in the shielded region.
  • no channel will be formed on both sides of the trench gate, and there will be no generation of channel current (on current), while in the part of the trench gate without the shielding region 506, the two sides of the trench gate will not be formed.
  • a channel is formed and a channel current (on current) is formed, that is, the electric field protection region and the conductive region can be separated and set, so as to ensure the on current and effectively reduce the electric field stress of the gate dielectric layer 507 in the blocking state.
  • the formation process of the shielding region 506 will not affect the ion doping concentration of the conductive region (trench surface), and will not affect the electrical characteristics such as the threshold voltage of the device, which is beneficial to the current sharing between cells.
  • the source metal layer 510 may be a metal having low contact resistivity with SiC, such as aluminum, nickel, or the like.
  • Step S511 forming a drain metal layer 511 under the substrate 501 in ohmic contact with the substrate 501 .
  • a drain metal layer 511 in ohmic contact with the substrate 501 is formed under the substrate 501, and the drain metal layer 511 may be a metal having low contact resistivity with SiC, such as aluminum and nickel.
  • the whole preparation process has the advantages of simple manufacturing process, strong manufacturability and low manufacturing cost.
  • the first conductivity type and the second conductivity type are opposite.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • This embodiment provides a method for fabricating a cell structure 500 of a silicon carbide device.
  • the gate of the device in the blocking state can be greatly reduced
  • the electric field stress of the dielectric layer 507 greatly improves the long-term reliability of the device; the shielding region 506 is in contact with the bottom of the well region 503, and can be electrically connected to the source metal layer 510 through the well region 503 and the source region, thereby increasing the switching frequency of the device.
  • the shielding region 506 arranged at vertical intervals can separate the conductive region and the electric field protection region, and the formation process of the shielding region 506 will not affect the ion doping concentration of the conductive region, and will not affect the threshold voltage of the device, etc.
  • the electrical characteristics have an effect, which is beneficial to the current sharing between cells.
  • the preparation process is simple, the manufacturability is strong, and the manufacturing cost is low.

Abstract

一种碳化硅器件的元胞结构、其制备方法及碳化硅器件，元胞结构包括：多个间隔设置于漂移层（202）表面内的第二导电类型阱区（203）；位于阱区（203）表面内的源区；位于相邻两个阱区（203）之间的栅极沟槽；位于漂移层（202）内且纵向间隔设置于栅极沟槽下方的第二导电类型屏蔽区（206）；其中，屏蔽区（206）的顶部与栅极沟槽的底部和阱区（203）的底部接触。通过在栅极沟槽底部设置纵向间隔的第二导电类型的屏蔽区（206），可大幅降低阻断状态下器件的栅极介质层的电场应力，大幅提高器件的长期使用可靠性；屏蔽区（206）与源极金属层（211）电连接，可以提高器件的开关频率，降低开关损耗。

Description

碳化硅器件的元胞结构、其制备方法及碳化硅器件
本公开要求享有2020年11月27日提交的名称为“碳化硅器件的元胞结构、其制备方法及碳化硅器件”的中国专利申请202011354573.6的优先权，其全部内容通过引用并入本文中。
技术领域
本公开涉及半导体器件技术领域，具体涉及一种碳化硅器件的元胞结构、其制备方法及碳化硅器件。
背景技术
随着新能源电动汽车市场的兴起，新型宽禁带半导体碳化硅(SiC)功率器件迎来快速发展契机，这要归结于碳化硅材料具有出色的物理、化学和电性能，例如，碳化硅的击穿电场强度是硅的10倍、导热率是硅的3倍等。尤其是碳化硅金属氧化物半导体场效应管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)器件，已有多家厂商推出了商业化产品。但是，碳化硅功率器件(MOSFET)也仍存在一些基本问题，尤其是平面栅碳化硅功率器件(MOSFET)，在碳化硅和栅极介质层界面存在大量的缺陷，使沟道的载子迁移率大幅降低。
而沟槽栅碳化硅功率器件(MOSFET)可利用碳化硅材料的各向异性，使用接近
Figure PCTCN2021125473-appb-000001
晶面以获得相对较高的沟道载流子迁移率，传统沟槽栅碳化硅功率器件(MOSFET)的元胞结构100如图1所示，包括衬底101、漂移层102、阱区103、第一源区104、第二源区105、栅极介质层106、栅极107、层间介质层108、源极金属层109和漏极金属层110。然而沟槽栅碳化硅功率器件(MOSFET)由于碳化硅材料与栅极介质层材料的介电常数差异，根据高斯定律，介质层内部的电场强度是碳化硅内部电场峰值的2.5倍，且碳化硅材料本身具有较高的临界击穿电场，这将导致栅极介质层电场应力过大，进而影响器件长期可靠性，甚至导致器件失效。
发明内容
针对上述问题，本公开提供了一种碳化硅器件的元胞结构、其制备方法及碳化硅器件，解决了现有技术中碳化硅器件在阻断状态下由于电场应力损害栅极介质层导致器件失效及可靠性变差的技术问题。
第一方面，本公开提供一种碳化硅器件的元胞结构，包括：
第一导电类型碳化硅衬底；
位于所述衬底上方的第一导电类型漂移层；
多个间隔设置于所述漂移层表面内的第二导电类型阱区；
位于所述阱区表面内的源区；
位于相邻两个所述阱区之间的栅极沟槽；其中，所述栅极沟槽的侧壁同时与所述阱区和所述源区接触，所述栅极沟槽的深度大于所述阱区的深度；
位于所述漂移层内且纵向间隔设置于所述栅极沟槽下方的第二导电类屏蔽区；其中，所述屏蔽区的顶部与所述栅极沟槽的底部和所述阱区的底部接触。
根据本公开的实施例，优选地，所述源区包括第一导电类型第一源区，以及纵向间隔设置于所述第一源区内的第二导电类型第二源区；
其中，所述第一源区的两端分别与两侧的所述栅极沟槽的侧壁接触，所述第二源区不与所述栅极沟槽的侧壁接触。
根据本公开的实施例，优选地，相邻两个所述栅极沟槽下方的所述屏蔽区交错设置。
根据本公开的实施例，优选地，还包括：
位于所述栅极沟槽下方的第一导电类型存储区；
其中，所述存储区和所述屏蔽区在纵向上间隔交替设置，所述存储区的顶部与所述栅极沟槽的底部和所述阱区的底部接触。
根据本公开的实施例，优选地，
相邻两个所述栅极沟槽下方的所述屏蔽区对齐设置。
根据本公开的实施例，优选地，所述源区包括在纵向上交替设置第一导电类型第一源区和第二导电类型第二源区；
其中，所述第二源区与所述屏蔽区横向对齐设置，所述第一源区和所述第二源区的两端分别与两侧的所述栅极沟槽的侧壁接触。
根据本公开的实施例，优选地，所述栅极沟槽的深度为0.4至2.0μm；
所述栅极沟槽的宽度为0.15至3.0μm。
根据本公开的实施例，优选地，
所述屏蔽区的离子掺杂浓度大于1E15cm -3；
所述屏蔽区的深度为0.2至5μm。
根据本公开的实施例，优选地，还包括：
设置于所述栅极沟槽的侧壁和底部的栅极介质层以及填充于所述栅极沟槽内的栅极；
位于所述源区上方且与所述源区形成电连接的源极金属层；其中，所述栅极通过层间 介质层与所述源极金属层隔离，所述屏蔽区通过所述阱区和所述源区与所述源极金属层电连接；
位于所述衬底下方并与所述衬底形成欧姆接触的漏极金属层。
第二方面，本公开提供一种碳化硅器件的元胞结构的制备方法，包括：
提供第一导电类型碳化硅衬底；
在所述衬底上方形成第一导电类型漂移层；
在所述漂移层表面内形成多个间隔设置的第二导电类型阱区；
在所述阱区表面内形成源区；
在相邻两个所述阱区之间形成栅极沟槽；其中，所述栅极沟槽的侧壁同时与所述阱区和所述源区接触，所述栅极沟槽的深度大于所述阱区的深度；
通过倾斜离子注入的方式在所述漂移层内于所述栅极沟槽下方形成纵向间隔设置的第二导电类型屏蔽区；其中，所述屏蔽区的顶部与所述栅极沟槽的底部和所述阱区的底部接触。
根据本公开的实施例，优选地，所述源区包括第一导电类型第一源区，以及纵向间隔设置于所述第一源区内的第二导电类型第二源区；所述在所述阱区表面内形成源区的步骤，包括以下步骤：
在所述阱区表面内形成第一导电类型第一源区；其中，所述第一源区的两端分别与两侧的所述栅极沟槽的侧壁接触；
在所述第一源区内形成纵向间隔设置的第二导电类型第二源区；其中，所述第二源区不与所述栅极沟槽的侧壁接触。
根据本公开的实施例，优选地，相邻两个所述栅极沟槽下方的所述屏蔽区交错设置。
根据本公开的实施例，优选地，所述通过倾斜离子注入的方式在所述漂移层内于所述栅极沟槽下方形成纵向间隔设置的第二导电类型屏蔽区的步骤之后，所述方法还包括：
在所述栅极沟槽下方形成第一导电类型存储区；
其中，所述存储区和所述屏蔽区在纵向上间隔交替设置，所述存储区的顶部与所述栅极沟槽的底部和所述阱区的底部接触。
根据本公开的实施例，优选地，相邻两个所述栅极沟槽下方的所述屏蔽区对齐设置。
根据本公开的实施例，优选地，所述源区包括在纵向上交替设置第一导电类型第一源区和第二导电类型第二源区；所述在所述阱区表面内形成源区的步骤，包括以下步骤：
在所述阱区表面内形成在纵向上交替设置第一导电类型第一源区和第二导电类型第二源区；
其中，所述第二源区与所述屏蔽区横向对齐设置，所述第一源区和所述第二源区的两 端分别与两侧的所述栅极沟槽的侧壁接触。
根据本公开的实施例，优选地，所述通过倾斜离子注入的方式在所述漂移层内于所述栅极沟槽下方形成纵向间隔设置的第二导电类型屏蔽区的步骤之后，所述方法还包括：
在所述栅极沟槽的侧壁和底部形成栅极介质层；
在所述栅极沟槽内填充多晶硅，以形成栅极；
在所述栅极上方形成覆盖所述栅极的层间介质层；
在所述源区上方形成与所述源区电连接的源极金属层；其中，所述栅极通过所述层间介质层与所述源极金属层隔离，所述屏蔽区通过所述阱区和所述源区与所述源极金属层电连接；
在所述衬底下方形成与所述衬底欧姆接触的漏极金属层。
第三方面，本公开提供一种碳化硅器件，包括若干如第一方面中任一项所述的碳化硅器件的元胞结构。
采用上述技术方案，至少能够达到如下技术效果：
(1)通过在栅极沟槽底部设置纵向间隔的第二导电类型的屏蔽区，可大幅降低阻断状态下器件的栅极介质层的电场应力，大幅提高器件的长期使用可靠性；
(2)所述屏蔽区与阱区的底部接触，可以通过阱区和源区(第二导电类型第二源区)与源极金属层电连接，提高器件的开关频率，降低开关损耗；
(3)在栅极沟槽底部纵向间隔设置的屏蔽区，可以将导电区域(底部没有屏蔽区的沟槽所在部分)与电场保护区域(底部设置屏蔽区的沟槽所在部分)进行分离设置，屏蔽区的形成过程不会影响到导电区域(沟槽表面)的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流；
(4)制备工艺制程简单，可制造性强且制造成本较低。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是传统的碳化硅器件的元胞结构的剖面结构示意图；
图2是本公开一示例性实施例示出的一种碳化硅器件的元胞结构的正面俯视示意图；
图3是本公开一示例性实施例示出的一种碳化硅器件的元胞结构的剖面结构示意图；
图4是本公开一示例性实施例示出的另一种碳化硅器件的元胞结构的正面俯视示意图；
图5是本公开一示例性实施例示出的另一种碳化硅器件的元胞结构的剖面结构示意 图；
图6是本公开一示例性实施例示出的另一种碳化硅器件的元胞结构的正面俯视示意图；
图7是本公开一示例性实施例示出的另一种碳化硅器件的元胞结构的剖面结构示意图；
图8是本公开一示例性实施例示出的另一种碳化硅器件的元胞结构的正面俯视示意图；
图9是本公开一示例性实施例示出的另一种碳化硅器件的元胞结构的剖面结构示意图；
图10是本公开一示例性实施例示出的一种碳化硅器件的元胞结构的制备方法流程示意图；
图11-15是本公开一示例性实施例示出的一种碳化硅器件的元胞结构的制备方法的相关步骤形成的剖面结构示意图；
图16是本公开一示例性实施例示出的另一种碳化硅器件的元胞结构的制备方法流程示意图；
图17是本公开一示例性实施例示出的另一种碳化硅器件的元胞结构的制备方法流程示意图；
在附图中，相同的部件使用相同的附图标记，附图并未按照实际的比例绘制。
具体实施方式
以下将结合附图及实施例来详细说明本公开的实施方式，借此对本公开如何应用技术手段来解决技术问题，并达到相应技术效果的实现过程能充分理解并据以实施。本公开实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本公开的保护范围之内。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应理解，尽管可使用术语“第一”、“第二”、“第三”等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
应理解，空间关系术语例如“在...上方”、位于...上方”、“在...下方”、“位于...下方”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件 或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下方”的元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下方”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述本公开的实施例。这样，可以预期由于例如制备技术和/或容差导致的从所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制备导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本公开的范围。
为了彻底理解本公开，将在下列的描述中提出详细的结构以及步骤，以便阐释本公开提出的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
实施例一
如图2和图3所示，本公开实施例提供一种碳化硅器件的元胞结构200，包括衬底201、漂移层202、阱区203、源区(图中未标注)、屏蔽区206、栅极沟槽(图中未标注)、栅极介质层207、栅极208、层间介质层209、源极金属层210和漏极金属层211。
需要说明的是，本实施例中，以下的“横向”是指“X方向”，“纵向”是指“Y方向”，“宽度”是指“X方向的宽度”，深度是指“Z方向的深度”。
需要说明的是，为了在图2中清楚显示源区(图中未标注)、屏蔽区206、栅极沟槽(图中未标注)、栅极介质层207和栅极208的形状和位置，所以图2中并未示出衬底201、漂移层202、阱区203、层间介质层209、源极金属层210和漏极金属层211。但是结合图3是可以理解到衬底201、漂移层202、阱区203、层间介质层209、源极金属层210和漏 极金属层211的形状和位置。
示例性地，衬底201为第一导电类型的碳化硅衬底201。衬底201的厚度较厚，离子掺杂浓度较高，离子掺杂浓度大于1E18cm -3。
漂移层202为第一导电类型的漂移层202，位于衬底201上方，离子掺杂浓度约为1E14至5E16cm -3，漂移层202的离子掺杂浓度与厚度具体需要根据芯片耐压来优化。
阱区203为第二导电类型的阱区203，多个阱区203间隔设置于漂移层202表面内，阱区203的上表面与漂移层202的上表面相平齐。阱区203的离子掺杂浓度为1E16至1E18cm -3，深度为0.3至1.5μm。
源区位于阱区203表面内，本实施例中，源区包括第一源区204和第二源区205。
第一源区204为第一导电类型的源区，第一源区204位于阱区203表面内，第一源区204的上表面与阱区203的上表面相平齐，第一源区204的两端与两侧的栅极沟槽的侧壁接触。第一源区204的宽度等于阱区203的宽度，第一源区204的深度小于阱区203的深度，第一源区204的离子掺杂浓度大于1E19cm -3，深度为0.2至0.5μm。
第二源区205为第二导电类型的源区，第二源区205纵向(Y方向)间隔设置于第一源区204内，第二源区205的上表面与阱区203的上表面相平齐，第二源区205不与栅极沟槽的侧壁接触。第二源区205的宽度小于第一源区204的宽度，第二源区205的深度大于第一源区204的深度，但小于阱区203的深度，第二源区205的离子掺杂浓度大于阱区203的离子掺杂浓度，第二源区205的离子掺杂浓度大于5E18cm -3，深度为0.3至1.5μm。
栅极沟槽(图中未标注)位于相邻两个阱区203之间，栅极沟槽的侧壁同时与阱区203和源区中的第一源区204接触。栅极沟槽的深度大于阱区203的深度，栅极沟槽的深度为0.4至2.0μm，栅极沟槽的宽度为0.15至3.0μm。
栅极介质层207均匀地设置于栅极沟槽的侧壁和底部，栅极介质层207可以为氧化层，厚度约30nm至1000nm，其中沟槽底部的介质层厚度可以高于侧壁介质层的厚度，以提高栅极介质层207底部的耐压能力。
栅极208为第一导电类型的多晶硅栅极，设置于栅极沟槽内，其离子掺杂浓度大于1E18cm -3。
屏蔽区206为第二导电类型的掺杂区，屏蔽区206位于漂移层202内且纵向(Y方向)间隔设置于栅极沟槽下方，屏蔽区206的顶部与栅极沟槽的底部和阱区203的底部接触，屏蔽区206的离子掺杂浓度大于1E15cm -3，且屏蔽区206的结深(深度)为0.2至5μm。
本实施例中，相邻两个栅极沟槽下方的屏蔽区206对齐设置。
屏蔽区206可大幅降低阻断状态下器件的栅极介质层207的电场应力，大幅提高器件的长期使用可靠性。
且屏蔽区206的顶部与栅极沟槽的底部和阱区203的底部接触，而阱区203表面内的第一源区204和第二源区205与源极金属层210电连接，所以，屏蔽区206通过阱区203和第二源区205与源极金属层210电连接(短接)，可提高器件的开关频率，降低开关损耗。
由于屏蔽区206在栅极沟槽底部纵向间隔设置，且其与源极金属层210短接，沟槽栅极(包括栅极沟槽、栅极介质层207和栅极208)在有屏蔽区206的部分，沟槽栅极两侧不会形成沟道，不会有沟道电流(导通电流)的产生，而沟槽栅极在没有屏蔽区206的部分，沟槽栅极两侧会形成沟道，形成沟道电流(导通电流)，即可以将电场保护区域和导电区域进行分离设置，达到既保证导通电流又能有效降低阻断态下栅极介质层207的电场应力的良好折中关系。且屏蔽区206的形成过程不会影响到导电区域(沟槽表面)的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
且由于屏蔽区206的顶部与栅极沟槽的底部和阱区203的底部接触，克服了现有技术中由于屏蔽区不得接触阱区，栅极沟槽需要一定的刻蚀深度导致的工艺困难问题。
层间介质层209，位于栅极208上方，层间介质层209将栅极208与源极金属层210隔离开。
源极金属层210，位于源区(包括第一源区204和第二源区205)上方且同时与第一源区204和第二源区205形成电连接。源极金属层210可以为铝、镍等与SiC具有低接触电阻率的金属。
漏极金属层211，位于衬底201下方并与衬底201形成欧姆接触，漏极金属可以为铝、镍等与SiC具有低接触电阻率的金属。
需要说明的是，本实施例中的碳化硅器件为沟槽栅碳化硅MOSFET器件。
对应地，第一导电类型和第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。
本实施例提供一种碳化硅器件的元胞结构200，通过在栅极沟槽底部形成纵向间隔设置的第二导电类型的屏蔽区206，可大幅降低阻断状态下器件的栅极介质层207的电场应力，大幅提高器件的长期使用可靠性；屏蔽区206与阱区203的底部接触，可以通过阱区203和源区与源极金属层210电连接，提高器件的开关频率，降低开关损耗；纵向间隔设置的屏蔽区206，可以将导电区域与电场保护区域进行分离设置，屏蔽区206的形成过程不会影响到导电区域的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
实施例二
如图4和图5所示，本公开实施例提供一种碳化硅器件的元胞结构300，包括衬底301、漂移层302、阱区303、源区(图中未标注)、屏蔽区306、栅极沟槽(图中未标注)、栅极介质层307、栅极308、层间介质层309、源极金属层310和漏极金属层311。
需要说明的是，本实施例中，以下的“横向”是指“X方向”，“纵向”是指“Y方向”，“宽度”是指“X方向的宽度”，深度是指“Z方向的深度”。
需要说明的是，为了在图4中清楚显示源区(图中未标注)、屏蔽区306、栅极沟槽(图中未标注)、栅极介质层307和栅极308的形状和位置，所以图4中并未示出衬底301、漂移层302、阱区303、层间介质层309、源极金属层310和漏极金属层311。但是结合图5是可以理解到衬底301、漂移层302、阱区303、层间介质层309、源极金属层310和漏极金属层311的形状和位置。
示例性地，衬底301为第一导电类型的碳化硅衬底301。衬底301的厚度较厚，离子掺杂浓度较高，离子掺杂浓度大于1E18cm -3。
漂移层302为第一导电类型的漂移层302，位于衬底301上方，离子掺杂浓度约为1E14至5E16cm -3，漂移层302的离子掺杂浓度与厚度具体需要根据芯片耐压来优化。
阱区303为第二导电类型的阱区303，多个阱区303间隔设置于漂移层302表面内，阱区303的上表面与漂移层302的上表面相平齐。阱区303的离子掺杂浓度为1E16至1E18cm -3，深度为0.3至1.5μm。
源区位于阱区303表面内，本实施例中，源区包括第一源区304和第二源区305。
第一源区304为第一导电类型的源区，第一源区304位于阱区303表面内，第一源区304的上表面与阱区303的上表面相平齐，第一源区304的两端与两侧的栅极沟槽的侧壁接触。第一源区304的宽度等于阱区303的宽度，第一源区304的深度小于阱区303的深度，第一源区304的离子掺杂浓度大于1E19cm -3，深度为0.2至0.5μm。
第二源区305为第二导电类型的源区，第二源区305纵向(Y方向)间隔设置于第一源区304内，第二源区305的上表面与阱区303的上表面相平齐，第二源区305不与栅极沟槽的侧壁接触。第二源区305的宽度小于第一源区304的宽度，第二源区305的深度大于第一源区304的深度，但小于阱区303的深度，第二源区305的离子掺杂浓度大于阱区303的离子掺杂浓度，第二源区305的离子掺杂浓度大于5E18cm -3，深度为0.3至1.5μm。
栅极沟槽(图中未标注)位于相邻两个阱区303之间，栅极沟槽的侧壁同时与阱区303和源区中的第一源区304接触。栅极沟槽的深度大于阱区303的深度，栅极沟槽的深度为0.4至2.0μm，栅极沟槽的宽度为0.15至3.0μm。
栅极介质层307均匀地设置于栅极沟槽的侧壁和底部，栅极介质层307可以为氧化层，厚度约30nm至1000nm，其中沟槽底部的介质层厚度可以高于侧壁介质层的厚度，以提高 栅极介质层307底部的耐压能力。
栅极308为第一导电类型的多晶硅栅极，设置于栅极沟槽内，其离子掺杂浓度大于1E18cm -3。
屏蔽区306为第二导电类型的掺杂区，屏蔽区306位于漂移层302内且纵向(Y方向)间隔设置于栅极沟槽下方，屏蔽区306的顶部与栅极沟槽的底部和阱区303的底部接触，屏蔽区306的离子掺杂浓度大于1E15cm -3，且屏蔽区306的结深(深度)为0.2至5μm。
本实施例中，相邻两个栅极沟槽下方的屏蔽区306交错设置。
屏蔽区306可大幅降低阻断状态下器件的栅极介质层307的电场应力，大幅提高器件的长期使用可靠性。
且屏蔽区306的顶部与栅极沟槽的底部和阱区303的底部接触，而阱区303表面内的第一源区304和第二源区305与源极金属层310电连接，所以，屏蔽区306通过阱区303和第二源区305与源极金属层310电连接(短接)，可提高器件的开关频率，降低开关损耗。
由于屏蔽区306在栅极沟槽底部纵向间隔设置，且其与源极金属层310短接，沟槽栅极(包括栅极沟槽、栅极介质层307和栅极308)在有屏蔽区306的部分，沟槽栅极两侧不会形成沟道，不会有沟道电流(导通电流)的产生，而沟槽栅极在没有屏蔽区306的部分，沟槽栅极两侧会形成沟道，形成沟道电流(导通电流)，即可以将电场保护区域和导电区域进行分离设置，达到既保证导通电流又能有效降低阻断态下栅极介质层307的电场应力的良好折中关系。且屏蔽区306的形成过程不会影响到导电区域(沟槽表面)的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
相对于实施例二中的对齐设置的屏蔽区，本实施例中交错设置的屏蔽区306，使得整个碳化硅器件中电场保护区域和导电区域交错设置，利用屏蔽区306向四周屏蔽电场，进一步降低栅极介质层307的电场应力，同时，增大了导电区域的面积，实现更好的导通电流与阻断电压的折中关系。
且由于屏蔽区306的顶部与栅极沟槽的底部和阱区303的底部接触，克服了现有技术中由于屏蔽区不得接触阱区，栅极沟槽需要一定的刻蚀深度导致的工艺困难问题。
层间介质层309，位于栅极308上方，层间介质层309将栅极308与源极金属层310隔离开。
源极金属层310，位于源区(包括第一源区304和第二源区305)上方且同时与第一源区304和第二源区305形成电连接。源极金属层310可以为铝、镍等与SiC具有低接触电阻率的金属。
漏极金属层311，位于衬底301下方并与衬底301形成欧姆接触，漏极金属可以为铝、 镍等与SiC具有低接触电阻率的金属。
需要说明的是，本实施例中的碳化硅器件为沟槽栅碳化硅MOSFET器件。
对应地，第一导电类型和第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。
本实施例提供一种碳化硅器件的元胞结构300，通过在栅极沟槽底部形成纵向间隔设置的第二导电类型的屏蔽区306，可大幅降低阻断状态下器件的栅极介质层307的电场应力，大幅提高器件的长期使用可靠性；屏蔽区306与阱区303的底部接触，可以通过阱区303和源区与源极金属层310电连接，提高器件的开关频率，降低开关损耗；纵向间隔设置的屏蔽区306，可以将导电区域与电场保护区域进行分离设置，屏蔽区306的形成过程不会影响到导电区域的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
实施例三
如图6和图7所示，本公开实施例提供一种碳化硅器件的元胞结构400，包括衬底401、漂移层402、阱区403、源区(图中未标注)、屏蔽区406、存储区412、栅极沟槽(图中未标注)、栅极介质层407、栅极408、层间介质层409、源极金属层410和漏极金属层411。
需要说明的是，本实施例中，以下的“横向”是指“X方向”，“纵向”是指“Y方向”，“宽度”是指“X方向的宽度”，深度是指“Z方向的深度”。
需要说明的是，为了在图6中清楚显示源区(图中未标注)、屏蔽区406、栅极沟槽(图中未标注)、栅极介质层407和栅极408的形状和位置，所以图6中并未示出衬底401、漂移层402、阱区403、层间介质层409、源极金属层410和漏极金属层411。但是结合图7是可以理解到衬底401、漂移层402、阱区403、层间介质层409、源极金属层410和漏极金属层411的形状和位置。
示例性地，衬底401为第一导电类型的碳化硅衬底401。衬底401的厚度较厚，离子掺杂浓度较高，离子掺杂浓度大于1E18cm -3。
漂移层402为第一导电类型的漂移层402，位于衬底401上方，离子掺杂浓度约为1E14至5E16cm -3，漂移层402的离子掺杂浓度与厚度具体需要根据芯片耐压来优化。
阱区403为第二导电类型的阱区403，多个阱区403间隔设置于漂移层402表面内，阱区403的上表面与漂移层402的上表面相平齐。阱区403的离子掺杂浓度为1E16至1E18cm -3，深度为0.3至1.5μm。
源区位于阱区403表面内，本实施例中，源区包括第一源区404和第二源区405。
第一源区404为第一导电类型的源区，第一源区404位于阱区403表面内，第一源区 404的上表面与阱区403的上表面相平齐，第一源区404的两端与两侧的栅极沟槽的侧壁接触。第一源区404的宽度等于阱区403的宽度，第一源区404的深度小于阱区403的深度，第一源区404的离子掺杂浓度大于1E19cm -3，深度为0.2至0.5μm。
第二源区405为第二导电类型的源区，第二源区405纵向(Y方向)间隔设置于第一源区404内，第二源区405的上表面与阱区403的上表面相平齐，第二源区405不与栅极沟槽的侧壁接触。第二源区405的宽度小于第一源区404的宽度，第二源区405的深度大于第一源区404的深度，但小于阱区403的深度，第二源区405的离子掺杂浓度大于阱区403的离子掺杂浓度，第二源区405的离子掺杂浓度大于5E18cm -3，深度为0.3至1.5μm。
栅极沟槽(图中未标注)位于相邻两个阱区403之间，栅极沟槽的侧壁同时与阱区403和源区中的第一源区404接触。栅极沟槽的深度大于阱区403的深度，栅极沟槽的深度为0.4至2.0μm，栅极沟槽的宽度为0.15至3.0μm。
栅极介质层407均匀地设置于栅极沟槽的侧壁和底部，栅极介质层407可以为氧化层，厚度约30nm至1000nm，其中沟槽底部的介质层厚度可以高于侧壁介质层的厚度，以提高栅极介质层407底部的耐压能力。
栅极408为第一导电类型的多晶硅栅极，设置于栅极沟槽内，其离子掺杂浓度大于1E18cm -3。
屏蔽区406为第二导电类型的掺杂区，屏蔽区406位于漂移层402内且纵向(Y方向)间隔设置于栅极沟槽下方，屏蔽区406的顶部与栅极沟槽的底部和阱区403的底部接触，屏蔽区406的离子掺杂浓度大于1E15cm -3，且屏蔽区406的结深(深度)为0.2至5μm。
本实施例中，相邻两个栅极沟槽下方的屏蔽区406对齐设置或交错设置(交错设置的结构图中未示出)。
屏蔽区406可大幅降低阻断状态下器件的栅极介质层407的电场应力，大幅提高器件的长期使用可靠性。
且屏蔽区406的顶部与栅极沟槽的底部和阱区403的底部接触，而阱区403表面内的第一源区404和第二源区405与源极金属层410电连接，所以，屏蔽区406通过阱区403和第二源区405与源极金属层410电连接(短接)，可提高器件的开关频率，降低开关损耗。
由于屏蔽区406在栅极沟槽底部纵向间隔设置，且其与源极金属层410短接，沟槽栅极(包括栅极沟槽、栅极介质层407和栅极408)在有屏蔽区406的部分，沟槽栅极两侧不会形成沟道，不会有沟道电流(导通电流)的产生，而沟槽栅极在没有屏蔽区406的部分，沟槽栅极两侧会形成沟道，形成沟道电流(导通电流)，即可以将电场保护区域和导电区域进行分离设置，达到既保证导通电流又能有效降低阻断态下栅极介质层407的电场 应力的良好折中关系。且屏蔽区406的形成过程不会影响到导电区域(沟槽表面)的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
且由于屏蔽区406的顶部与栅极沟槽的底部和阱区403的底部接触，克服了现有技术中由于屏蔽区不得接触阱区，栅极沟槽需要一定的刻蚀深度导致的工艺困难问题。
存储区412为第一导电类型的掺杂区，存储区412同样位于栅极沟槽下方，存储区412与屏蔽区406在纵向(Y方向)上间隔交替设置，存储区412不与屏蔽区406接触，存储区412的顶部与栅极沟槽的底部和阱区403的底部接触，存储区412的离子掺杂浓度大于衬底201的离子掺杂浓度。
存储区412可以增强导电区域的导通电流能力，基于存储区412的存在，导通区域的区域尺寸可以进一步减小，也就是说，屏蔽区406之间的纵向距离可以进一步减小，也不会影响导通区域的导通电流能力。
层间介质层409，位于栅极408上方，层间介质层409将栅极408与源极金属层410隔离开。
源极金属层410，位于源区(包括第一源区404和第二源区405)上方且同时与第一源区404和第二源区405形成电连接。源极金属层410可以为铝、镍等与SiC具有低接触电阻率的金属。
漏极金属层411，位于衬底401下方并与衬底401形成欧姆接触，漏极金属可以为铝、镍等与SiC具有低接触电阻率的金属。
需要说明的是，本实施例中的碳化硅器件为沟槽栅碳化硅MOSFET器件。
对应地，第一导电类型和第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。
本实施例提供一种碳化硅器件的元胞结构400，通过在栅极沟槽底部形成纵向间隔设置的第二导电类型的屏蔽区406，可大幅降低阻断状态下器件的栅极介质层407的电场应力，大幅提高器件的长期使用可靠性；屏蔽区406与阱区403的底部接触，可以通过阱区403和源区与源极金属层410电连接，提高器件的开关频率，降低开关损耗；纵向间隔设置的屏蔽区406，可以将导电区域与电场保护区域进行分离设置，屏蔽区406的形成过程不会影响到导电区域的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
实施例四
如图8和图9所示，本公开实施例提供一种碳化硅器件的元胞结构500，包括衬底501、漂移层502、阱区503、源区(图中未标注)、屏蔽区506、栅极沟槽(图中未标注)、栅 极介质层507、栅极508、层间介质层509、源极金属层510和漏极金属层511。
需要说明的是，本实施例中，以下的“横向”是指“X方向”，“纵向”是指“Y方向”，“宽度”是指“X方向的宽度”，深度是指“Z方向的深度”。
需要说明的是，为了在图8中清楚显示源区(图中未标注)、屏蔽区506、栅极沟槽(图中未标注)、栅极介质层507和栅极508的形状和位置，所以图8中并未示出衬底501、漂移层502、阱区503、层间介质层509、源极金属层510和漏极金属层511。但是结合图9是可以理解到衬底501、漂移层502、阱区503、层间介质层509、源极金属层510和漏极金属层511的形状和位置。
示例性地，衬底501为第一导电类型的碳化硅衬底501。衬底501的厚度较厚，离子掺杂浓度较高，离子掺杂浓度大于1E18cm -3。
漂移层502为第一导电类型的漂移层502，位于衬底501上方，离子掺杂浓度约为1E14至5E16cm -3，漂移层502的离子掺杂浓度与厚度具体需要根据芯片耐压来优化。
阱区503为第二导电类型的阱区503，多个阱区503间隔设置于漂移层502表面内，阱区503的上表面与漂移层502的上表面相平齐。阱区503的离子掺杂浓度为1E16至1E18cm -3，深度为0.3至1.5μm。
源区位于阱区503表面内，本实施例中，源区包括第一源区504和第二源区505，第一源区504和第二源区505在纵向(Y方向)上交替设置。
第一源区504为第一导电类型的源区，第一源区504的上表面与阱区503的上表面相平齐，第一源区504的两端与两侧的栅极沟槽的侧壁接触。第一源区504的宽度等于阱区503的宽度，第一源区504的深度小于阱区503的深度，第一源区504的离子掺杂浓度大于1E19cm -3，深度为0.2至0.5μm。
第二源区505为第二导电类型的源区，第二源区505的上表面与阱区503的上表面相平齐，第二源区505的两端与两侧的栅极沟槽的侧壁接触。第二源区505的宽度等于第一源区504的宽度，第二源区505的深度大于第一源区504的深度，但小于阱区503的深度，第二源区505的离子掺杂浓度大于阱区503的离子掺杂浓度，第二源区505的离子掺杂浓度大于5E18cm -3，深度为0.3至1.5μm。
本实施例中，碳化硅器件是体二极管增强结构的碳化硅器件。其体二极管(图中未标出)电流导通电流较高，器件性能较好。
栅极沟槽(图中未标注)位于相邻两个阱区503之间，栅极沟槽的侧壁同时与阱区503和源区中的第一源区504接触。栅极沟槽的深度大于阱区503的深度，栅极沟槽的深度为0.4至2.0μm，栅极沟槽的宽度为0.15至3.0μm。
栅极介质层507均匀地设置于栅极沟槽的侧壁和底部，栅极介质层507为氧化层，厚 度约30nm至1000nm，其中沟槽底部的介质层厚度可以高于侧壁介质层的厚度，以提高栅极介质层507底部的耐压能力。
栅极508为第一导电类型的多晶硅栅极，设置于栅极沟槽内，其离子掺杂浓度大于1E18cm -3。
屏蔽区506为第二导电类型的掺杂区，屏蔽区506位于漂移层502内且纵向(Y方向)间隔设置于栅极沟槽下方，屏蔽区506的顶部与栅极沟槽的底部和阱区503的底部接触，屏蔽区506的离子掺杂浓度大于1E15cm -3，且屏蔽区506的结深(深度)为0.2至5μm。
本实施例中，相邻两个栅极沟槽下方的屏蔽区506对齐设置，且屏蔽区506与第二源区505横向(X方向)对齐设置。
屏蔽区506可大幅降低阻断状态下器件的栅极介质层507的电场应力，大幅提高器件的长期使用可靠性。
且屏蔽区506的顶部与栅极沟槽的底部和阱区503的底部接触，而阱区503表面内的第一源区504和第二源区505与源极金属层510电连接，所以，屏蔽区506通过阱区503和第二源区505与源极金属层510电连接(短接)，可提高器件的开关频率，降低开关损耗。
由于屏蔽区506在栅极沟槽底部纵向间隔设置，且其与源极金属层510短接，沟槽栅极(包括栅极沟槽、栅极介质层507和栅极508)在有屏蔽区506的部分，沟槽栅极两侧不会形成沟道，不会有沟道电流(导通电流)的产生，而沟槽栅极在没有屏蔽区506的部分，沟槽栅极两侧会形成沟道，形成沟道电流(导通电流)，即可以将电场保护区域和导电区域进行分离设置，达到既保证导通电流又能有效降低阻断态下栅极介质层507的电场应力的良好折中关系。且屏蔽区506的形成过程不会影响到导电区域(沟槽表面)的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
且由于屏蔽区506的顶部与栅极沟槽的底部和阱区503的底部接触，克服了现有技术中由于屏蔽区不得接触阱区，栅极沟槽需要一定的刻蚀深度导致的工艺困难问题。
层间介质层509，位于栅极508上方，层间介质层509将栅极508与源极金属层510隔离开。
源极金属层510，位于源区(包括第一源区504和第二源区505)上方且同时与第一源区504和第二源区505形成电连接。源极金属层510可以为铝、镍等与SiC具有低接触电阻率的金属。
漏极金属层511，位于衬底501下方并与衬底501形成欧姆接触，漏极金属可以为铝、镍等与SiC具有低接触电阻率的金属。
需要说明的是，本实施例中的碳化硅器件为沟槽栅碳化硅MOSFET器件。
对应地，第一导电类型和第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。
本实施例提供一种碳化硅器件的元胞结构500，通过在栅极沟槽底部形成纵向间隔设置的第二导电类型的屏蔽区506，可大幅降低阻断状态下器件的栅极介质层507的电场应力，大幅提高器件的长期使用可靠性；屏蔽区506与阱区503的底部接触，可以通过阱区503和源区与源极金属层510电连接，提高器件的开关频率，降低开关损耗；纵向间隔设置的屏蔽区506，可以将导电区域与电场保护区域进行分离设置，屏蔽区506的形成过程不会影响到导电区域的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
实施例五
在实施例一的基础上，本实施例提供一种碳化硅器件的元胞结构200的制备方法。图10是本公开实施例示出的一种碳化硅器件的元胞结构200的制备方法流程示意图。图11-图15是本公开实施例示出的一种碳化硅器件的元胞结构200的制备方法的相关步骤形成的剖面结构示意图。下面，参照图10和图11-图15来描述本公开实施例提出的碳化硅器件的元胞结构200的制备方法一个示例性方法的详细步骤。
如图10所示，本实施例的碳化硅器件的元胞结构200的制备方法，包括如下步骤：
步骤S201：提供第一导电类型碳化硅衬底201。
衬底201的厚度较厚，离子掺杂浓度较高，离子掺杂浓度大于1E18cm -3。
步骤S202：如图11所示，在衬底201上方形成第一导电类型漂移层202。
具体地，漂移层202为均匀掺杂的碳化硅层，离子掺杂浓度约为1E14至5E16cm -3，漂移层202的离子掺杂浓度与厚度具体需要根据芯片耐压来优化。
步骤S203：在漂移层202表面内形成多个间隔设置的第二导电类型阱区203。
具体的，在漂移层202表面内注入第二导电类型离子，以形成多个间隔设置的第二导电类型阱区203。阱区203的上表面与漂移层202的上表面相平齐。阱区203的离子掺杂浓度为1E16至1E18cm -3，深度为0.3至1.5μm。
步骤S204：在阱区203表面内形成源区。
本实施例中，源区包括第一源区204和第二源区205。
步骤S204具体包括以下步骤：
在阱区203表面内形成第一导电类型第一源区204；其中，第一源区204的两端分别与两侧的栅极沟槽的侧壁接触；
在第一源区204内形成纵向间隔设置的第二导电类型第二源区205；其中，第二源区 205不与栅极沟槽的侧壁接触。
具体的，通过离子注入，在阱区203内注入第一导电类型离子，以在阱区203内形成第一导电类型第一源区204，采用光刻工艺，通过光刻胶选择性屏蔽第一源区204的部分表面，通过离子注入，在第一源区204内注入第二导电类型离子，以在第一源区204内形成第二导电类型第二源区205。
第一源区204为第一导电类型的源区，第一源区204位于阱区203表面内，第一源区204的上表面与阱区203的上表面相平齐，第一源区204的两端与两侧的栅极沟槽的侧壁接触。第一源区204的宽度等于阱区203的宽度，第一源区204的深度小于阱区203的深度，第一源区204的离子掺杂浓度大于1E19cm -3，深度为0.2至0.5μm。
第二源区205为第二导电类型的源区，第二源区205纵向(Y方向)间隔设置于第一源区204内，第二源区205的上表面与阱区203的上表面相平齐，第二源区205不与栅极沟槽的侧壁接触。第二源区205的宽度小于第一源区204的宽度，第二源区205的深度大于第一源区204的深度，但小于阱区203的深度，第二源区205的离子掺杂浓度大于阱区203的离子掺杂浓度，第二源区205的离子掺杂浓度大于5E18cm -3，深度为0.3至1.5μm。
步骤S205：在相邻两个阱区203之间形成栅极沟槽；其中，栅极沟槽的侧壁同时与阱区203和源区接触，栅极沟槽的深度大于阱区203的深度。
具体的，刻蚀相邻两个阱区203之间区域，以在相邻两个阱区203之间形成栅极沟槽。其中，栅极沟槽的侧壁同时与阱区203和源区中的第一源区204接触。栅极沟槽的深度大于阱区203的深度，栅极沟槽的深度为0.4至2.0μm，栅极沟槽的宽度为0.15至3.0μm。
需要说明的是，上述形成阱区203、第一源区204、第二源区205和栅极沟槽的步骤也可以是：形成整面的阱区203→形成第一源区204和第二源区205→刻蚀形成栅极沟槽。
步骤S206：如图12所示，通过倾斜离子注入的方式在漂移层202内于栅极沟槽下方形成纵向(Y方向)间隔设置的第二导电类型屏蔽区206；其中，屏蔽区206的顶部与栅极沟槽的底部和阱区203的底部接触。
采用光刻工艺，通过光刻胶选择性屏蔽源区(包括第一源区204和第二源区205)的上表面和各个栅极沟槽的部分底部和侧壁，通过倾斜离子注入的方式，不仅可以在沟槽底部的漂移层202内注入第二导电类型的离子，也可以在未被光刻胶覆盖的沟槽靠近底部的侧壁旁的漂移层202内注入第二导电类型的离子，然后通过高温杂质激活退火工艺，即可在栅极沟槽下方形成纵向间隔设置的第二导电类型屏蔽区206。屏蔽区206的顶部与栅极沟槽的底部和阱区203的底部接触。
本实施例中，相邻两个栅极沟槽下方的屏蔽区206对齐设置。
步骤S207：如图13所示，在栅极沟槽的侧壁和底部形成栅极介质层207。
具体的，步骤S207包括以下步骤：
S207a：对漂移层202表面、栅极沟槽的侧壁和底部进行牺牲氧化处理；
S207b：在漂移层202上方、栅极沟槽的侧壁和底部形成栅极介质层207；
S207c：刻蚀掉漂移层202上方的栅极介质层207。
其中，牺牲氧化处理包括以下步骤：
(a)对漂移层202表面进行热氧化以形成牺牲氧化层(图中未示出)；其中，牺牲氧化层的厚度为10至20nm；
(b)通过湿法刻蚀将牺牲氧化层去除。
栅极介质层207为氧化层，与牺牲氧化层类似，都是在高温(如1300℃)氧气氛围内进行热氧化形成。栅极介质层207厚度约30nm至1000nm。沟槽底部的介质层厚度可以高于侧壁介质层的厚度，以提高栅极介质层207底部的耐压能力。
屏蔽区206可大幅降低阻断状态下器件的栅极介质层207的电场应力，大幅提高器件的长期使用可靠性。
步骤S208：在栅极沟槽内填充多晶硅，以形成栅极208。
其中，填充的多晶硅为第一导电类型的高浓度掺杂的多晶硅，离子掺杂浓度大于1E18cm -3。
步骤S209：如图14所示，在栅极208上方形成覆盖栅极208的层间介质层209。
具体的，先在漂移层202上方形成整面的层间介质层209，然后通过刻蚀，只留下栅极208上方的层间介质层209。
步骤S210：在源区上方形成与源区电连接的源极金属层210；其中，栅极208通过层间介质层209与源极金属层210隔离，屏蔽区206通过阱区203和源区与源极金属层210电连接。
通过金属化工艺，在第一源区204和第二源区205上方形成同时与第一源区204和第二源区205电连接的源极金属层210。
由于屏蔽区206的顶部与栅极沟槽的底部和阱区203的底部接触，而阱区203表面内的第一源区204和第二源区205与源极金属层210电连接，所以，屏蔽区206通过阱区203和第二源区205与源极金属层210电连接(短接)，可提高器件的开关频率，降低开关损耗。
由于屏蔽区206在栅极沟槽底部纵向间隔设置，且其与源极金属层210短接，沟槽栅极(包括栅极沟槽、栅极介质层207和栅极208)在有屏蔽区206的部分，沟槽栅极两侧不会形成沟道，不会有沟道电流(导通电流)的产生，而沟槽栅极在没有屏蔽区206的部分，沟槽栅极两侧会形成沟道，形成沟道电流(导通电流)，即可以将电场保护区域和导 电区域进行分离设置，达到既保证导通电流又能有效降低阻断态下栅极介质层207的电场应力的良好折中关系。且屏蔽区206的形成过程不会影响到导电区域(沟槽表面)的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
且由于屏蔽区206的顶部与栅极沟槽的底部和阱区203的底部接触，克服了现有技术中由于屏蔽区不得接触阱区，栅极沟槽需要一定的刻蚀深度导致的工艺困难问题。
源极金属层210可以为铝、镍等与SiC具有低接触电阻率的金属。
步骤S211：如图15所示，在衬底201下方形成与衬底201欧姆接触的漏极金属层211。
具体的，通过金属化工艺，在衬底201下方形成与衬底201欧姆接触的漏极金属层211，漏极金属层211可以为铝、镍等与SiC具有低接触电阻率的金属。
整个制备工艺过程制程简单，可制造性强且制造成本较低。
对应地，第一导电类型和第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。
本实施例提供一种碳化硅器件的元胞结构200的制备方法，通过在栅极沟槽底部形成纵向间隔设置的第二导电类型的屏蔽区206，可大幅降低阻断状态下器件的栅极介质层207的电场应力，大幅提高器件的长期使用可靠性；屏蔽区206与阱区203的底部接触，可以通过阱区203和源区与源极金属层210电连接，提高器件的开关频率，降低开关损耗；纵向间隔设置的屏蔽区206，可以将导电区域与电场保护区域进行分离设置，屏蔽区206的形成过程不会影响到导电区域的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。且制备工艺制程简单，可制造性强且制造成本较低。
实施例六
在实施例二的基础上，本实施例提供一种碳化硅器件的元胞结构300的制备方法。
碳化硅器件的元胞结构300的制备方法与实施例五中碳化硅器件的元胞结构200的制备方法相似，区别仅在于屏蔽区306的位置不同，所以此处不再赘述。
实施例七
在实施例三的基础上，本实施例提供一种碳化硅器件的元胞结构400的制备方法。图16是本公开实施例示出的一种碳化硅器件的元胞结构400的制备方法流程示意图。
如图16所示，本实施例的碳化硅器件的元胞结构400的制备方法，包括如下步骤：
步骤S401：提供第一导电类型碳化硅衬底401。
衬底401的厚度较厚，离子掺杂浓度较高，离子掺杂浓度大于1E18cm -3。
步骤S402：在衬底401上方形成第一导电类型漂移层402。
具体地，漂移层402为均匀掺杂的碳化硅层，离子掺杂浓度约为1E14至5E16cm -3，漂移层402的离子掺杂浓度与厚度具体需要根据芯片耐压来优化。
步骤S403：在漂移层402表面内形成多个间隔设置的第二导电类型阱区403。
具体的，在漂移层402表面内注入第二导电类型离子，以形成多个间隔设置的第二导电类型阱区403。阱区403的上表面与漂移层402的上表面相平齐。阱区403的离子掺杂浓度为1E16至1E18cm -3，深度为0.3至1.5μm。
步骤S404：在阱区403表面内形成源区。
本实施例中，源区包括第一导电类型第一源区404，以及纵向间隔设置于第一源区404内的第二导电类型第二源区405。
步骤S404具体包括以下步骤：
在阱区403表面内形成第一导电类型第一源区404；其中，第一源区404的两端分别与两侧的栅极沟槽的侧壁接触；
在第一源区404内形成纵向间隔设置的第二导电类型第二源区405；其中，第二源区405不与栅极沟槽的侧壁接触。
具体的，通过离子注入，在阱区403内注入第一导电类型离子，以在阱区403内形成第一导电类型第一源区404，采用光刻工艺，通过光刻胶选择性屏蔽第一源区404的部分表面，通过离子注入，在第一源区404内注入第二导电类型离子，以在第一源区404内形成第二导电类型第二源区405。
第一源区404为第一导电类型的源区，第一源区404位于阱区403表面内，第一源区404的上表面与阱区403的上表面相平齐，第一源区404的两端与两侧的栅极沟槽的侧壁接触。第一源区404的宽度等于阱区403的宽度，第一源区404的深度小于阱区403的深度，第一源区404的离子掺杂浓度大于1E19cm -3，深度为0.2至0.5μm。
第二源区405为第二导电类型的源区，第二源区405纵向(Y方向)间隔设置于第一源区404内，第二源区405的上表面与阱区403的上表面相平齐，第二源区405不与栅极沟槽的侧壁接触。第二源区405的宽度小于第一源区404的宽度，第二源区405的深度大于第一源区404的深度，但小于阱区403的深度，第二源区405的离子掺杂浓度大于阱区403的离子掺杂浓度，第二源区405的离子掺杂浓度大于5E18cm -3，深度为0.3至1.5μm。
步骤S405：在相邻两个阱区403之间形成栅极沟槽；其中，栅极沟槽的侧壁同时与阱区403和源区接触，栅极沟槽的深度大于阱区403的深度。
具体的，刻蚀相邻两个阱区403之间区域，以在相邻两个阱区403之间形成栅极沟槽。其中，栅极沟槽的侧壁同时与阱区403和源区中的第一源区404接触。栅极沟槽的深度大于阱区403的深度，栅极沟槽的深度为0.4至2.0μm，栅极沟槽的宽度为0.15至3.0μm。
需要说明的是，上述形成阱区403、第一源区404、第二源区405和栅极沟槽的步骤也可以是：形成整面的阱区403→形成第一源区404和第二源区405→刻蚀形成栅极沟槽。
步骤S406：通过倾斜离子注入的方式在漂移层402内于栅极沟槽下方形成纵向(Y方向)间隔设置的第二导电类型屏蔽区406；其中，屏蔽区406的顶部与栅极沟槽的底部和阱区403的底部接触。
采用光刻工艺，通过光刻胶选择性屏蔽源区(包括第一源区404和第二源区405)的上表面和各个栅极沟槽的部分底部和侧壁，通过倾斜离子注入的方式，不仅可以在沟槽底部的漂移层402内注入离子，也可以在未被光刻胶覆盖的沟槽靠近底部的侧壁旁的漂移层402内注入离子，然后通过高温杂质激活退火工艺，即可在栅极沟槽下方形成纵向间隔设置的第二导电类型屏蔽区406。屏蔽区406的顶部与栅极沟槽的底部和阱区403的底部接触。
本实施例中，相邻两个栅极沟槽下方的屏蔽区406对齐设置或交错设置。
步骤S407：在栅极沟槽下方形成第一导电类型存储区412；其中，存储区412和屏蔽区406在纵向上间隔交替设置，存储区412的顶部与栅极沟槽的底部和阱区403的底部接触。
采用光刻工艺，通过光刻胶选择性屏蔽源区(包括第一源区404和第二源区405)的上表面和屏蔽区406，通过倾斜离子注入的方式，不仅可以在沟槽底部的漂移层402内注入第一导电类型的离子，也可以在未被光刻胶覆盖的沟槽靠近底部的侧壁旁的漂移层402内注入第一导电类型的离子，然后通过高温杂质激活退火工艺，即可在栅极沟槽下方形成第一导电类型存储区412。存储区412和屏蔽区406在纵向上间隔交替设置，存储区412不与屏蔽区406接触，存储区412的顶部与栅极沟槽的底部和阱区403的底部接触。
存储区412可以增强导电区域的导通电流能力，基于存储区412的存在，导通区域的区域尺寸可以进一步减小，也就是说，屏蔽区406之间的纵向距离可以进一步减小，也不会影响导通区域的导通电流能力。
步骤S408：在栅极沟槽的侧壁和底部形成栅极介质层407。
具体的，步骤S408包括以下步骤：
S408a：对漂移层402表面、栅极沟槽的侧壁和底部进行牺牲氧化处理；
S408b：在漂移层402上方、栅极沟槽的侧壁和底部形成栅极介质层407；
S408c：刻蚀掉漂移层402上方的栅极介质层407。
其中，牺牲氧化处理包括以下步骤：
(a)对漂移层402表面进行热氧化以形成牺牲氧化层(图中未示出)；其中，牺牲氧化层的厚度为10至40nm；
(b)通过湿法刻蚀将牺牲氧化层去除。
栅极介质层407为氧化层，与牺牲氧化层类似，都是在高温(如1300℃)氧气氛围内进行热氧化形成。栅极介质层407厚度约30nm至1000nm。沟槽底部的介质层厚度可以高于侧壁介质层的厚度，以提高栅极介质层407底部的耐压能力。
屏蔽区406可大幅降低阻断状态下器件的栅极介质层407的电场应力，大幅提高器件的长期使用可靠性。
步骤S409：在栅极沟槽内填充多晶硅，以形成栅极408。
其中，填充的多晶硅为第一导电类型的高浓度掺杂的多晶硅，离子掺杂浓度大于1E18cm -3。
步骤S410：在栅极408上方形成覆盖栅极408的层间介质层409。
具体的，先在漂移层402上方形成整面的层间介质层409，然后通过刻蚀，只留下栅极408上方的层间介质层409。
步骤S411：在源区上方形成与源区电连接的源极金属层410；其中，栅极408通过层间介质层409与源极金属层410隔离，屏蔽区406通过阱区403和源区与源极金属层410电连接。
通过金属化工艺，在第一源区404和第二源区405上方形成同时与第一源区404和第二源区405电连接的源极金属层410。
由于屏蔽区406的顶部与栅极沟槽的底部和阱区403的底部接触，而阱区403表面内的第一源区404和第二源区405与源极金属层410电连接，所以，屏蔽区406通过阱区403和第二源区405与源极金属层410电连接(短接)，可提高器件的开关频率，降低开关损耗。
由于屏蔽区406在栅极沟槽底部纵向间隔设置，且其与源极金属层410短接，沟槽栅极(包括栅极沟槽、栅极介质层407和栅极408)在有屏蔽区406的部分，沟槽栅极两侧不会形成沟道，不会有沟道电流(导通电流)的产生，而沟槽栅极在没有屏蔽区406的部分，沟槽栅极两侧会形成沟道，形成沟道电流(导通电流)，即可以将电场保护区域和导电区域进行分离设置，达到既保证导通电流又能有效降低阻断态下栅极介质层407的电场应力的良好折中关系。且屏蔽区406的形成过程不会影响到导电区域(沟槽表面)的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
且由于屏蔽区406的顶部与栅极沟槽的底部和阱区403的底部接触，克服了现有技术中由于屏蔽区不得接触阱区，栅极沟槽需要一定的刻蚀深度导致的工艺困难问题。
源极金属层410可以为铝、镍等与SiC具有低接触电阻率的金属。
步骤S412：在衬底401下方形成与衬底401欧姆接触的漏极金属层411。
具体的，通过金属化工艺，在衬底401下方形成与衬底401欧姆接触的漏极金属层411，漏极金属层411可以为铝、镍等与SiC具有低接触电阻率的金属。
整个制备工艺过程制程简单，可制造性强且制造成本较低。
对应地，第一导电类型和第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。
本实施例提供一种碳化硅器件的元胞结构400的制备方法，通过在栅极沟槽底部形成纵向间隔设置的第二导电类型的屏蔽区406，可大幅降低阻断状态下器件的栅极介质层407的电场应力，大幅提高器件的长期使用可靠性；屏蔽区406与阱区403的底部接触，可以通过阱区403和源区与源极金属层410电连接，提高器件的开关频率，降低开关损耗；纵向间隔设置的屏蔽区406，可以将导电区域与电场保护区域进行分离设置，屏蔽区406的形成过程不会影响到导电区域的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。且制备工艺制程简单，可制造性强且制造成本较低。
实施例八
在实施例四的基础上，本实施例提供一种碳化硅器件的元胞结构500的制备方法。图17是本公开实施例示出的一种碳化硅器件的元胞结构500的制备方法流程示意图。
如图17所示，本实施例的碳化硅器件的元胞结构500的制备方法，包括如下步骤：
步骤S501：提供第一导电类型碳化硅衬底501。
衬底501的厚度较厚，离子掺杂浓度较高，离子掺杂浓度大于1E18cm -3。
步骤S502：在衬底501上方形成第一导电类型漂移层502。
具体地，漂移层502为均匀掺杂的碳化硅层，离子掺杂浓度约为1E14至5E16cm -3，漂移层502的离子掺杂浓度与厚度具体需要根据芯片耐压来优化。
步骤S503：在漂移层502表面内形成多个间隔设置的第二导电类型阱区503。
具体的，在漂移层502表面内注入第二导电类型离子，以形成多个间隔设置的第二导电类型阱区503。阱区503的上表面与漂移层502的上表面相平齐。阱区503的离子掺杂浓度为1E16至1E18cm -3，深度为0.3至1.5μm。
步骤S504：在阱区503表面内形成源区。
本实施例中，源区包括在纵向上交替设置第一导电类型第一源区504和第二导电类型第二源区505。
具体的，依次在阱区503内选择性注入第一导电类型离子和第二导电类型离子，在阱区503表面内形成在纵向上交替设置第一导电类型第一源区504和第二导电类型第二源区505。
第一源区504为第一导电类型的源区，第一源区504的上表面与阱区503的上表面相平齐，第一源区504的两端与阱区503的两端对齐。第一源区504的宽度等于阱区503的宽度，第一源区504的深度小于阱区503的深度，第一源区504的离子掺杂浓度大于1E19cm -3，深度为0.2至0.5μm。
第二源区505为第二导电类型的源区，第二源区505的上表面与阱区503的上表面相平齐，第二源区505的两端与阱区503的两端对齐。第二源区505的宽度等于第一源区504的宽度，第二源区505的深度大于第一源区504的深度，但小于阱区503的深度，第二源区505的离子掺杂浓度大于阱区503的离子掺杂浓度，第二源区505的离子掺杂浓度大于5E18cm -3，深度为0.3至1.5μm。
本实施例中，形成的碳化硅器件是体二极管增强结构的碳化硅器件。其体二极管(图中未标出)电流导通电流较高，器件性能较好。
步骤S505：在相邻两个阱区503之间形成栅极沟槽；其中，栅极沟槽的侧壁同时与阱区503和源区接触，栅极沟槽的深度大于阱区503的深度。
具体的，刻蚀相邻两个阱区503之间区域，以在相邻两个阱区503之间形成栅极沟槽。其中，栅极沟槽的侧壁同时与阱区503、第一源区504和第二源区505接触。栅极沟槽的深度大于阱区503的深度，栅极沟槽的深度为0.4至2.0μm，栅极沟槽的宽度为0.15至3.0μm。
需要说明的是，上述形成阱区503、第一源区504、第二源区505和栅极沟槽的步骤也可以是：形成整面的阱区503→形成第一源区504和第二源区505→刻蚀形成栅极沟槽。
步骤S506：通过倾斜离子注入的方式在漂移层502内于栅极沟槽下方形成纵向(Y方向)间隔设置的第二导电类型屏蔽区506；其中，屏蔽区506的顶部与栅极沟槽的底部和阱区503的底部接触，屏蔽区506与第二源区505横向对齐设置。
采用光刻工艺，通过光刻胶选择性屏蔽源区(包括第一源区504和第二源区505)的上表面和各个栅极沟槽的部分底部和侧壁，通过倾斜离子注入的方式，不仅可以在沟槽底部的漂移层502内注入第二导电类型的离子，也可以在未被光刻胶覆盖的沟槽靠近底部的侧壁旁的漂移层502内注入第二导电类型的离子，然后通过高温杂质激活退火工艺，即可在栅极沟槽下方形成纵向间隔设置的第二导电类型屏蔽区506。屏蔽区506的顶部与栅极沟槽的底部和阱区503的底部接触。
本实施例中，相邻两个栅极沟槽下方的屏蔽区506对齐设置。
步骤S507：在栅极沟槽的侧壁和底部形成栅极介质层507。
具体的，步骤S507包括以下步骤：
S507a：对漂移层502表面、栅极沟槽的侧壁和底部进行牺牲氧化处理；
S507b：在漂移层502上方、栅极沟槽的侧壁和底部形成栅极介质层507；
S507c：刻蚀掉漂移层502上方的栅极介质层507。
其中，牺牲氧化处理包括以下步骤：
(a)对漂移层502表面进行热氧化以形成牺牲氧化层(图中未示出)；其中，牺牲氧化层的厚度为10至50nm；
(b)通过湿法刻蚀将牺牲氧化层去除。
栅极介质层507为氧化层，与牺牲氧化层类似，都是在高温(如1300℃)氧气范围内进行热氧化形成。栅极介质层507厚度约30至1000nm。沟槽底部的介质层厚度可以高于侧壁介质层的厚度，以提高栅极介质层507底部的耐压能力。
屏蔽区506可大幅降低阻断状态下器件的栅极介质层507的电场应力，大幅提高器件的长期使用可靠性。
步骤S508：在栅极沟槽内填充多晶硅，以形成栅极508。
其中，填充的多晶硅为第一导电类型的高浓度掺杂的多晶硅，离子掺杂浓度大于1E18cm -3。
步骤S509：在栅极508上方形成覆盖栅极508的层间介质层509。
具体的，先在漂移层502上方形成整面的层间介质层509，然后通过刻蚀，只留下栅极508上方的层间介质层509。
步骤S510：在源区上方形成与源区电连接的源极金属层510；其中，栅极508通过层间介质层509与源极金属层510隔离，屏蔽区506通过阱区503和源区与源极金属层510电连接。
通过金属化工艺，在第一源区504和第二源区505上方形成同时与第一源区504和第二源区505电连接的源极金属层510。
由于屏蔽区506的顶部与栅极沟槽的底部和阱区503的底部接触，而阱区503表面内的第一源区504和第二源区505与源极金属层510电连接，所以，屏蔽区506通过阱区503和第二源区505与源极金属层510电连接(短接)，可提高器件的开关频率，降低开关损耗。
由于屏蔽区506在栅极沟槽底部纵向间隔设置，且其与源极金属层510短接，沟槽栅极(包括栅极沟槽、栅极介质层507和栅极508)在有屏蔽区506的部分，沟槽栅极两侧不会形成沟道，不会有沟道电流(导通电流)的产生，而沟槽栅极在没有屏蔽区506的部分，沟槽栅极两侧会形成沟道，形成沟道电流(导通电流)，即可以将电场保护区域和导电区域进行分离设置，达到既保证导通电流又能有效降低阻断态下栅极介质层507的电场应力的良好折中关系。且屏蔽区506的形成过程不会影响到导电区域(沟槽表面)的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。
且由于屏蔽区506的顶部与栅极沟槽的底部和阱区503的底部接触，克服了现有技术中由于屏蔽区不得接触阱区，栅极沟槽需要一定的刻蚀深度导致的工艺困难问题。
源极金属层510可以为铝、镍等与SiC具有低接触电阻率的金属。
步骤S511：在衬底501下方形成与衬底501欧姆接触的漏极金属层511。
具体的，通过金属化工艺，在衬底501下方形成与衬底501欧姆接触的漏极金属层511，漏极金属层511可以为铝、镍等与SiC具有低接触电阻率的金属。
整个制备工艺过程制程简单，可制造性强且制造成本较低。
对应地，第一导电类型和第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。
本实施例提供一种碳化硅器件的元胞结构500的制备方法，通过在栅极沟槽底部形成纵向间隔设置的第二导电类型的屏蔽区506，可大幅降低阻断状态下器件的栅极介质层507的电场应力，大幅提高器件的长期使用可靠性；屏蔽区506与阱区503的底部接触，可以通过阱区503和源区与源极金属层510电连接，提高器件的开关频率，降低开关损耗；纵向间隔设置的屏蔽区506，可以将导电区域与电场保护区域进行分离设置，屏蔽区506的形成过程不会影响到导电区域的离子掺杂浓度，不会对器件的阈值电压等电特性产生影响，有利于元胞间的均流。且制备工艺制程简单，可制造性强且制造成本较低。
以上仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。虽然本公开所公开的实施方式如上，但的内容只是为了便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属技术领域内的技术人员，在不脱离本公开所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本公开的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种碳化硅器件的元胞结构，其中，包括：
    第一导电类型碳化硅衬底；
    位于所述衬底上方的第一导电类型漂移层；
    多个间隔设置于所述漂移层表面内的第二导电类型阱区；
    位于所述阱区表面内的源区；
    位于相邻两个所述阱区之间的栅极沟槽；其中，所述栅极沟槽的侧壁同时与所述阱区和所述源区接触，所述栅极沟槽的深度大于所述阱区的深度；
    位于所述漂移层内且纵向间隔设置于所述栅极沟槽下方的第二导电类屏蔽区；其中，所述屏蔽区的顶部与所述栅极沟槽的底部和所述阱区的底部接触。
  2. 根据权利要求1所述的碳化硅器件的元胞结构，其中，
    所述源区包括第一导电类型第一源区，以及纵向间隔设置于所述第一源区内的第二导电类型第二源区；
    其中，所述第一源区的两端分别与两侧的所述栅极沟槽的侧壁接触，所述第二源区不与所述栅极沟槽的侧壁接触。
  3. 根据权利要求2所述的碳化硅器件的元胞结构，其中，相邻两个所述栅极沟槽下方的所述屏蔽区交错设置。
  4. 根据权利要求2所述的碳化硅器件的元胞结构，其中，还包括：
    位于所述栅极沟槽下方的第一导电类型存储区；
    其中，所述存储区和所述屏蔽区在纵向上间隔交替设置，所述存储区的顶部与所述栅极沟槽的底部和所述阱区的底部接触。
  5. 根据权利要求1所述的碳化硅器件的元胞结构，其中，
    相邻两个所述栅极沟槽下方的所述屏蔽区对齐设置。
    .
  6. 根据权利要求5所述的碳化硅器件的元胞结构，其中，所述源区包括在纵向上交替设置第一导电类型第一源区和第二导电类型第二源区；
    其中，所述第二源区与所述屏蔽区横向对齐设置，所述第一源区和所述第二源区的两 端分别与两侧的所述栅极沟槽的侧壁接触。
  7. 根据权利要求1所述的碳化硅器件的元胞结构，其中，还包括：
    设置于所述栅极沟槽的侧壁和底部的栅极介质层以及填充于所述栅极沟槽内的栅极；
    位于所述源区上方且与所述源区电连接的源极金属层；其中，所述栅极通过层间介质层与所述源极金属层隔离，所述屏蔽区通过所述阱区和所述源区与所述源极金属层电连接；
    位于所述衬底下方并与所述衬底形成欧姆接触的漏极金属层。
  8. 一种碳化硅器件的元胞结构的制备方法，其中，包括：
    提供第一导电类型碳化硅衬底；
    在所述衬底上方形成第一导电类型漂移层；
    在所述漂移层表面内形成多个间隔设置的第二导电类型阱区；
    在所述阱区表面内形成源区；
    在相邻两个所述阱区之间形成栅极沟槽；其中，所述栅极沟槽的侧壁同时与所述阱区和所述源区接触，所述栅极沟槽的深度大于所述阱区的深度；
    通过倾斜离子注入的方式在所述漂移层内于所述栅极沟槽下方形成纵向间隔设置的第二导电类型屏蔽区；其中，所述屏蔽区的顶部与所述栅极沟槽的底部和所述阱区的底部接触。
  9. 根据权利要求8所述的碳化硅器件的元胞结构的制备方法，其中，所述源区包括第一导电类型第一源区，以及纵向间隔设置于所述第一源区内的第二导电类型第二源区；
    所述在所述阱区表面内形成源区的步骤，包括以下步骤：
    在所述阱区表面内形成第一导电类型第一源区；其中，所述第一源区的两端分别与两侧的所述栅极沟槽的侧壁接触；
    在所述第一源区内形成纵向间隔设置的第二导电类型第二源区；其中，所述第二源区不与所述栅极沟槽的侧壁接触。
  10. 根据权利要求9所述的碳化硅器件的元胞结构的制备方法，其中，相邻两个所述栅极沟槽下方的所述屏蔽区交错设置。
  11. 根据权利要求9所述的碳化硅器件的元胞结构的制备方法，其中，所述通过倾斜离子注入的方式在所述漂移层内于所述栅极沟槽下方形成纵向间隔设置的第二导电类型屏蔽 区的步骤之后，所述方法还包括：
    在所述栅极沟槽下方形成第一导电类型存储区；
    其中，所述存储区和所述屏蔽区在纵向上间隔交替设置，所述存储区的顶部与所述栅极沟槽的底部和所述阱区的底部接触。
  12. 根据权利要求8所述的碳化硅器件的元胞结构的制备方法，其中，相邻两个所述栅极沟槽下方的所述屏蔽区对齐设置。
  13. 根据权利要求12所述的碳化硅器件的元胞结构的制备方法，其中，所述源区包括在纵向上交替设置第一导电类型第一源区和第二导电类型第二源区；
    所述在所述阱区表面内形成源区的步骤，包括以下步骤：
    在所述阱区表面内形成在纵向上交替设置第一导电类型第一源区和第二导电类型第二源区；
    其中，所述第二源区与所述屏蔽区横向对齐设置，所述第一源区和所述第二源区的两端分别与两侧的所述栅极沟槽的侧壁接触。
  14. 根据权利要求8所述的碳化硅器件的元胞结构的制备方法，其中，所述通过倾斜离子注入的方式在所述漂移层内于所述栅极沟槽下方形成纵向间隔设置的第二导电类型屏蔽区的步骤之后，所述方法还包括：
    在所述栅极沟槽的侧壁和底部形成栅极介质层；
    在所述栅极沟槽内填充多晶硅，以形成栅极；
    在所述栅极上方形成覆盖所述栅极的层间介质层；
    在所述源区上方形成与所述源区电连接的源极金属层；其中，所述栅极通过所述层间介质层与所述源极金属层隔离，所述屏蔽区通过所述阱区和所述源区与所述源极金属层电连接；
    在所述衬底下方形成与所述衬底欧姆接触的漏极金属层。
  15. 一种碳化硅器件，其中，包括若干如权利要求1至7中任一项所述的碳化硅器件的元胞结构。
PCT/CN2021/125473 2020-11-27 2021-10-22 碳化硅器件的元胞结构、其制备方法及碳化硅器件 WO2022111160A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP21896662.0A EP4254503A1 (en) 2020-11-27 2021-10-22 Cellular structure of silicon carbide device, method for preparation thereof, and silicon carbide device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011354573.6A CN112614879A (zh) 2020-11-27 2020-11-27 碳化硅器件的元胞结构、其制备方法及碳化硅器件
CN202011354573.6 2020-11-27

Publications (1)

Publication Number Publication Date
WO2022111160A1 true WO2022111160A1 (zh) 2022-06-02

Family

ID=75225582

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/125473 WO2022111160A1 (zh) 2020-11-27 2021-10-22 碳化硅器件的元胞结构、其制备方法及碳化硅器件

Country Status (3)

Country Link
EP (1) EP4254503A1 (zh)
CN (1) CN112614879A (zh)
WO (1) WO2022111160A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116013776A (zh) * 2023-03-02 2023-04-25 绍兴中芯集成电路制造股份有限公司 屏蔽栅沟槽型晶体管的制备方法及屏蔽栅沟槽型晶体管
CN116153966A (zh) * 2023-02-09 2023-05-23 上海功成半导体科技有限公司 超结mos器件结构及其制备方法
WO2024060259A1 (zh) * 2022-09-23 2024-03-28 华为数字能源技术有限公司 半导体器件、其制备方法、功率转换电路及车辆

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112614879A (zh) * 2020-11-27 2021-04-06 株洲中车时代半导体有限公司 碳化硅器件的元胞结构、其制备方法及碳化硅器件
CN113345965B (zh) * 2021-08-05 2021-11-09 浙江大学杭州国际科创中心 一种具有电场屏蔽结构的沟槽栅mosfet器件
CN113707723B (zh) * 2021-10-26 2022-02-08 北京世纪金光半导体有限公司 基于伪沟道的半导体器件及其制作方法
CN115148826B (zh) * 2022-09-06 2023-01-06 深圳平创半导体有限公司 一种深沟槽碳化硅jfet结构的制作方法
CN115513298A (zh) * 2022-11-11 2022-12-23 广东芯粤能半导体有限公司 沟槽型晶体管及其形成方法
CN116581161A (zh) * 2023-07-14 2023-08-11 西安电子科技大学 一种带有非连续型P+屏蔽层的SiC UMOSFET及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101326852B1 (ko) * 2012-09-14 2013-11-20 현대자동차주식회사 반도체 소자 및 그 제조 방법
CN105359277A (zh) * 2013-07-03 2016-02-24 罗伯特·博世有限公司 场板沟槽fet以及半导体构件
CN106449757A (zh) * 2016-09-28 2017-02-22 中国科学院半导体研究所 一种SiC基沟槽型场效应晶体管及其制备方法
CN111199969A (zh) * 2018-11-16 2020-05-26 英飞凌科技股份有限公司 具有集成体二极管的SiC功率半导体器件
CN112151619A (zh) * 2019-06-27 2020-12-29 比亚迪股份有限公司 碳化硅mosfet及其制造方法以及电子设备
CN112614879A (zh) * 2020-11-27 2021-04-06 株洲中车时代半导体有限公司 碳化硅器件的元胞结构、其制备方法及碳化硅器件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000106434A (ja) * 1998-09-29 2000-04-11 Toshiba Corp 高耐圧半導体装置
US6812521B1 (en) * 1999-11-16 2004-11-02 Advanced Micro Devices, Inc. Method and apparatus for improved performance of flash memory cell devices
JP3524850B2 (ja) * 2000-08-03 2004-05-10 三洋電機株式会社 絶縁ゲート型電界効果半導体装置
JP4398185B2 (ja) * 2003-06-24 2010-01-13 セイコーインスツル株式会社 縦形ｍｏｓトランジスタ
JP2009088198A (ja) * 2007-09-28 2009-04-23 Rohm Co Ltd 半導体装置
US8525255B2 (en) * 2009-11-20 2013-09-03 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates having thick trench bottom oxide as termination
JP5717661B2 (ja) * 2011-03-10 2015-05-13 株式会社東芝 半導体装置とその製造方法
CN108110056B (zh) * 2017-12-13 2020-10-16 上海芯龙半导体技术股份有限公司 垂直双扩散场效应晶体管及其制作方法
US10985248B2 (en) * 2018-11-16 2021-04-20 Infineon Technologies Ag SiC power semiconductor device with integrated Schottky junction

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101326852B1 (ko) * 2012-09-14 2013-11-20 현대자동차주식회사 반도체 소자 및 그 제조 방법
CN105359277A (zh) * 2013-07-03 2016-02-24 罗伯特·博世有限公司 场板沟槽fet以及半导体构件
CN106449757A (zh) * 2016-09-28 2017-02-22 中国科学院半导体研究所 一种SiC基沟槽型场效应晶体管及其制备方法
CN111199969A (zh) * 2018-11-16 2020-05-26 英飞凌科技股份有限公司 具有集成体二极管的SiC功率半导体器件
CN112151619A (zh) * 2019-06-27 2020-12-29 比亚迪股份有限公司 碳化硅mosfet及其制造方法以及电子设备
CN112614879A (zh) * 2020-11-27 2021-04-06 株洲中车时代半导体有限公司 碳化硅器件的元胞结构、其制备方法及碳化硅器件

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024060259A1 (zh) * 2022-09-23 2024-03-28 华为数字能源技术有限公司 半导体器件、其制备方法、功率转换电路及车辆
CN116153966A (zh) * 2023-02-09 2023-05-23 上海功成半导体科技有限公司 超结mos器件结构及其制备方法
CN116153966B (zh) * 2023-02-09 2023-12-12 上海功成半导体科技有限公司 超结mos器件结构及其制备方法
CN116013776A (zh) * 2023-03-02 2023-04-25 绍兴中芯集成电路制造股份有限公司 屏蔽栅沟槽型晶体管的制备方法及屏蔽栅沟槽型晶体管
CN116013776B (zh) * 2023-03-02 2023-09-15 绍兴中芯集成电路制造股份有限公司 屏蔽栅沟槽型晶体管的制备方法及屏蔽栅沟槽型晶体管

Also Published As

Publication number Publication date
CN112614879A (zh) 2021-04-06
EP4254503A1 (en) 2023-10-04

Similar Documents

Publication Publication Date Title
WO2022111160A1 (zh) 碳化硅器件的元胞结构、其制备方法及碳化硅器件
WO2022028315A1 (zh) 碳化硅器件的元胞结构、其制备方法及碳化硅器件
US8637922B1 (en) Semiconductor device
TWI520337B (zh) 階梯溝渠式金氧半場效電晶體及其製造方法
KR101106535B1 (ko) 전력용 반도체 소자 및 그 제조방법
US10522627B2 (en) Semiconductor device
US9825158B2 (en) Insulated gate bipolar transistor
JP2007027266A (ja) 半導体素子及びその製造方法
JP2011023675A (ja) 半導体装置及びその製造方法
US11888022B2 (en) SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof
CN104979395A (zh) 半导体结构
CN108604551A (zh) 半导体装置以及用于制造这种半导体装置的方法
CN114284358A (zh) 一种碳化硅功率器件及其制备方法
JP5233158B2 (ja) 炭化珪素半導体装置
KR100398756B1 (ko) 반도체장치 및 그 제조방법
JP2023162328A (ja) 縦型電界効果トランジスタおよびその形成のための方法
CN116759461A (zh) 一种高温稳定性的功率mosfet器件及其制备方法
CN116613210A (zh) 一种高耐压碳化硅umosfet器件及其制备方法
CN208489191U (zh) 一种屏蔽栅功率mosfet器件
CN115513297A (zh) 碳化硅平面mosfet器件及其制造方法
CN108376710A (zh) 具有浮岛结构的宽禁带半导体vdmosfet器件及其制造方法
RU2749386C2 (ru) Способ производства структуры единичной ячейки силиконово-карбидного моп-транзистора
CN114628516A (zh) SiC MOSFET器件及制造方法
CN111192915A (zh) 半导体功率器件及其制造方法
CN212113722U (zh) 具有肖特基二极管的半导体器件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21896662

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2021896662

Country of ref document: EP

Effective date: 20230627