CN116613210A - 一种高耐压碳化硅umosfet器件及其制备方法 - Google Patents
一种高耐压碳化硅umosfet器件及其制备方法 Download PDFInfo
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- 239000000377 silicon dioxide Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 claims description 4
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Abstract
本发明公开了一种高耐压碳化硅UMOSFET器件及其制备方法。所述碳化硅UMOSFET器件包括漏电极、N型掺杂衬底层、两个P型离子注入区、N型外延区、N型电流扩展区和P型基区，其中，P型基区上设置有P型源区和N型源区，N型外延区设置有沟槽结构，所述沟槽结构的底部延伸至所述N型漂移区的内部，沟槽结构的两个底边分别与两个P型注入区接触，增强了栅极氧化层的可靠性，降低了沟槽底部和侧面氧化层的电场强度，提高了器件的击穿电压。同时浮空式P型埋层反向阻断时形成耗尽区，减少了栅漏接触面积，降低了栅漏电容，提升开关速率。
Description
技术领域
本发明属于半导体技术领域，具体涉及一种高耐压碳化硅UMOSFET器件及其制备方法。
背景技术
碳化硅(SiC)作为一种优异的第三代半导体材料，具有很多优良的电学和物理特性：禁带宽度大、击穿场强高、热导率高、载流子饱和漂移速率高、相对介电常数小等，并且它可以通过热氧化得到氧化物材料(SiO2)，适合制作高温、高压、大功率及抗辐射照的半导体器件。与硅(Si)基器件相比，SiC MOSFET器件具有电流密度大、体积小、开关速度快、反向耐压高等优点，目前已经被广泛应用在开关电源、汽车电子、航空航天等方面。
SiC MOSFET器件结构的发展从最初的LDMOS(横向平面双扩散MOSFET)到VDMOS(垂直双扩散MOSFET)，再到目前的UMOS(沟槽栅MOSFET)。垂直结构与平面结构相比，导电沟道变为垂直方向，减小的元胞的尺寸，电流密度显著增加，而且由于消除了寄生的JEFT区，导通电阻明显变小。
目前，在传统的槽栅结构UMOSFET器件中已经能够通过设计使其达到较高的耐压水平，但是在实际应用中，碳化硅MOSFET器件在击穿时，栅极氧化层中的电场远远大于硅基MOSFET器件氧化层中的电场，在碳化硅器件发生击穿时，体内的最大电场强度可以达到3MV/cm，由高斯定理得知，栅极氧化层的电场超过7MV/cm，使得栅极氧化层的可靠性大大降低，特别是沟槽结构底部及其槽角处会存在电场集中现象，极大的降低了器件的击穿电压。虽然目前有V型栅结构可以改善这种现象，但是该结构重复性差，刻蚀窗口小(沟槽的刻蚀方法、碳化硅器件的制备方法及碳化硅器件CN 111986991 A)。因此，降低栅沟槽底部的电场强度是目前研究的重点。
发明内容
为了解决现有技术中存在的上述问题，本发明提供了一种含有两个P型离子注入区的高耐压碳化硅UMOSFET器件及其制作方法。本发明额外增加了两个P型离子注入区，使得栅极氧化层电场强度大幅度降低，提高了器件的击穿电压。
本发明的目的至少通过如下技术方案之一实现。
一种高耐压碳化硅UMOSFET器件，包括从下至上顺次层叠的漏电极、N型掺杂衬底层和N型外延区；
N型外延区上表面中部设置有沟槽结构；
N型外延区上依次层叠N型电流扩展区和P型基区；
P型基区上表面上设置有紧贴的N型源区和P型源区，N型源区设置在P型基区上表面中部，P型源区设置在P型基区上表面外围，包围N型源区；
所述沟槽结构下表面设置于N型外延区内，上表面与N型源区的上表面齐平；N型外延区内部设置有两个P型离子注入区，分别与沟槽结构的两个底边接触；
沟槽结构中设置有多晶硅栅，多晶硅栅除上表面外其余表面均连接有栅极氧化层；
多晶硅栅上表面设置有栅电极，N型源区和P型源区的连接处上方设置有源电极。
进一步地，源电极分别与N型源区和P型源区接触的界面都为欧姆接触。
进一步地，所述N型掺杂衬底层的掺杂浓度为5×1018cm-3～1×1019cm-3。
进一步地，所述N型外延区的厚度为12μm～16μm，且掺杂浓度为5×1015cm-3～1×1016cm-3。
进一步地，所述P型离子注入区的掺杂浓度为2×1017cm-3～8×1017cm-3，所述P型离子注入区在N型外延区中横向、纵向超出沟槽结构的距离均为0.2μm～0.6μm，所述P型离子注入区在N型外延区中横向、纵向与沟槽结构交叠的距离均为0.2μm～0.6μm。
进一步地，所述N型电流扩展层的厚度为0.3μm～0.6μm，且掺杂浓度为2×1017cm-3～6×1017cm-3。
进一步地，所述P型基区的厚度为0.6μm～1μm，且掺杂浓度为1×1017cm-3～5×1017cm-3；
所述N型源区以及P型源区的厚度为0.2μm～0.5μm，且掺杂浓度为1×1019cm-3～1×1019cm-3。
进一步地，所述栅电极氧化层的材料包括二氧化硅；
所述源电极的材料包括钛或镍；
所述栅电极的材料包括多晶硅；
所述漏电极的材料包括钛或镍。
进一步地，所述沟槽结构从上至下的深度为2.5μm～3.5μm，宽度为2.5μm～3.5μm。
一种高耐压碳化硅UMOSFET器件的制作方法，包括如下步骤:
S1、提供N型衬底，在所述N型衬底上生长N型外延区；
S2、制作光刻对准标记并且刻蚀沟槽结构；
S3、利用离子注入工艺，在所述N型外延区上形成N型电流扩展区以及P型基区；
S4、利用离子注入工艺，在所述P型基区上形成N型源区和P型源区；
S5、利用离子注入工艺，在沟槽结构的底部运用倾斜注入方式形成两个P型离子注入区；
S6、高温退火后，在所述沟槽结构的侧壁和底部上生长栅极氧化层作为栅介质，并且在氮气氧气混合环境下退火；
S7、在栅介质上制作多晶硅介质层，在多晶硅介质层上制备栅电极；
S8、在N型衬底背面制作漏电极，在P型源区和N型源区上制作源电极。
与现有技术相比，本发明的有益效果在于：
1、通过额外注入的两个P型离子注入区与N型外延区形成的空间电荷区来承受高电压，大幅度降低了栅电极氧化层的电场强度，保护了沟槽栅的两个槽角。同时形成的超级结结构保护沟槽栅的底部，提高了器件击穿电压。
2、N型外延区中的N型电流扩展区能够使N型载流子在通过反型层后迅速在横向上扩展开来，大幅度降低了器件导通电阻。
3、通过在槽栅结构底部增加P型离子注入区，减小了栅电极与漏电极之间的电容，增大了器件的开关速度，减小了能量损耗，降低了器件在高频工作下的散热要求。
附图说明
图1是本发明实施例提供的一种高耐压碳化硅UMOSFET器件的结构示意图；
图2是本发明实施例提供的一种高耐压碳化硅UMOSFET器件的结构尺寸图；
图3是本发明实施例提供的一种高耐压碳化硅UMOSFET器件的制备方法流程图；
图4～图11是本发明实施例提供的一种高耐压碳化硅UMOSFET器件形成过程示意图；
图12是本发明实施例提供的一种高耐压碳化硅UMOSFET器件与传统沟槽栅UMOSFET器件击穿电压对比图。
具体实施方式
为了进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体实施方式对本发明进行详细说明。需要指出的是，只要各种变化和修饰是基于本发明所附权利要求限定和精神范围内的，都在保护范围之列。
在本说明书中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本说明。在本说明书一个或多个实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本说明书一个或多个实施例中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
实施例：
在一个实施例中，一种高耐压碳化硅UMOSFET器件，如图1所示，包括从下至上顺次层叠的漏电极1、N型掺杂衬底层2和N型外延区3；
N型外延区3上表面中部设置有沟槽结构；
N型外延区3上依次层叠N型电流扩展区6和P型基区8；
P型基区8上表面上设置有紧贴的N型源区9和P型源区10，N型源区9设置在P型基区8上表面中部，P型源区10设置在P型基区8上表面外围，包围N型源区9；
所述沟槽结构下表面设置于N型外延区3内，上表面与N型源区9的上表面齐平；N型外延区3内部设置有两个P型离子注入区4，分别与沟槽结构的两个底边接触；
沟槽结构中设置有多晶硅栅7，多晶硅栅7除上表面外其余表面均连接有栅极氧化层5；
多晶硅栅7上表面设置有栅电极12，N型源区9和P型源区10的连接处上方设置有源电极11。
金属化漏电极为Ti/Ni合金。N型掺杂衬底层2在漏电极1上方，作为重掺杂衬底用于减小器件导通电阻并传输电流，掺杂浓度为8×1018cm-3～8×1019cm-3。N型漂移区3在N型掺杂衬底层2上方，作为轻掺杂区用于反向截止工作下承担漏电极1的电压，防止器件被击穿，其厚度为12μm～16μm，掺杂浓度为5×1015cm-3～1×1016cm-3，如果掺杂浓度过高，虽然器件导通电阻减小，但是器件击穿电压会降低。
优选的，P型离子注入区4的掺杂浓度为2×1017cm-3～8×1017cm-3，所述P型离子注入区在N型外延区中横向、纵向超出沟槽结构的距离均为0.2μm～0.6μm，所述P型离子注入区在N型外延区中横向、纵向与沟槽结构交叠的距离均为0.2μm～0.6μm。如果此区域过大、掺杂浓度过高，那么与N型外延区3形成的空间电荷区也会变大，阻碍了载流子的扩散，增加了导通电阻。
优选的，栅极氧化层5在沟槽表面，厚度过大会增大阈值电压，增加器件功耗，其厚度为40～70nm。N型电流扩展区6位于所述N型外延区3中，并且与沟槽的栅极氧化层5侧壁相接触，N型电流扩展层的厚度为0.3μm～0.6μm，且掺杂浓度为2×1017cm-3～6×1017cm-3，它可以使载流子在横向上迅速扩散。
优选的，P型基区8位于N型电流扩展区6上方，作为轻掺杂注入区用于在栅电极12加压时形成导电沟道，厚度0.6μm～1μm，且掺杂浓度为1×1017cm-3～5×1017cm-3，厚度过大会增加器件导电沟道的长度，使得导通电阻增大，掺杂浓度过高，器件的阈值电压会偏高，栅充电速度降低，对器件栅电极驱动电路要求增大，掺杂浓度过低，器件阈值电压偏低，容易误开启，所以综合考虑选择掺杂浓度为1×1017cm-3～5×1017cm-3。
优选的，N型源区9在P型基区8上方，其厚度为0.2μm～0.5μm，且掺杂浓度为1×1019cm-3～5×1019cm-3，它是器件中N型载流子的主要来源。同样的，P型源区的厚度也为0.2μm～0.5μm，且掺杂浓度为1×1019cm-3～1×1019cm-3，它用来防止寄生BJT的导通，延长器件的寿命。
在一个实施例中，一种高耐压碳化硅UMOSFET器件的制作方法，参照图4～图11，包括如下步骤：
S1、在一个实施例中，提供N型衬底，在所述N型衬底上生长N型外延区，随后将外延置于H2SO4:H2O2＝3：1(质量比)溶液中浸泡10分钟，去除表面氧化层，再采用丙酮和异丙醇超声清洗10分钟去除外延上的有机物，如图4所示。
S2、制作光刻对准标记并且刻蚀沟槽结构；
在一个实施例中，首先用PECVD生长2μm二氧化硅作为硬掩膜层，然后通过光刻工艺得到图形化的沟槽区域，首先采用ICP/RIE刻蚀技术进行二氧化硅掩膜层刻蚀，其次再对碳化硅进行刻蚀，刻蚀气体选择CF4/Cl2/O2，随后去除二氧化硅掩膜层，如图5所示。
S3、利用离子注入工艺，在所述N型外延区上形成N型电流扩展区以及P型基区，如图6所示；
在一个实施例中，首先通过光刻工艺得到图形化的注入区域，然后利用离子注入工艺，在所述N型外延区上形成N型电流扩展区以及P型基区。
S4、利用离子注入工艺，在所述P型基区上形成N型源区和P型源区，如图7所示；
S5、利用离子注入工艺，在沟槽结构的底部运用倾斜注入方式形成两个P型离子注入区，如图8所示；
S6、高温退火后，在所述沟槽结构的侧壁和底部上生长栅极氧化层作为栅介质，并且在氮气氧气混合环境下退火，如图9所示；
在一个实施例中，首先在沟槽处用磁控溅射生长一层碳膜，然后1700℃下30min退火激活离子活性。接下来，通过湿法氧化或者干法氧化在所述沟槽生长栅极氧化层作为栅介质，并且在氮气氧气环境中，1300℃进行退火，退火时间为30min。
S7、在栅介质上制作多晶硅介质层，在多晶硅介质层上制备栅电极，如图10所示；
在一个实施例中，在栅介质上用LPCVD沉积多晶硅，离子注入N增加导电性，然后在多晶硅介质层上制备栅电极。
S8、在N型衬底背面制作漏电极，在P型源区和N型源区上制作源电极，如图11所示；
在一个实施例中，在SiC衬底背面电子束蒸镀Ni/Ti制作漏电极，在在P型源区和N型源区上电子束蒸镀Ni/Ti制作源电极。
图12为传统沟槽栅UMOSFET、改进沟槽栅UMOSFET的击穿特性曲线。改进型UMOSFET阻断电压为1509V，传统沟槽栅UMOSFET阻断电压为1121V，击穿电压提高了34.62％。
以上公开的本申请优选实施例只是用于帮助理解本发明及核心思想。对于本领域的一般技术人员，依据本发明的思想，在具体应用场景和实施操作上均会有改变之处，本说明书不应理解对本发明的限制。本发明仅受权利要求书及其全部范围和等效物的限制。
Claims (10)
1.一种高耐压碳化硅UMOSFET器件，其特征在于，包括从下至上顺次层叠的漏电极(1)、N型掺杂衬底层(2)和N型外延区(3)；
N型外延区(3)上表面中部设置有沟槽结构；
N型外延区(3)上依次层叠N型电流扩展区(6)和P型基区(8)；
P型基区(8)上表面上设置有紧贴的N型源区(9)和P型源区(10)，N型源区(9)设置在P型基区(8)上表面中部，P型源区(10)设置在P型基区(8)上表面外围，包围N型源区(9)；
所述沟槽结构下表面设置于N型外延区(3)内，上表面与N型源区(9)的上表面齐平；N型外延区(3)内部设置有两个P型离子注入区(4)，分别与沟槽结构的两个底边接触；
沟槽结构中设置有多晶硅栅(7)，多晶硅栅(7)除上表面外其余表面均连接有栅极氧化层(5)；
多晶硅栅(7)上表面设置有栅电极(12)，N型源区(9)和P型源区(10)的连接处上方设置有源电极(11)。
2.根据权利要求1所述的一种高耐压碳化硅UMOSFET器件，其特征在于，源电极(11)分别与N型源区(9)和P型源区(10)接触的界面都为欧姆接触。
3.根据权利要求1所述的一种高耐压碳化硅UMOSFET器件，其特征在于，所述N型掺杂衬底层(2)的掺杂浓度为5×1018cm-3～1×1019cm-3。
4.根据权利要求1所述的一种高耐压碳化硅UMOSFET器件，其特征在于，所述N型外延区(3)的厚度为12μm～16μm，且掺杂浓度为5×1015cm-3～1×1016cm-3。
5.根据权利要求1所述的一种高耐压碳化硅UMOSFET器件，其特征在于，所述P型离子注入区(4)的掺杂浓度为2×1017cm-3～8×1017cm-3，所述P型离子注入区(4)在N型外延区(3)中横向、纵向超出沟槽结构的距离均为0.2μm～0.6μm，所述P型离子注入区(4)在N型外延区(3)中横向、纵向与沟槽结构交叠的距离均为0.2μm～0.6μm。
6.根据权利要求1所述的一种高耐压碳化硅UMOSFET器件，其特征在于，所述N型电流扩展层(6)的厚度为0.3μm～0.6μm，且掺杂浓度为2×1017cm-3～6×1017cm-3。
7.根据权利要求1所述的一种高耐压碳化硅UMOSFET器件，其特征在于，所述P型基区(8)的厚度为0.6μm～1μm，且掺杂浓度为1×1017cm-3～5×1017cm-3；
所述N型源区(9)以及P型源区(10)的厚度为0.2μm～0.5μm，且掺杂浓度为1×1019cm-3～1×1019cm-3。
8.根据权利要求1所述的一种高耐压碳化硅UMOSFET器件，其特征在于，所述栅电极氧化层(5)的材料包括二氧化硅；
所述源电极(11)的材料包括钛或镍；
所述栅电极(12)的材料包括多晶硅；
所述漏电极(1)的材料包括钛或镍。
9.根据权利要求1所述的一种高耐压碳化硅UMOSFET器件，其特征在于，所述沟槽结构从上至下的深度为2.5μm～3.5μm，宽度为2.5μm～3.5μm。
10.一种高耐压碳化硅UMOSFET器件的制作方法，其特征在于，包括如下步骤:
S1、提供N型衬底，在所述N型衬底上生长N型外延区；
S2、制作光刻对准标记并且刻蚀沟槽结构；
S3、利用离子注入工艺，在所述N型外延区上形成N型电流扩展区以及P型基区；
S4、利用离子注入工艺，在所述P型基区上形成N型源区和P型源区；
S5、利用离子注入工艺，在沟槽结构的底部运用倾斜注入方式形成两个P型离子注入区；
S6、高温退火后，在所述沟槽结构的侧壁和底部上生长栅极氧化层作为栅介质，并且在氮气氧气混合环境下退火；
S7、在栅介质上制作多晶硅介质层，在多晶硅介质层上制备栅电极；
S8、在N型衬底背面制作漏电极，在P型源区和N型源区上制作源电极。
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