CN108336133B - 一种碳化硅绝缘栅双极型晶体管及其制作方法 - Google Patents
一种碳化硅绝缘栅双极型晶体管及其制作方法 Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 217
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 206
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 78
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 210000000746 body region Anatomy 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229910045601 alloy Inorganic materials 0.000 claims description 14
- 239000000956 alloy Substances 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 210000003850 cellular structure Anatomy 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 12
- 230000001965 increasing effect Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 210000004027 cell Anatomy 0.000 description 5
- 239000000969 carrier Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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Abstract
一种碳化硅绝缘栅双极型晶体管及其制作方法,属于半导体功率器件技术领域。本发明提供的SiC IGBT器件包括自下而上依次层叠设置的金属集电极、衬底、缓冲层、漂移区、栅极结构、层间介质层和发射极金属,其中,漂移区的两端分别存在凹槽,两个凹槽相互独立并在其间形成一个高于凹槽底部平面的平台,本发明在凹槽底部顶层和平台顶层上集成了平面型和槽栅型IGBT,相比传统平面型IGBT增加了水平沟槽和垂直沟槽的数量,进而增强了正向电导调制效应,提升了器件正向导通能力;并且有利于屏蔽凹槽底部的电场集聚效应,提高了器件制造的可行性。此外,本发明提供的制作工艺与现有半导体制作工艺相兼容,无需增加额外的工艺步骤,节约了器件制造成本。
Description
技术领域
本发明属于半导体功率器件技术领域,特别涉及一种碳化硅绝缘栅双极型晶体及其制作方法。
背景技术
近年来,作为新兴宽禁带半导体材料——碳化硅(Silicon Carbide,SiC)因其出色的物理及电特性,正越来越受到产业界的广泛关注。由于SiC比Si具有更大的禁带宽度、更高的电子饱和漂移速度、更高的临界击穿电场以及更高的热导率,故使碳化硅基功率器件相比于同等耐压等级的硅基功率器件,具有更高的掺杂浓度及更小的外延层厚度,因此能够显著减小正向导通电阻和功率损耗。而且碳化硅的高热导率特别适合用于高压大电流的场合,从而减少整个功率转换系统的散热设备,缩小设备体积,提高可靠性,降低成本。因此,碳化硅基功率器件正因为很大程度的降低了电子设备的功耗而被称为“绿色能源”器件,在绿色节能领域开始越来越多的替代硅基功率器件,推动了“新能源革命”的发展。
碳化硅绝缘栅双极型晶体管(SiC IGBT)是一种MOS电压控制与双极晶体管相结合的复合器件。其作为两种载流子导电器件,相比单极型器件具有更高的电流导通能力。但是,现有SiC材料受到体内深能级缺陷的影响,载流子寿命低,双极扩散长度小,电导调制能力差,导致传统平面型或者沟槽型SiC IGBT器件的导通电流密度小,无法充分发挥SiC材料的优异性能。如果要传导更大的电流,则需要多个IGBT器件并联,这样使得成本明显增加。故而,如何提高SiC IGBT器件的导通电流成为了本领域技术人员亟待解决的技术问题。
目前,为了改善SiC IGBT器件的电导调制效应,通常采用如下技术手段:一方面通过改善SiC外延材料的质量或者通过碳注入或高温氧化退火的方式,减少或者消除SiC材料体内深能级缺陷密度,延长SiC材料中载流子寿命,从而增强SiC IGBT器件的正向导通电流;另一方面在器件中引入高掺杂浓度的电荷存储层,以此增强器件的电导调制效应,从而提升器件的正向导通电流,但是随之而来产生了击穿电压降低的严峻问题,降低了器件的可靠性。
发明内容
本发明的目的在于:针对现有技术中碳化硅绝缘栅双极型晶体管所存在正向导通电流小的问题,提供了一种电导调制效应更强的碳化硅绝缘栅双极型晶体管,通过在传统平面型碳化硅绝缘栅双极型晶体管结构的基础上集成槽栅结构,进而藉由沟道数量的增加来提高器件的正向电流能力,并且该结构采用自对准工艺制作器件以缩短沟道长度,同时制作方法与现有半导体制作方法兼容,无需增加额外工艺步骤。
为了实现上述目的,本发明采用如下技术方案:
一方面本发明提供了一种碳化硅绝缘栅双极型晶体管,其特征在于,其元胞结构包括自下而上依次层叠设置的金属集电极12、第一导电类型碳化硅衬底1、第二导电类型碳化硅缓冲层2、第二导电类型碳化硅漂移区3、栅介质层7、多晶硅栅8、层间介质层10和发射极金属11;所述第二导电类型碳化硅漂移区3为凸型结构,在第二导电类型碳化硅漂移区3的表面两侧分别具有凹槽,两个凹槽之间形成一个凸起的平台;所述平台的表面两侧和所述凹槽的底部分别具有一个第一导电类型碳化硅体区4,每个第一导电类型碳化硅体区4中具有相互独立且彼此接触的第一导电类型碳化硅体接触区5和第二导电类型碳化硅源区6,其中:平台表面两侧的第一导电类型碳化硅体区4的顶层具有设置在第一导电类型碳化硅体接触区5两侧的第二导电类型碳化硅源区6,凹槽底部的第一导电类型碳化硅体区4的顶层具有设置在第一导电类型碳化硅体接触区5一侧的第二导电类型碳化硅源区6;每个第一导电类型碳化硅体区4中的第一导电类型碳化硅体接触区5及部分第二导电类型碳化硅源区6的上表面设置有欧姆合金层9;凹槽底部表面及其槽壁表面以及平台上表面设置有与第二导电类型碳化硅漂移区3、第一导电类型碳化硅体区4和第二导电类型碳化硅源区6相接触的栅介质层7,栅介质层7的上表面设置有多晶硅栅8,栅介质层7和多晶硅栅8构成栅极结构;发射极金属11设置在欧姆合金层9上方且与之相接触,且发射极金属11与栅极结构之间通过层间介质层10相隔离。
进一步地,本发明中第一导电类型碳化硅为P型碳化硅,第二导电类型碳化硅为N型碳化硅或者第一导电类型碳化硅为N型碳化硅,第二导电类型碳化硅为P型碳化硅。
另一方面本发明提供上述碳化硅绝缘栅双极型晶体管的制作方法,其特征在于,包括如下步骤:
步骤1:在第一导电类型碳化硅衬底1上依次制作第二导电类型碳化硅缓冲层2和第二导电类型碳化硅漂移区3;
步骤2:在第二导电类型碳化硅漂移区3表面两侧刻蚀形成凹槽,两个凹槽之间形成一个凸起的平台;
步骤3:通过离子注入工艺,在第二导电类型碳化硅漂移区3的凹槽底部及平台表面两侧形成第一导电类型碳化硅体区4;
步骤4:通过顺次淀积多晶硅及介质层和刻蚀工艺、在平台表面中间及槽壁形成侧墙结构;
步骤5:通过沟道自对准工艺和离子注入工艺,在第一导电类型碳化硅体区4顶层形成第二导电类型碳化硅源区6;
步骤6:通过离子注入工艺,在凹槽底部的第二导电类型碳化硅源区6一侧以及平台顶层的第二导电类型碳化硅源区6中央形成第一导电类型碳化硅体接触区5;
步骤7:通过淀积或者热氧化工艺,在第一导电类型碳化硅体区4、第一导电类型碳化硅体接触区5和第二导电类型碳化硅源区6的上表面形成栅介质层7;
步骤8:通过刻蚀、淀积及退火工艺,在半导体表面形成窗口露出第一导电类型碳化硅体接触区5和部分第二导电类型碳化硅源区6,并在第一导电类型碳化硅体接触区5和部分第二导电类型碳化硅源区6的上表面制作欧姆合金层9;
步骤9:通过淀积工艺,在半导体背面形成金属集电极12;
步骤10:通过淀积和刻蚀工艺,在栅介质层7上表面形成多晶硅栅8;
步骤11:通过淀积和刻蚀工艺,在半导体正面淀积层间介质层10,在半导体表面的层间介质层10上形成窗口露出欧姆合金层9;
步骤12:通过淀积和刻蚀工艺,在半导体表面形成金属发射极11。
进一步地,本发明中第一导电类型碳化硅为P型碳化硅,第二导电类型碳化硅为N型碳化硅或者第一导电类型碳化硅为N型碳化硅,第二导电类型碳化硅为P型碳化硅。
本发明相比现有技术最显著的区别在于:器件集成了平面型和沟槽栅,形成了由多个MOSFET结构构成的发射极。当器件工作在正向导通时,器件发射极的多个MOS沟道同时导通,从而能够向漂移区提供大量的多数载流子电流,由于电中性要求,器件集电极也会向漂移区注入大量少数载流子电流,因而增强了体内双极载流子的电导调制效应,显著提高了正向导通电流能力,减小了高阻基区的导通损耗;并且由于本发明提供的器件结构中沟道数量相比传统IGBT器件增多,从而显著增加了器件的沟道密度;当器件工作在反向阻断时,体区能够屏蔽两端凹槽底部栅介质层的电场集中效应影响。
相比现有技术,本发明的有益效果是:
相比传统绝缘栅双极型晶体管(IGBT),本发明提供的碳化硅绝缘栅双极型晶体管(SiCIGBT)兼具平面型IGBT栅极-集电极电容小,器件开关速度快以及沟槽栅IGBT导通电阻小,导通电流能力强的优势;并且在传统平面型IGBT的基础上进一步增加水平沟道和垂直沟道的数目,从而达到了增大其沟道密度,增强其正向导通能力,降低其高阻基区的导通损耗的目的。另外,本发明提供的SiC IGBT器件的制作方法采用沟道自对准工艺,能够同时形成多种MOSFET导电沟道结构,与现有半导体制造工艺相兼容,不会增加额外的工艺步骤,节约了器件制造成本。
附图说明
图1是本发明实施例提供的SiC IGBT器件元胞结构的剖面示意图。
图2是本发明实施例提供的SiC IGBT器件结构在P型碳化硅衬底上制作得到N+碳化硅缓冲层和N-碳化硅漂移区的示意图。
图3是本发明实施例提供的SiC IGBT器件结构刻蚀得到凸型结构N-碳化硅漂移区的示意图。
图4是本发明实施例提供的SiC IGBT器件结构形成P型碳化硅体区的示意图。
图5是本发明实施例提供的SiC IGBT器件结构形成侧墙结构的示意图。
图6是本发明实施例提供的SiC IGBT器件结构形成N+碳化硅源区的示意图。
图7是本发明实施例提供的SiC IGBT器件结构形成P+碳化硅体接触区的示意图。
图8是本发明实施例提供的SiC IGBT器件结构在表面淀积栅介质层的示意图。
图9是本发明实施例提供的SiC IGBT器件结构刻蚀栅介质层形成欧姆合金层的示意图,其中,图(a)为元胞结构的剖面示意图,图(b)为元胞结构的立体示意图。
图10是本发明实施例提供的SiC IGBT器件结构形成金属集电极的示意图。
图11是本发明实施例提供的SiC IGBT器件结构形成多晶硅栅的示意图,其中,图(a)为元胞结构的剖面示意图,图(b)为元胞结构的立体示意图。
图12是本发明实施例提供的SiC IGBT器件结构形成层间介质层的示意图。
图13是本发明实施例提供的SiC IGBT器件结构形成发射极金属的示意图。
图14是本发明实施例提供的SiC IGBT器件正向导通时载流子路径示意图。
图中:1是P型碳化硅衬底,2是N+碳化硅缓冲层,3是N-碳化硅漂移区,4是P型碳化硅体区,5是P+碳化硅体接触区,6是N+碳化硅源区,7为栅介质层,8是多晶硅栅,9是欧姆合金层,10是层间介质层,11为金属发射极,12为金属集电极。
具体实施方式
下面结合具体实施例说明书附图对本发明的原理和特性进行详细说明:
在附图中相同的标号表示相同或者相似的结构。本发明提供的SiC IGBT器件可以是N沟道IGBT器件,也可以是P沟道IGBT器件,下面以N沟道IGBT器件为例进行说明,所属领域技术人员在公开N沟道IGBT器件的基础上能够清楚P沟道IGBT器件的结构及工作原理。
实施例:
本实施例提供一种碳化硅绝缘栅双极型晶体管,其元胞结构的剖面示意图如图1所示,包括自下而上依次层叠设置的金属集电极12、P型碳化硅衬底1、N+碳化硅缓冲层2、N-碳化硅漂移区3、栅介质层7、多晶硅栅8、层间介质层10和发射极金属11;所述N-碳化硅漂移区3为凸型结构,在N-碳化硅漂移区3的表面两侧分别具有凹槽,两个凹槽之间形成一个凸起的平台;所述平台表面两侧和所述凹槽的底部分别具有一个P型碳化硅体区4;每个P型碳化硅体区4中具有相互独立且彼此接触的P+碳化硅体接触区5和N+碳化硅源区6,其中:平台表面两侧的P型碳化硅体区4的顶层具有设置在P+碳化硅体接触区5两侧的N+碳化硅源区6,凹槽底部的P型碳化硅体区4的顶层具有设置在P+碳化硅体接触区5一侧的N+碳化硅源区6;每个P型碳化硅体区4中的P+碳化硅体接触区5及部分N+碳化硅源区6的上表面设置有欧姆合金层9;凹槽底部表面及其侧壁表面以及平台上表面设置有与N-碳化硅漂移区3、P型碳化硅体区4和N+碳化硅源区6相接触的栅介质层7,栅介质层7的上表面设置有多晶硅栅8,栅介质层7和多晶硅栅8构成栅极结构;发射极金属11设置在欧姆合金层9上方且与之相接触,且发射极金属11与栅极结构之间通过层间介质层10相隔离。
制作上述碳化硅绝缘栅双极型晶体管结构的工艺包括如下步骤:
步骤1:选择洁净的P型碳化硅片作为衬底,在P型碳化硅衬底1上依次制作N+碳化硅缓冲层2和N-碳化硅漂移区3,如图2所示;
步骤2:在N-碳化硅漂移区3上沉淀SiO2并采用干法刻蚀表面两侧的SiO2形成窗口,继续采用干法刻蚀去除窗口区的N-碳化硅漂移区3形成凹槽,两侧凹槽之间形成一个凸起的平台,如图3所示;
步骤3:在N型碳化硅漂移区3的凹槽底部及平台表面两侧的顶层注入P型离子,形成P型碳化硅体区4,如图4所示;
步骤4:在半导体表面淀积多晶硅,并刻蚀;再在半导体表面淀积SiO2,经刻蚀在平台表面中间及槽壁形成侧墙结构,如图5所示;
步骤5:在P型碳化硅体区4顶层注入N型离子,形成N型碳化硅源区6,如图6所示;
步骤6:在凹槽底部的N型碳化硅源区6一侧以及平台顶层的N型碳化硅源区6中央注入P型离子,形成P型碳化硅体接触区5,如图7所示;
步骤7:在半导体表面淀积或者热氧化生长栅介质层7,如图8所示;
步骤8:在半导体表面刻蚀形成窗口露出P型碳化硅体接触区5和部分N型碳化硅源区6,并在P型碳化硅体接触区5和部分N型碳化硅源区6的上表面蒸发金属并退火,形成欧姆合金层9,如图9所示;
步骤9:在半导体背面蒸发金属,形成金属集电极12,如图10所示;
步骤10:在栅介质层7上表面淀积并刻蚀形成多晶硅栅8,如图11所示;
步骤11:在半导体正面淀积层间介质层10,在半导体表面的层间介质层10上形成窗口露出欧姆合金层9;
步骤12:通过淀积和刻蚀工艺,在半导体表面形成金属发射极11,如图12所示。
以N型碳化硅绝缘栅双极型晶体管为例对本发明器件的工作原理进行说明,如图14所示,当栅极电压与发射极电压差值达到平面栅和沟槽栅的开启电压时,此时在发射极与N型外延层之间会形成电子沟道。若金属集电极12为高电位,金属发射极11为低电位,并且二者之间的电压差大于3V的话,电子e-会通过图中水平沟道以及垂直沟道从金属发射极1进入N-碳化硅漂移区3,同时空穴h+也由金属集电极12进入N-碳化硅漂移区3。相比于传统的SiC IGBT器件,本发明结构在沟道数量上更具优势,因而提高了电子e-注入到漂移区的数量,由于N-碳化硅漂移区3要保持电中性,所以注入的电子数量要与注入的空穴数量相等,电子数量的增多会导致空穴数量的增多,所以N-碳化硅漂移区3中的载流子总数量增多,电导调制效应更显著,增强了正向电流能力,进一步减小碳化硅IGBT的导通损耗。
以上为本发明的优选实施例,通过上述说明内容,本领域技术人员能够在不偏离本发明技术思想的范围内,进行多种多样的变更以及修改。因此本发明的技术性范围并不局限于说明书的内容,凡依本发明申请专利范围所作的均等变化与修饰,皆应属于本发明的涵盖范围。
Claims (6)
1.一种碳化硅绝缘栅双极型晶体管,其特征在于,其元胞结构包括自下而上依次层叠设置的金属集电极(12)、第一导电类型碳化硅衬底(1)、第二导电类型碳化硅缓冲层(2)、第二导电类型碳化硅漂移区(3)、栅介质层(7)、多晶硅栅(8)、层间介质层(10)和发射极金属(11);所述第二导电类型碳化硅漂移区(3)为凸型结构,在第二导电类型碳化硅漂移区(3)的表面两侧分别具有凹槽,两个凹槽之间形成一个凸起的平台;所述平台的表面两侧和所述凹槽的底部分别具有一个第一导电类型碳化硅体区(4),每个第一导电类型碳化硅体区(4)中具有相互独立且彼此接触的第一导电类型碳化硅体接触区(5)和第二导电类型碳化硅源区(6),其中:平台表面两侧的第一导电类型碳化硅体区(4)的顶层具有设置在第一导电类型碳化硅体接触区(5)两侧的第二导电类型碳化硅源区(6),凹槽底部的第一导电类型碳化硅体区(4)的顶层具有设置在第一导电类型碳化硅体接触区(5)一侧的第二导电类型碳化硅源区(6);每个第一导电类型碳化硅体区(4)中的第一导电类型碳化硅体接触区(5)及部分第二导电类型碳化硅源区(6)的上表面设置有欧姆合金层(9);凹槽底部表面及其槽壁表面以及平台上表面设置有与第二导电类型碳化硅漂移区(3)、第一导电类型碳化硅体区(4)和第二导电类型碳化硅源区(6)相接触的栅介质层(7),栅介质层(7)的上表面设置有多晶硅栅(8),栅介质层(7)和多晶硅栅(8)构成栅极结构;发射极金属(11)设置在欧姆合金层(9)上方且与之相接触,且发射极金属(11)与栅极结构之间通过层间介质层(10)相隔离。
2.根据权利要求1所述的一种碳化硅绝缘栅双极型晶体管,其特征在于:第一导电类型碳化硅为P型碳化硅,第二导电类型碳化硅为N型碳化硅。
3.根据权利要求1所述的一种碳化硅绝缘栅双极型晶体管,其特征在于:第一导电类型碳化硅为N型碳化硅,第二导电类型碳化硅为P型碳化硅。
4.一种碳化硅绝缘栅双极型晶体管的制作方法,其特征在于,包括如下步骤:
步骤1:在第一导电类型碳化硅衬底(1)上依次制作第二导电类型碳化硅缓冲层(2)和第二导电类型碳化硅漂移区(3);
步骤2:在第二导电类型碳化硅漂移区(3)表面两侧刻蚀形成凹槽,两个凹槽之间形成一个凸起的平台;
步骤3:通过离子注入工艺,在第二导电类型碳化硅漂移区(3)的凹槽底部及平台表面两侧形成第一导电类型碳化硅体区(4);
步骤4:通过顺次淀积多晶硅及介质层和刻蚀工艺、在平台表面中间及槽壁形成侧墙结构;
步骤5:通过沟道自对准工艺和离子注入工艺,在第一导电类型碳化硅体区(4)顶层形成第二导电类型碳化硅源区(6);
步骤6:通过离子注入工艺,在凹槽底部的第二导电类型碳化硅源区(6)一侧以及平台顶层的第二导电类型碳化硅源区(6)中央形成第一导电类型碳化硅体接触区(5);
步骤7:通过淀积或者热氧化工艺,在第一导电类型碳化硅体区(4)、第一导电类型碳化硅体接触区(5)和第二导电类型碳化硅源区(6)的上表面形成栅介质层(7);
步骤8:通过刻蚀、淀积及退火工艺,在半导体表面形成窗口露出第一导电类型碳化硅体接触区(5)和部分第二导电类型碳化硅源区(6),并在第一导电类型碳化硅体接触区(5)和部分第二导电类型碳化硅源区(6)的上表面制作欧姆合金层(9);
步骤9:通过淀积工艺,在半导体背面形成金属集电极(12);
步骤10:通过淀积和刻蚀工艺,在栅介质层(7)上表面形成多晶硅栅(8);
步骤11:通过淀积和刻蚀工艺,在半导体正面淀积层间介质层(10),在半导体表面的层间介质层(10)上形成窗口露出欧姆合金层(9);
步骤12:通过淀积和刻蚀工艺,在半导体表面形成金属发射极(11)。
5.根据权利要求4所述的一种碳化硅绝缘栅双极型晶体管的制作方法,其特征在于:第一导电类型碳化硅为P型碳化硅,第二导电类型碳化硅为N型碳化硅。
6.根据权利要求4所述的一种碳化硅绝缘栅双极型晶体管的制作方法,其特征在于:第一导电类型碳化硅为N型碳化硅,第二导电类型碳化硅为P型碳化硅。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1117176A (ja) * | 1997-06-24 | 1999-01-22 | Hitachi Ltd | 炭化けい素半導体装置 |
CN103928516A (zh) * | 2013-01-14 | 2014-07-16 | 三星电子株式会社 | 具有双平行沟道结构的半导体器件及其制造方法 |
CN206672940U (zh) * | 2017-03-23 | 2017-11-24 | 深圳基本半导体有限公司 | 一种沟槽栅金属氧化物场效应晶体管 |
WO2017208734A1 (ja) * | 2016-06-03 | 2017-12-07 | 富士電機株式会社 | 半導体装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6526591B2 (ja) * | 2016-03-16 | 2019-06-05 | 株式会社東芝 | 半導体装置 |
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WO2017208734A1 (ja) * | 2016-06-03 | 2017-12-07 | 富士電機株式会社 | 半導体装置 |
CN206672940U (zh) * | 2017-03-23 | 2017-11-24 | 深圳基本半导体有限公司 | 一种沟槽栅金属氧化物场效应晶体管 |
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