WO2024060259A1 - 半导体器件、其制备方法、功率转换电路及车辆 - Google Patents

半导体器件、其制备方法、功率转换电路及车辆 Download PDF

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Publication number
WO2024060259A1
WO2024060259A1 PCT/CN2022/121112 CN2022121112W WO2024060259A1 WO 2024060259 A1 WO2024060259 A1 WO 2024060259A1 CN 2022121112 W CN2022121112 W CN 2022121112W WO 2024060259 A1 WO2024060259 A1 WO 2024060259A1
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type semiconductor
semiconductor region
trench
region
epitaxial layer
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PCT/CN2022/121112
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English (en)
French (fr)
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滨田公守
胡飞
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华为数字能源技术有限公司
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Priority to CN202280008428.3A priority Critical patent/CN118077064A/zh
Priority to PCT/CN2022/121112 priority patent/WO2024060259A1/zh
Publication of WO2024060259A1 publication Critical patent/WO2024060259A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method thereof, a power conversion circuit and a vehicle.
  • SiC material has advantages over silicon (Si) material such as wide bandgap, high critical breakdown electric field, high thermal conductivity and high electron saturation drift velocity.
  • Metal-oxide semiconductors made of SiC material Field-effect transistors metal-oxide-semiconductor field-effect transistor, MOSFET
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • IGBT insulated gate bipolar transistor
  • SiC MOSFET has been used in some application scenarios such as automotive micro controller unit. , MCU), vehicle battery charger (on-board battery charger, OBC) and other fields to replace Si IGBT.
  • SiC MOSFET devices with trench gate structures embed the gate into the SiC body, causing the conductive channel of the device to shift from the plane direction to the vertical direction, thus significantly reducing the unit cell size of the device.
  • the size greatly increases the conductive channel density of the device, which can significantly reduce the on-resistance of the chip and improve the flow capacity.
  • the trench gate structure has become the mainstream technology direction of future devices.
  • the abscissa represents the cell size
  • the ordinate represents the resistance.
  • the cell size of the SiC MOSFET device can be reduced, the conductive channel density can be increased, and the channel area resistance can be reduced.
  • the current flow width of the JFET area will also decrease, causing the resistance of the JFET area to increase.
  • the overall conduction resistance of the SiC MOSFET device will increase, reducing device performance and increasing chip loss.
  • the gate dielectric layer at the bottom and corners of the trench gate structure will withstand extremely high electric field intensity when the device is operating. It is a weak point for electric field breakdown and can easily cause the device to fail. Long-term operating reliability fails, so how to effectively shield the gate dielectric layer from high electric field stress has become the key to high robustness/reliability design of the device.
  • This application provides a semiconductor device, its preparation method, a power conversion circuit and a vehicle, which are used to reduce the total on-resistance of the device, improve the robustness of the device, improve device performance, and reduce device loss.
  • the present application provides a semiconductor device, including: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source and a drain.
  • the epitaxial layer may include a first P-type semiconductor region.
  • the trench structure is disposed in the epitaxial layer, and in a third direction perpendicular to the plane of the semiconductor substrate, the trench structure contacts the first P-type semiconductor region. The projection of the first P-type semiconductor region in the third direction may cover the trench structure.
  • the trench structure may specifically include a plurality of first trenches and a second trench, each of the plurality of first trenches extending in a first direction parallel to a plane where the semiconductor substrate is located, and in a parallel direction.
  • the second trenches are arranged at intervals in the second direction of the plane of the semiconductor substrate, the second trenches extend along the second direction, and the second trenches are intersected with each of the plurality of first trenches and are in communication with each other,
  • the main function of the second trench is to connect the first trenches.
  • the first direction, the second direction and the third direction are arranged to be perpendicular to each other.
  • the gate electrode is filled and disposed in the trench structure through the gate dielectric layer.
  • Each portion of the gate electrode disposed in the plurality of first trenches extends along the first direction.
  • the portion of the gate electrode disposed in the second trenches extends along the second direction. extends and is used to connect various parts of the gate extending along the first direction.
  • the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region and a source region which are sequentially provided on the semiconductor substrate; the first P-type semiconductor region may be provided on In the first N-type semiconductor region, in the third direction, the trench structure may extend into the first N-type semiconductor region.
  • the existence of the trench structure causes the gate to be embedded inside the epitaxial layer of the material, and the gate forms the trench gate structure of the SiC MOSFET device through the gate dielectric layer and the second P-type semiconductor region, making the semiconductor device provided by the embodiment of the present application SiC MOSFET with trench gate structure.
  • the interlayer dielectric layer is disposed on the gate electrode and covers the gate electrode.
  • the source electrode is disposed on the interlayer dielectric layer, that is, the source electrode covers the entire interlayer dielectric layer.
  • the drain electrode is disposed on a side of the semiconductor substrate away from the epitaxial layer, that is, the drain electrode covers the side of the semiconductor substrate where the epitaxial layer is not disposed.
  • a contact hole extending along the second direction can be provided in the interlayer dielectric layer.
  • the projection of the contact hole in the third direction and the gate electrode can not overlap each other, and then the contact hole and the gate electrode do not overlap each other.
  • the contact hole can expose part of the epitaxial layer, for example, the contact hole can expose part of the source region, so that the source contacts the source region through the contact hole, and the source can be connected to the first P-type semiconductor region.
  • the gate control channel When the gate control channel is turned on, signals can be transmitted between the source and the drain.
  • the portions of the two sidewalls of each first trench in the trench structure that are oppositely arranged in the second direction are channel.
  • the extension direction of the contact hole provided in the interlayer dielectric layer is the second direction
  • the extension direction of each first trench of the trench structure is the first direction
  • the extension direction of the contact hole is perpendicular to each other, that is, the contact hole is placed in a direction perpendicular to the first trench.
  • the trench structure array density of the semiconductor device provided by the embodiment of the present application can be much higher than the trench structure array density of the device structure in the prior art, thereby increasing the channel density of the SiC MOSFET and significantly reducing the conduction of the device. Pass the total resistance, improve device performance and reduce device loss.
  • the SiC MOSFET device when the SiC MOSFET device is working, a voltage will be loaded on the source. Since the first P-type semiconductor region is conductive to the source, the voltage loaded on the source will be input into the first P-type semiconductor region, so that the first P-type semiconductor region also has a corresponding voltage, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.
  • the SiC MOSFET provided in the embodiment of the present application when the SiC MOSFET provided in the embodiment of the present application is applied to an electronic device, its source can be grounded and its drain can be connected to other components. Then the voltage of the source of the SiC MOSFET is the ground voltage (0V). Since the first P-type semiconductor region is connected to the source, the voltage of the first P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thus improving the robustness of the device operation.
  • the SiC MOSFET provided in the embodiment of the present application when the SiC MOSFET provided in the embodiment of the present application is applied to an electronic device, its source can also be connected to other components, and its drain can also be connected to other components. Then the voltage of the source of the SiC MOSFET is input by other components. signal voltage. Since the first P-type semiconductor region is conductive to the source, the voltage of the first P-type semiconductor region is also the voltage of the input signal, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the operation efficiency of the device. robustness.
  • the thickness of the first P-type semiconductor region in the third direction may range less than 1 ⁇ m.
  • the thickness of the first P-type semiconductor region in the third direction may range from 0.3 ⁇ m to 0.8 ⁇ m.
  • the semiconductor substrate may be a SiC single crystal substrate doped with pentavalent elements.
  • the epitaxial layer can be made of SiC material grown by epitaxial growth and doped with corresponding impurities.
  • the first N-type semiconductor region may be a partial region of the epitaxial layer formed by epitaxial growth, and the second N-type semiconductor region and the source region may be formed by doping the epitaxial layer using an ion implantation process.
  • the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).
  • the doping concentration of the semiconductor substrate is generally greater than the doping concentration of the second N-type semiconductor region
  • the doping concentration of the second N-type semiconductor region is generally greater than the doping concentration of the first N-type semiconductor region
  • the doping concentration of the source region is generally greater than that of the second N-type semiconductor region.
  • the second P-type semiconductor region and the first P-type semiconductor region may be formed by doping the epitaxial layer using an ion implantation process.
  • the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • the material of the gate electrode may be polysilicon material, or other materials with good conductive properties such as metal (such as W, Al, Ti, Cu, Mo or Pt).
  • the material forming the interlayer dielectric layer may be a dielectric material.
  • the dielectric material includes but is not limited to silicon dioxide (SiO 2 ), silicon oxynitride (SiNO). , silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.
  • the material used to form the source electrode and the drain electrode may be a metal material.
  • the metal material may include W, Al, Ti, Cu, Mo or Pt, etc.
  • a trench structure may be set between two adjacent contact holes, which can make the signal flow faster. Evenly.
  • the structural parameters in each trench structure can be the same, which can ensure that the trench structures are evenly distributed.
  • the number of first trenches may be the same, the trench spacing between the first trenches may be the same, the trench lengths of the first trenches may be the same, and the lengths of the second trenches may be the same.
  • the number of first trenches in the trench structure can be determined according to the needs of the actual application, which is not limited in this application.
  • the number of first trenches in some trench structures can also be made the same, and the number of first trenches in the rest of the trench structures can be different.
  • the number of first trenches in different trench structures may also be different.
  • the number of first trenches in the trench structure can be determined according to the needs of the actual application, which is not limited in this application.
  • the two first trenches at the edge in the trench structure can be defined as the first edge trench and the second edge trench respectively, and the contact hole is formed by the third edge trench.
  • a side of an edge groove facing away from the second edge groove extends along the second direction to a side of the second edge groove facing away from the first edge groove. That is to say, the contact holes are continuous openings, and the first trenches in different trench structures do not communicate with each other.
  • the epitaxial layer may further include: a third P-type semiconductor region and a fourth P-type semiconductor region.
  • the third P-type semiconductor region is disposed on at least one sidewall of the trench structure, and the fourth P-type semiconductor region and the source region are disposed in the same layer.
  • the third P-type semiconductor region is in contact with the first P-type semiconductor region, and the fourth P-type semiconductor region is disposed in one-to-one correspondence with the third P-type semiconductor region and is in contact with each other.
  • the voltage can be input to the first P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region in turn, thereby being able to effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.
  • the second P-type semiconductor region, the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region may be formed by doping the epitaxial layer using an ion implantation process.
  • the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • the doping concentration of the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region is greater than the doping concentration of the second P-type semiconductor region.
  • the doping concentrations of the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region may be the same or similar.
  • at least two of the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region may have different doping concentrations. It should be noted that the doping concentrations of the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region can be determined according to the requirements of the actual application environment, and are not limited here.
  • each first trench in the plurality of first trenches may have first sidewalls and second sidewalls arranged oppositely, and the third P-type semiconductor The regions may be disposed on the first sidewall and the second sidewall of at least one first trench among the plurality of first trenches, that is, the first sidewall and the second sidewall of the at least one first trench, respectively.
  • a third P-type semiconductor region is provided. Furthermore, the third P-type semiconductor regions are all in contact with the first P-type semiconductor region, so that the third P-type semiconductor regions are all connected to the first P-type semiconductor region for signal transmission, and the third P-type semiconductor regions are all in contact with each other. The same voltage as the first P-type semiconductor region.
  • the fourth P-type semiconductor region and the third P-type semiconductor region are in one-to-one correspondence and are arranged in contact, and the fourth P-type semiconductor region is in contact with the corresponding source electrode through the contact hole.
  • the third P-type semiconductor region disposed on the first sidewall corresponds to a fourth P-type semiconductor region
  • the fourth P-type semiconductor region is disposed on the first side of the third P-type semiconductor region away from the first trench. side of the wall.
  • the third P-type semiconductor region provided on the second sidewall is correspondingly provided with a fourth P-type semiconductor region
  • the fourth P-type semiconductor region is provided on the second side of the third P-type semiconductor region away from the first trench. side of the wall.
  • the source is connected to the first P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region that are arranged corresponding to each other in sequence, so that the voltage loaded on the source electrode passes through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence.
  • the semiconductor region is input to the first P-type semiconductor region, so that the first P-type semiconductor region has a voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.
  • multiple third P-type semiconductor regions may be provided, and the first sidewall of each first trench is provided with one third P-type semiconductor region among the plurality of third P-type semiconductor regions. , and the second sidewall of each first trench is also provided with a third P-type semiconductor region among a plurality of third P-type semiconductor regions. That is to say, the first sidewall and the second sidewall of each first trench are respectively provided with third P-type semiconductor regions. Moreover, these third P-type semiconductor regions are all in contact with the first P-type semiconductor region, so that the third P-type semiconductor regions can be connected to the first P-type semiconductor region for signal transmission, then the third P-type semiconductor region Both are the same as the voltage of the first P-type semiconductor region.
  • a plurality of fourth P-type semiconductor regions may be provided, and the plurality of fourth P-type semiconductor regions correspond to the plurality of third P-type semiconductor regions one by one and are arranged in contact with each other.
  • the third P-type semiconductor region provided on the first sidewall corresponds to one of the plurality of fourth P-type semiconductor regions
  • the fourth P-type semiconductor region is provided on the third P-type semiconductor region. area away from a side of the first side wall of the first trench.
  • the third P-type semiconductor region provided on the second sidewall corresponds to one of the plurality of fourth P-type semiconductor regions
  • the fourth P-type semiconductor region is provided on the third P-type semiconductor region. area away from the side of the second sidewall of the first trench.
  • the source is connected to the first P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region that are arranged corresponding to each other in sequence, so that the voltage loaded on the source electrode passes through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence.
  • the semiconductor region is input to the first P-type semiconductor region, so that the first P-type semiconductor region has a voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.
  • multiple source regions may also be provided, and multiple source regions and multiple fourth P-type semiconductor regions located at the same end of the trench structure are alternately provided.
  • a plurality of source regions and a plurality of fourth P-type semiconductor regions located at the first sidewalls of the plurality of first trenches in the same trench structure are alternately arranged.
  • a plurality of source regions and a plurality of fourth P-type semiconductor regions located at the second sidewalls of the plurality of first trenches in the same trench structure are alternately arranged.
  • this application does not limit the width of the fourth P-type semiconductor region along the second direction.
  • the width of the fourth P-type semiconductor region along the second direction can be the same as or similar to the width of the first trench.
  • the width of the source region along the second direction is the same as or similar to the trench spacing between two adjacent first trenches.
  • the width of the fourth P-type semiconductor region along the second direction can also be different from the width of the first trench, which is not limited here.
  • the trench spacing may be less than 1 ⁇ m.
  • the trench spacing ranges from 50nm to 0.5um. It should be noted that when the trench spacing is less than 100nm, the semiconductor device provided by this application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly increase the carrier channel mobility and further reduce The total on-resistance of the device.
  • Fin Field-Effect Transistor Fin Field-Effect Transistor
  • the first trench has a trench length.
  • This application does not limit the trench length.
  • the trench length can be greater than 5um.
  • the first trench has a trench width.
  • This application does not limit the width of the trench.
  • the width of the trench may be less than 1 ⁇ m.
  • the contact hole has a contact width, so that the trench pitch can be no larger than the contact width.
  • the trench spacing can also be made larger than the contact width.
  • the groove spacing and contact width can be determined according to the environmental requirements of the actual application, and are not limited here.
  • the first P-type semiconductor region is formed by using a vertical ion implantation process at the bottom of the trench structure after the channel structure is formed. Therefore, the first P-type semiconductor region is formed in the third direction.
  • the projection can cover the trench structure. Moreover, due to the diffusion of ions during the ion implantation process, the first P-type semiconductor region will diffuse toward the bottom periphery of the trench structure, that is, the orthographic projection edge of the first P-type semiconductor region on the semiconductor substrate is located in the trench.
  • the structure is at the periphery of the orthographic edge of the semiconductor substrate 1 .
  • the orthographic projection shape of the first P-type semiconductor region on the semiconductor substrate 1 is similar to the orthographic projection shape of the trench structure on the semiconductor substrate.
  • the first P-type semiconductor region can also cover the gap between two adjacent first trenches. That is to say, the orthographic projection of the first P-type semiconductor region on the semiconductor substrate 1 also covers the orthographic projection of the gap between two adjacent first trenches in the second direction on the semiconductor substrate.
  • the first P-type semiconductor region can be considered as a planar region extending along the second direction, and the shape of the first P-type semiconductor region can be considered as a rectangle.
  • the projection of the first P-type semiconductor region in the third direction may also cover the third P-type semiconductor region. That is to say, the orthographic projection of the first P-type semiconductor region on the semiconductor substrate not only covers the orthographic projection of the trench structure on the semiconductor substrate, but also covers the orthographic projection of all the third P-type semiconductor regions on the semiconductor substrate. .
  • one trench structure is corresponding to a first P-type semiconductor region. That is to say, if a trench structure is provided, a first P-type semiconductor region is correspondingly provided. If two trench structures are provided, two first P-type semiconductor regions are correspondingly provided. Moreover, there is a gap between the two first P-type semiconductor regions. If multiple trench structures are provided, multiple first P-type semiconductor regions are provided accordingly. Moreover, there is a gap between every two adjacent first P-type semiconductor regions.
  • the second P-type semiconductor region at the two sidewalls of the first trench in the second direction of the trench structure forms the channel region of the SiC MOSFET. Therefore, by increasing Reducing the trench width or reducing the trench spacing can increase the conductive channel density of SiC MOSFET devices and reduce the total on-resistance of SiC MOSFET devices.
  • the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source and a drain.
  • the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, a source region, a first P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. district.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • a plurality of third P-type semiconductor regions are provided, one of the plurality of third P-type semiconductor regions is provided on the first side wall of each first trench, and in each first trench, a third P-type semiconductor region is provided.
  • a third P-type semiconductor region is not provided on the second sidewall of a first trench. That is to say, the third P-type semiconductor region is provided only at the first sidewall of each first trench.
  • these third P-type semiconductor regions are all in contact with the first P-type semiconductor region, so that the third P-type semiconductor regions are connected to the first P-type semiconductor region for signal transmission, and the third P-type semiconductor regions are all connected to the first P-type semiconductor region.
  • the voltages of the first P-type semiconductor regions are the same.
  • a plurality of fourth P-type semiconductor regions are also provided, and the plurality of fourth P-type semiconductor regions correspond to the plurality of third P-type semiconductor regions one by one and are arranged in contact with each other.
  • the third P-type semiconductor region provided on the first side wall corresponds to one of the plurality of fourth P-type semiconductor regions
  • the fourth P-type semiconductor region is provided on the third P-type semiconductor region. area away from a side of the first sidewall of the first trench.
  • the source is connected to the first P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region that are arranged corresponding to each other in sequence, so that the voltage loaded on the source electrode passes through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence.
  • the semiconductor region is input to the first P-type semiconductor region, so that the first P-type semiconductor region has a voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.
  • the epitaxial layer may further include: a fifth P-type semiconductor region, the fifth P-type semiconductor region and the source region are arranged in the same layer, and the fifth P-type semiconductor region is arranged away from the second sidewall of the first trench. One side of the first sidewall, and the fifth P-type semiconductor region is in contact with the source through the contact hole.
  • a plurality of fifth P-type semiconductor regions may be provided, and the plurality of fifth P-type semiconductor regions are provided in one-to-one correspondence with the second sidewalls of each first trench. Furthermore, a plurality of source regions and a plurality of fifth P-type semiconductor regions located on the second sidewall of the first trench are alternately arranged.
  • the fifth P-type semiconductor region may be formed by doping the epitaxial layer using an ion implantation process.
  • the fifth P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • P-type impurities such as boron (B), aluminum (Al) or gallium (Ga).
  • the doping concentration of the fifth P-type semiconductor region may be the same as or similar to the doping concentration of the fourth P-type semiconductor region.
  • a third P-type semiconductor region is provided at the first sidewall of the first trench, and no channel is formed.
  • the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source and a drain.
  • the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, a source region, a first P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. district.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • a plurality of third P-type semiconductor regions are provided, one of the plurality of third P-type semiconductor regions is provided on the first side wall of each first trench, and each third P-type semiconductor region is provided on the first side wall of each first trench.
  • the third P-type semiconductor region is not provided on the second sidewall of a trench. That is to say, the third P-type semiconductor region is provided only at the first sidewall of each first trench.
  • these third P-type semiconductor regions are all in contact with the first P-type semiconductor region, so that the third P-type semiconductor regions are connected to the first P-type semiconductor region for signal transmission, and the third P-type semiconductor regions are all connected to the first P-type semiconductor region.
  • the voltages of the first P-type semiconductor regions are the same.
  • a plurality of fourth P-type semiconductor regions are also provided, and the plurality of fourth P-type semiconductor regions correspond to the plurality of third P-type semiconductor regions one by one and are arranged in contact with each other.
  • the third P-type semiconductor region provided on the first sidewall corresponds to one of the plurality of fourth P-type semiconductor regions
  • the fourth P-type semiconductor region is provided on the third P-type semiconductor region. area away from a side of the first side wall of the first trench.
  • the source is connected to the first P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region that are arranged corresponding to each other in sequence, so that the voltage loaded on the source electrode passes through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence.
  • the semiconductor region is input to the first P-type semiconductor region, so that the first P-type semiconductor region has a voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.
  • the fourth P-type semiconductor region is provided only at the first sidewall of the first trench, and the source regions are provided at the second sidewall of the first trench.
  • the positions of the first sidewall and the second sidewall of the first trench can also be interchanged, that is, multiple third P-type semiconductors can be provided on the second sidewall of the first trench.
  • a third P-type semiconductor region is provided in the region, and the third P-type semiconductor region is not provided on the first sidewall of each first trench.
  • the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source and a drain.
  • the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, a source region, a first P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. district.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • At least one end of the second groove may protrude from the first groove located at the edge of the plurality of first grooves, and in the second direction, the second groove may have a third oppositely disposed
  • the third sidewall and the fourth sidewall, the third P-type semiconductor region may be disposed on the third sidewall and/or the fourth sidewall of the second trench.
  • both ends of the second trench may extend from the first trench located at the edge of the plurality of first trenches
  • the third P-type semiconductor region may be disposed on the third sidewall of the second trench.
  • the fourth sidewall that is to say, the third sidewall and the fourth sidewall of the second trench are respectively provided with third P-type semiconductor regions.
  • the third P-type semiconductor regions are all in contact with the first P-type semiconductor region, so that the third P-type semiconductor regions are all connected to the first P-type semiconductor region for signal transmission, and the third P-type semiconductor regions are all in contact with each other.
  • the fourth P-type semiconductor region and the third P-type semiconductor region correspond one to one and are arranged in contact.
  • the third P-type semiconductor region provided on the third sidewall corresponds to a fourth P-type semiconductor region
  • the fourth P-type semiconductor region is provided on the third side of the third P-type semiconductor region away from the second trench. side of the wall.
  • the third P-type semiconductor region provided on the fourth sidewall is provided with a fourth P-type semiconductor region correspondingly, and the fourth P-type semiconductor region is provided on the fourth side of the third P-type semiconductor region away from the second trench. side of the wall.
  • the voltage can be input to the first P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence, so that the first P-type semiconductor region has a voltage, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, This improves the robustness of device operation.
  • the epitaxial layer may further include: a fifth P-type semiconductor region, the fifth P-type semiconductor region and the source region are arranged in the same layer, and the fifth P-type semiconductor region may be arranged on the second sidewall of the first trench.
  • the fifth P-type semiconductor region can also be disposed on a side of the first sidewall of the first trench facing away from the second sidewall, and the fifth P-type semiconductor region is connected to the source through the contact hole. touch.
  • a plurality of fifth P-type semiconductor regions may be provided, and the plurality of fifth P-type semiconductor regions may be provided in one-to-one correspondence with the first sidewall and the second sidewall of each first trench. Furthermore, a plurality of source regions and a plurality of fifth P-type semiconductor regions located on the first sidewall of the first trench are alternately arranged, and a plurality of source regions and a plurality of fifth P-type semiconductor regions located on the second sidewall of the first trench are alternately arranged. Type semiconductor regions are arranged alternately.
  • the fifth P-type semiconductor region may be formed by doping the epitaxial layer using an ion implantation process.
  • the fifth P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • P-type impurities such as boron (B), aluminum (Al) or gallium (Ga).
  • the doping concentration of the fifth P-type semiconductor region may be the same as or similar to the doping concentration of the fourth P-type semiconductor region.
  • a third P-type semiconductor region is provided at the third sidewall and the fourth sidewall of the second trench, and no channel is formed.
  • the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source and a drain.
  • the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, a source region, a first P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. district.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the first trenches arranged along the first direction penetrate each other.
  • the first edge grooves in the two adjacent groove structures on the left and right are arranged along the first direction, and the two first edge grooves penetrate each other.
  • the second edge grooves in the two adjacent groove structures on the left and right are arranged along the first direction, and the two second edge grooves penetrate each other.
  • a first groove in the middle of the left groove structure may also communicate with a first groove in the middle of the right groove structure.
  • the contact hole may be divided into a plurality of sub-contact holes spaced apart from each other, and at least one first through-going trench is provided between two adjacent sub-contact holes in the same contact hole.
  • This application does not limit the number of sub-contact holes into which a contact hole is divided. For example, it may be two, three, four or more.
  • the present application does not limit the number of through-going first trenches provided between two adjacent sub-contact holes in the same contact hole. For example, it may be one, two, three, four or more. . This can improve the design freedom of contact holes and improve the flow uniformity of SiC MOSFET devices.
  • the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source and a drain.
  • the epitaxial layer may include: a third N-type semiconductor region, a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, a source region, a first P-type semiconductor region, a third P-type semiconductor region and a fourth P-type semiconductor region.
  • This embodiment is a variation of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the third N-type semiconductor region may be disposed between the first N-type semiconductor region and the semiconductor substrate. Due to the provision of the third N-type semiconductor region, the thickness of the first P-type semiconductor region in the third direction in the epitaxial layer can be made thicker. For example, the thickness of the first P-type semiconductor region in the third direction can be made thicker. The thickness setting is greater than 1um.
  • the third N-type semiconductor region may be SiC doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).
  • N-type impurities such as nitrogen (N), phosphorus (P) or arsenic (As).
  • the doping concentration of the third N-type semiconductor region may be smaller than the doping concentration of the first N-type semiconductor region.
  • inventions of the present application also provide a method for preparing a semiconductor device.
  • the preparation method may include the following steps: epitaxially growing an epitaxial layer on an N-type semiconductor substrate; etching the epitaxial layer to form a trench structure;
  • the trench structure includes a plurality of first trenches and a second trench, each of the plurality of first trenches extending in a first direction parallel to a plane of the semiconductor substrate, and in a direction parallel to the plane of the semiconductor substrate.
  • the second trenches are arranged at intervals in the second direction of the plane where the substrate is located, the second trenches extend along the second direction, and the second trenches are intersected with each of the plurality of first trenches and are in communication with each other; in the trenches A first P-type semiconductor region is formed at the bottom of the trench structure, and the projection of the first P-type semiconductor region in the third direction covers the trench structure; a gate dielectric layer and a gate electrode are sequentially formed in the trench structure; a covering epitaxial layer is formed on the gate electrode an interlayer dielectric layer; the interlayer dielectric layer is etched to form a contact hole extending in the second direction, the contact hole exposes part of the epitaxial layer, and the projection of the contact hole in the third direction does not overlap with the gate electrode; The first direction, the second direction and the third direction are arranged to intersect with each other; a source electrode is formed on the interlayer dielectric layer, and the source electrode contacts the epitaxial layer exposed by the contact hole through the contact hole;
  • the preparation method may further include: before sequentially forming a gate dielectric layer and a gate electrode in the trench structure, using an inclined ion implantation process on at least one side wall of the trench structure to form a third P-type semiconductor region in contact with the first P-type semiconductor region; using an ion implantation process to form a fourth P-type semiconductor region in the epitaxial layer that is arranged in the same layer as the source region.
  • epitaxially growing an epitaxial layer on an N-type semiconductor substrate may include the following steps: using an epitaxial process, epitaxially growing SiC material doped with N-type impurities on an N-type SiC semiconductor substrate to form an epitaxial layer.
  • the present application does not limit the specific value of the thickness of the epitaxial layer. In practical applications, the specific value of the thickness of the epitaxial layer can be determined according to the requirements of the actual application environment.
  • the preparation method may further include: using an ion implantation process to perform ion implantation in part of the epitaxial layer to sequentially form a second N-type The semiconductor region, the second P-type semiconductor region and the source region, and the region in the epitaxial layer that has not been ion implanted form the first N-type semiconductor region.
  • a region of the epitaxial layer that has not been ion implanted forms a first N-type semiconductor region.
  • ions are implanted in part of the epitaxial layer to form a second N-type semiconductor region, a second P-type semiconductor region and a source region.
  • the first N-type semiconductor region is formed in a region where ions are not implanted in the first epitaxial layer.
  • Semiconductor region may include the following steps:
  • N-type impurities are doped on the surface of the epitaxial layer to form a second N-type semiconductor region.
  • an ion implantation process is used to dope P-type impurities on the surface of the epitaxial layer to form a second P-type semiconductor region.
  • an ion implantation process is used to perform N-type impurity doping on the surface of the epitaxial layer to form a source region, and P-type impurity doping is performed on the surface of the epitaxial layer at the first sidewall and the second sidewall of the first trench.
  • the fourth P-type semiconductor region is formed in the same layer as the source region.
  • the second N-type semiconductor region, the second P-type semiconductor region, the source region and the fourth P-type semiconductor region are formed in part of the epitaxial layer.
  • the first N-type semiconductor region is formed in the area where the ions are not implanted using the ion implantation process.
  • etching the epitaxial layer to the first N-type semiconductor region to form a trench structure in the epitaxial layer may include the following steps:
  • the trench mask can be a mask formed using photoresist or a hard mask. Through this trench mask, there is no need to form the epitaxial layer of the trench structure. The areas in the epitaxial layer are covered, while the areas in the epitaxial layer where the trench structure needs to be formed are exposed.
  • an appropriate etching process is selected from the etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the areas of the epitaxial layer that are not covered by the trench mask are etched until The etching is stopped when the first N-type semiconductor region is exposed and the first P-type semiconductor region is exposed, so as to form a trench structure composed of a plurality of first trenches and second trenches in the epitaxial layer.
  • the etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process
  • the first P-type semiconductor region in order to form the first P-type semiconductor region, is formed at the bottom of the trench structure. In the third direction, the first P-type semiconductor region covers the trench structure, which may include the following: step:
  • a vertical ion implantation process is used to dope P-type impurities into the bottom of the trench structure to form a first P-type semiconductor region that is consistent with the bottom pattern of the trench structure or is a planar region.
  • This application does not limit the thickness of the first P-type semiconductor region (that is, the thickness in the third direction). In practical applications, the specific value of the thickness of the first P-type semiconductor region can be determined according to the requirements of the actual application environment.
  • an oblique ion implantation process is used to form on the first sidewall and the second sidewall of each first trench along the first direction respectively.
  • the third P-type semiconductor region contacted by the first P-type semiconductor region may include the following steps:
  • P-type impurities are doped on the surfaces of the first sidewall and the second sidewall of each first trench to form third P-type semiconductor regions that are in contact with the first P-type semiconductor region.
  • forming the gate dielectric layer in the trench structure may include the following steps: using an oxidation process to oxidize the surface of the trench structure, so that the surface of the trench structure forms gate dielectric layer.
  • forming the gate electrode in the trench structure in which the gate dielectric layer is formed may include the following steps:
  • a deposition process is used to deposit polysilicon material on the entire epitaxial layer forming the trench structure, and the polysilicon material fills the trench structure. After filling the trench structure with the polysilicon material, the entire epitaxial layer covers the polysilicon material. film layer. Then, an appropriate etching process is selected from etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the polysilicon material area not covered by the trench mask is etched until the etching process is completed. Stop etching until the source region and the fourth P-type semiconductor region are exposed to form a gate electrode.
  • etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process
  • forming an interlayer dielectric layer covering the entire epitaxial layer on the gate may include the following steps: using a deposition process to deposit the interlayer dielectric layer on the entire epitaxial layer, And the interlayer dielectric layer covers the entire epitaxial layer.
  • etching the interlayer dielectric layer to form a contact hole extending along the second direction may include the following steps:
  • a contact hole mask is formed on the epitaxial layer (the contact hole mask may be a mask formed by photoresist or a hard mask plate), and the contact hole mask is used to cover the area where the contact hole does not need to be formed, while exposing the area where the contact hole needs to be formed.
  • a suitable etching process is selected from etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the area of the interlayer dielectric layer not covered by the contact hole mask is etched to expose part of the source region, such as the part of the source region located on both sides of the gate in the first direction, and the part of the fourth P-type semiconductor region located on both sides of the gate is exposed.
  • the source electrode in order to form the source electrode and the drain electrode, the source electrode is formed on the interlayer dielectric layer, and the source electrode is contacted with the source region through the contact hole.
  • forming a drain electrode on the side of the semiconductor substrate away from the epitaxial layer may include the following steps:
  • metal materials are deposited on the interlayer dielectric layer to form the source.
  • the contact hole is filled with metal material, so that the source electrode contacts the source area through the metal material filled in the contact hole.
  • a deposition process may be used to deposit a metal material on the side of the semiconductor substrate away from the epitaxial layer to form the drain electrode.
  • a deposition process may be used to deposit a metal material on the side of the semiconductor substrate away from the epitaxial layer to form the drain electrode.
  • the material forming the source electrode and the drain electrode may be a metal material.
  • the metallic material may include W, Al, Ti, Cu, Mo, or Pt.
  • an embodiment of the present application further provides a power conversion circuit, which may be an AC-DC conversion circuit and/or a DC-DC conversion circuit.
  • the power conversion circuit may include: a circuit board and one or more semiconductor devices, and the semiconductor device is connected to the circuit board.
  • the semiconductor device may be a semiconductor device such as the first aspect or various possible designs of the first aspect, or a semiconductor device prepared using the second aspect or various possible designs of the second aspect. Since the performance of the above-mentioned semiconductor device is good, the performance of the power conversion circuit including the above-mentioned semiconductor device is also good.
  • the principle of solving the problem by the power conversion circuit is similar to the principle that the aforementioned semiconductor device can solve the problem, so the technical effect of the power conversion circuit can refer to the technical effect of the aforementioned semiconductor device, and the repeated parts will not be repeated.
  • embodiments of the present application further provide a vehicle, which may include a power conversion circuit.
  • the power conversion circuit may be the power conversion circuit in the third aspect or various possible designs of the third aspect. Since the performance of the above-mentioned power conversion circuit is better, the circuit performance of the vehicle including the above-mentioned power conversion circuit is also better. Moreover, the principle of solving problems of this vehicle is similar to the principle of solving problems of the aforementioned power conversion circuit. Therefore, the technical effect of this vehicle can be referred to the technical effect of the aforementioned power conversion circuit, and the repeated parts will not be repeated.
  • Figure 1 shows the relationship between the channel area resistance and JFET area resistance in SiC MOSFET devices
  • FIG2a is a schematic diagram of the structure of an electric vehicle provided by an embodiment of the present application.
  • Figure 2b is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 3 is a schematic top structural view of a semiconductor device provided by an embodiment of the present application.
  • Figure 4 is a schematic cross-sectional structural diagram along the tangential direction A1A2 in Figure 3;
  • Figure 5 is a schematic cross-sectional structural diagram along the tangential direction A3A4 in Figure 3;
  • Figure 6a is a schematic cross-sectional structural diagram along the tangential direction V1V2 in Figure 3;
  • Figure 6b is another sectional structural schematic diagram along the tangent direction V1V2 in Figure 3;
  • Figure 7 is a schematic cross-sectional structural diagram along the tangent direction V3V4 in Figure 3;
  • Figure 8 is a schematic diagram of the partial three-dimensional structure in Figure 3.
  • Figure 9 is a schematic three-dimensional structural diagram of the semiconductor device shown in Figure 8 when no interlayer dielectric layer and source electrode are provided;
  • Figure 10 is a schematic three-dimensional structural diagram of the trench structure in the semiconductor device shown in Figure 8.
  • Figure 11 is some schematic diagrams of the semiconductor device provided by the embodiment of the present application when generating conduction current
  • Figure 12 is a schematic cross-sectional structural diagram along the C1C2 tangent direction in Figure 11;
  • Figure 13 is some flowcharts of methods for manufacturing semiconductor devices provided by embodiments of the present application.
  • Figures 14a to 14i are respectively structural schematic diagrams of a process for preparing a semiconductor device provided by embodiments of the present application.
  • Figure 15 is a schematic three-dimensional structural diagram of a semiconductor device provided by another embodiment of the present application.
  • FIG16 is a schematic diagram of a three-dimensional structure of the semiconductor device shown in FIG15 when an interlayer dielectric layer and a source electrode are not provided;
  • Figure 17 is a schematic structural diagram of the trench structure in the semiconductor device shown in Figure 15;
  • Figure 18 is a schematic three-dimensional structural diagram of a semiconductor device provided by another embodiment of the present application.
  • Figure 19 is a schematic three-dimensional structural diagram of the semiconductor device shown in Figure 18 when no interlayer dielectric layer and source electrode are provided;
  • Figure 20 is a schematic three-dimensional structural diagram of the trench structure in the semiconductor device shown in Figure 18;
  • Figure 21 is a schematic top structural view of a semiconductor device provided by another embodiment of the present application.
  • Figure 22 is a schematic cross-sectional structural diagram along the tangential direction B1B2 in Figure 21;
  • Figure 23 is a schematic cross-sectional structural diagram along the tangential direction B3B4 in Figure 21;
  • FIG24a is a schematic cross-sectional view of the structure along the tangent line X1X2 in FIG21;
  • Figure 24b is another sectional structural schematic diagram along the tangential direction X1X2 in Figure 21;
  • Figure 25 is a schematic cross-sectional structural diagram along the tangential direction X3X4 in Figure 21;
  • Figure 26 is a schematic diagram of the partial three-dimensional structure in Figure 21;
  • Figure 27 is a schematic three-dimensional structural diagram of the semiconductor device shown in Figure 26 when no interlayer dielectric layer and source electrode are provided;
  • Figure 28 is a schematic diagram of a partial three-dimensional structure of the semiconductor device shown in Figure 27;
  • Figure 29 is a schematic top structural view of a semiconductor device provided by another embodiment of the present application.
  • Figure 30 is a schematic top structural view of a semiconductor device provided by another embodiment of the present application.
  • FIG. 31 is a schematic three-dimensional structural diagram of a semiconductor device provided by another embodiment of the present application.
  • connection in the embodiments of this application refers to electrical connection, and the connection between two electrical components may be a direct or indirect connection between two electrical components.
  • a and B can be connected directly, or A and B can be connected indirectly through one or more other electrical components.
  • a and B can be connected, or A and C can be connected directly.
  • C and B are directly connected, and A and B are connected through C.
  • the semiconductor device provided by the embodiment of the present application can be applied in vehicles (such as electric vehicles), for example, can be used in vehicle-mounted micro control units (micro controller unit, MCU), vehicle-mounted battery charger (on-board battery charger, OBC), etc. It should be noted that the semiconductor devices proposed in the embodiments of the present application are intended to include, but are not limited to, applications in these and any other suitable types of devices. The following description takes the vehicle as an electric vehicle as an example.
  • FIG 2a is a schematic structural diagram of an electric vehicle provided by an embodiment of the present application.
  • the electric vehicle 010 may include a power conversion circuit 0110 and a battery 012.
  • the power conversion circuit 0110 may include an alternating current (AC)-direct current (DC) conversion circuit and a DC-DC conversion circuit.
  • the power conversion circuit 0110 may also be called an inverter. device.
  • the electric vehicle 010 when the electric vehicle is charging, the electric vehicle 010 may be connected to a three-phase power grid and receive three-phase AC power provided by the three-phase power grid.
  • the AC-DC conversion circuit can convert three-phase alternating current into direct current, and by controlling the power of the DC-DC conversion circuit in the power conversion circuit 0110
  • the operation of the switching tube allows the DC-DC conversion circuit to regulate the voltage of the direct current output by the AC-DC conversion circuit, thereby providing a voltage-adapted direct current to the battery 012, so that the battery 012 can store the direct current and realize the charging function.
  • the power conversion circuit 0110 may also be a DC-DC conversion circuit, and the electric vehicle 010 may also include a load 013, which may be an on-board equipment, power system, etc. of the electric vehicle 010.
  • the power conversion circuit 0110 can adjust the voltage of the DC power output by the battery and output it to the load 013, thereby providing voltage adaptation for the load 013. of direct current.
  • the semiconductor device provided by the embodiment of the present application is a MOSFET with a trench gate structure, which can increase the conduction channel density without increasing the JFET area resistance, thereby reducing the total conduction resistance, thereby improving device performance and reducing device loss.
  • the semiconductor device provided by the embodiment of the present application can be applied to the power conversion circuit 0110 of the vehicle as a power switch transistor in the AC-DC converter and/or DC-DC converter. Since the semiconductor device provided by the embodiments of the present application has better device performance, when the semiconductor device is used in an AC-DC converter and/or a DC-DC converter, the AC-DC converter and/or DC-DC converter can be improved. converter performance and reduced driving losses, thereby improving the performance of the entire circuit and reducing driving losses.
  • the semiconductor device provided by the embodiment of the present application can also be widely used in various electronic devices, for example, it can be used in electronic devices with logic devices or memory devices.
  • the electronic device may be a smartphone, a smart TV, a laptop, a personal digital assistant (PDA), a wearable device with wireless communication functions (such as a smart watch, smart glasses, a smart bracelet), etc.
  • PDA personal digital assistant
  • the semiconductor devices proposed in the embodiments of the present application are intended to include, but are not limited to, applications in these and any other suitable types of electronic equipment.
  • FIG. 2b is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device 0100 provided by the embodiment of the present application includes a power conversion circuit 0110 and a load module 0120.
  • the power conversion circuit 0110 is electrically connected to the load module 0120.
  • electronic device 0100 may be any electrically powered device.
  • PDA personal digital assistant
  • wearable devices with wireless communication functions such as smart watches, smart glasses, smart bracelets
  • vehicle-mounted micro control units micro controller unit
  • MCU vehicle-mounted micro control units
  • OBC on-board battery charger
  • the power conversion circuit 0110 may be a direct current (DC)-DC power conversion circuit, which is used to step up or step down the DC power and then output the DC power to power the load module 0120.
  • the power conversion circuit 0110 can convert the DC power (eg 48V) output by the power supply 0200 into DC power for all types of load modules 0120, and output it to the load module 0120 for the load module 0120 to operate.
  • the power supply 0200 can be any device or component that can output direct current.
  • the power supply 0200 can be a battery (such as a battery), and the power conversion circuit 0110 can receive the battery voltage provided by the battery.
  • the load module 0120 can be any functional module that uses direct current.
  • the load module 0120 can be a processor, a chip, etc.
  • the power conversion circuit 0110 may include a DC-DC converter 0111.
  • the MOSFET in the DC-DC converter 0111 works at a certain switching frequency, so that the DC-DC converter 0111 converts the DC power of the power supply 0200 into a step-up or step-down process, and then outputs it to the load module 0120.
  • the DC-DC converter can be: Buck converter, Boost converter, half-bridge converter, full-bridge converter and inductor-inductor (inductor-inductor). -capacitor, LLC) resonant converter, etc.
  • the semiconductor device provided by the embodiment of the present application is a MOSFET with a trench gate structure, which can increase the conduction channel density without increasing the JFET area resistance, thereby reducing the total conduction resistance, thereby improving device performance and reducing device loss.
  • the semiconductor device provided by the embodiment of the present application can be applied to the DC-DC converter 0111 as a MOSFET in the DC-DC converter 0111. Since the semiconductor device provided by the embodiment of the present application has better device performance, when the semiconductor device is used in the MOSFET in the DC-DC converter 0111, the performance of the DC-DC converter 0111 can be improved and the driving loss can be reduced, thereby improving performance of the entire electronic device and reduced drive losses.
  • the materials of the semiconductor substrate 1 and the epitaxial layer 100 may be SiC, and then the semiconductor device provided by the embodiments of this application is a SiC MOSFET.
  • N or P in the layers and regions prefixed with N or P, it means that electrons or holes are the majority carriers respectively.
  • “+” marked on N or P indicates that the doping concentration is higher than that of the layer or region not marked with +, and the greater the number of “+”s, the higher the doping concentration.
  • N or P containing the same number of "+” means that the doping concentration is similar and is not limited to the same doping concentration.
  • “-" marked with N or P indicates that the doping concentration is lower than that of the layer or region not marked with -, and the greater the number of "-”s, the lower the doping concentration.
  • N or P containing the same number of "-” indicates similar doping concentration and is not limited to the same doping concentration.
  • the comparison of the doping concentrations of the two regions in this application only refers to the comparison of the concentrations of the impurities doped in the two regions.
  • the lining used for doping the impurities The base is not limited, that is, the components of the impurities may be the same or different; the materials of the substrate used for doping the impurities may be the same or different.
  • Figure 3 shows a schematic top structural view of a semiconductor device provided by an embodiment of the present application.
  • Figure 4 shows a schematic cross-sectional structural view along the tangent line A1A2 in Figure 3.
  • Figure 5 shows a schematic cross-sectional structural view along the tangent line A3A4 in Figure 3.
  • the schematic cross-sectional structural diagram in the direction Figure 6a shows a schematic cross-sectional structural diagram along the tangent direction V1V2 in Figure 3
  • Figure 6b shows another schematic cross-sectional structural diagram along the tangent direction V1V2 in Figure 3
  • Figure 7 shows a schematic cross-sectional structural view along the tangent direction V3V4 in Figure 3
  • Figure 8 shows a partial three-dimensional structural schematic view in Figure 3
  • Figure 9 shows the semiconductor device shown in Figure 8 without layers.
  • a schematic three-dimensional structural diagram of the trench structure in the semiconductor device shown in FIG. 8 is shown in FIG. 10 .
  • the semiconductor device provided in the embodiment of the present application may specifically include: an N-type semiconductor substrate 1, an epitaxial layer 100, a trench structure 7, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14.
  • the epitaxial layer 100 may include a first P-type semiconductor region 8.
  • the epitaxial layer 100 may also include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, and a source region 6 sequentially arranged on the semiconductor substrate 1, and the first P-type semiconductor region 8 is arranged in the first N-type semiconductor region 2.
  • the semiconductor substrate 1 may be a SiC single crystal substrate doped with pentavalent elements.
  • the epitaxial layer 100 may be made of SiC material grown by epitaxial growth and doped with corresponding impurities.
  • the first N-type semiconductor region 2 may be a partial region of the epitaxial layer 100 formed by epitaxial growth, and the second N-type semiconductor region 3 and the source region 6 may be formed by doping the epitaxial layer 100 using an ion implantation process. of.
  • the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).
  • the doping concentration of the semiconductor substrate 1 is generally greater than the doping concentration of the second N-type semiconductor region 3
  • the doping concentration of the second N-type semiconductor region 3 is generally greater than the doping concentration of the first N-type semiconductor region 2
  • the doping concentration of the source region 6 is generally greater than the doping concentration of the second N-type semiconductor region 3 .
  • the second P-type semiconductor region 4 and the first P-type semiconductor region 8 may be formed by doping the epitaxial layer 100 using an ion implantation process.
  • the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • the trench structure 7 is disposed in the epitaxial layer 100 , and in the third direction z perpendicular to the plane of the semiconductor substrate 1 , the trench structure 7 extends into the first N-type semiconductor region 2 and in contact with the first P-type semiconductor region 8 .
  • the projection of the first P-type semiconductor region 8 in the third direction z may cover the trench structure 7 .
  • the trench structure 7 may specifically include a plurality of first trenches 71 and a second trench 72 , each of the plurality of first trenches 71 extending along a first direction parallel to the plane of the semiconductor substrate 1 .
  • the second trenches 72 extend along the second direction y, and are spaced apart along the second direction y parallel to the plane of the semiconductor substrate 1 .
  • Each first trench 71 is arranged to intersect and communicate with each other.
  • the main function of the second trench 72 is to communicate with each first trench 71.
  • a closely arranged trench structure 7 is formed.
  • the first direction x, the second direction y, and the third direction z are arranged to cross each other.
  • the first direction x, the second direction y, and the third direction z are arranged to be perpendicular to each other.
  • the gate electrode 11 is filled and disposed in the trench structure 7 through the gate dielectric layer 10 .
  • Each portion of the gate electrode 11 disposed in the plurality of first trenches 71 extends along the first direction x.
  • the portion of the electrode 11 disposed in the second trench 72 extends along the second direction y, and is used to communicate with the portions of the gate electrode 11 extending along the first direction x.
  • the existence of the trench structure 7 causes the gate electrode 11 to be embedded inside the epitaxial layer 100 of the SiC material.
  • the gate electrode 11 forms the trench gate structure of the SiC MOSFET device through the gate dielectric layer 10 and the second P-type semiconductor region 4, so that the present application
  • the semiconductor device provided in the embodiment is a SiC MOSFET with a trench gate structure.
  • the material of the gate electrode 11 can be polysilicon material, or other materials with good conductive properties such as metal (such as W, Al, Ti, Cu, Mo or Pt).
  • the interlayer dielectric layer 12 is disposed on the gate electrode 11 and covers the gate electrode 11 .
  • the source electrode 13 is disposed on the interlayer dielectric layer 12 , that is, the source electrode 13 covers the entire interlayer dielectric layer 12 .
  • the drain electrode 14 is disposed on the side of the semiconductor substrate 1 away from the epitaxial layer 100 , that is, the drain electrode 14 covers the side of the semiconductor substrate 1 where the epitaxial layer 100 is not disposed.
  • a contact hole 121 extending along the second direction y may be provided in the interlayer dielectric layer 12 .
  • the projection of the contact hole 121 in the third direction z and the gate electrode 11 may not overlap each other, that is, the contact hole 121 and the gate electrode 11 may not overlap each other.
  • the contact hole 121 exposes part of the source region 6 , for example, the contact hole 121 can expose the portion of the source region 6 located on both sides of the gate 11 in the first direction x, so that the source 13 can communicate with the source 13 through the contact hole 121 .
  • the source region 6 is in contact, achieving the effect of connecting the source electrode 13 with the source region 6 , and the source electrode 13 can be electrically connected to the first P-type semiconductor region 8 .
  • the gate 11 controls the channel to be turned on, signals can be transmitted between the source 13 and the drain 14 , wherein each first trench 71 in the trench structure 7 is arranged oppositely in the second direction y.
  • the part of the side wall is the channel.
  • the material forming the interlayer dielectric layer 12 may be a dielectric material, including but not limited to silicon dioxide ( SiO2 ), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), and the like.
  • the material used to form the source electrode 13 and the drain electrode 14 may be a metal material.
  • the metal material may include W, Al, Ti, Cu, Mo or Pt, etc.
  • the semiconductor device provided by the embodiment of the present application since the extension direction of the contact hole 121 provided in the interlayer dielectric layer 12 is the second direction y, and the extension direction of each first trench 71 of the trench structure 7 is the first direction x, Then the extension direction of the contact hole 121 is perpendicular to the extension direction of each first trench 71, that is, the contact hole 121 is placed in a direction perpendicular to the first trench 71.
  • the semiconductor device provided by the embodiment of the present application reduces the restriction of the contact hole 121 on the trench spacing C of the adjacent first trench 71 in the second direction y, and can make the trench structure more precise.
  • the trench structure array density of the semiconductor device provided by the embodiment of the present application can be much higher than the trench structure array density of the device structure in the prior art, thereby increasing the channel density of the SiC MOSFET and significantly reducing the conduction of the device. Pass the total resistance, improve device performance and reduce device loss.
  • the source 13 when the SiC MOSFET device is operating, the source 13 will be loaded with voltage. Since the first P-type semiconductor region 8 is connected to the source 13, the voltage loaded on the source 13 will be input into the first P-type semiconductor region 8. , so that the first P-type semiconductor region 8 also has a corresponding voltage, so that the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7 can be effectively shielded, thereby improving the robustness of the device operation.
  • the SiC MOSFET provided in the embodiment of the present application when the SiC MOSFET provided in the embodiment of the present application is applied to an electronic device, its source 13 can be grounded, and its drain 14 can be connected to other components, then the voltage of the source 13 of the SiC MOSFET is the ground voltage (0V). Since the first P-type semiconductor region 8 is conductive with the source 13, the voltage of the first P-type semiconductor region 8 is also the ground voltage, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of the device operation.
  • the SiC MOSFET provided by the embodiment of the present application when the SiC MOSFET provided by the embodiment of the present application is applied to electronic equipment, its source 13 can also be connected to other components, and its drain 14 can also be connected to other components. Then the voltage of the source 13 of the SiC MOSFET is other The voltage of the signal input to the component. Since the first P-type semiconductor region 8 is connected to the source electrode 13, the voltage of the first P-type semiconductor region 8 is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7. This improves the robustness of device operation.
  • the range of the thickness of the first P-type semiconductor region 8 in the third direction z may be less than 1 ⁇ m.
  • the range of the thickness of the first P-type semiconductor region 8 in the third direction z may be 0.3um ⁇ 0.8um.
  • a trench structure 7 may be provided between two adjacent contact holes 121, so that the signal The circulation is more even.
  • FIGS. 3 to 5 two trench structures 7 and three contact holes 121 are illustrated.
  • the structural parameters in each trench structure 7 can be the same, which can ensure that the trench structures 7 are evenly distributed.
  • the number of the first trenches 71 may be the same
  • the trench spacing between the first trenches 71 may be the same
  • the trench lengths of the first trenches 71 may be the same
  • the lengths of the second trenches 72 may be the same.
  • the two groove structures 7 are respectively provided with five first grooves 71 .
  • the number of first trenches 71 provided in the trench structure 7 shown in FIG. 3 is only for explanation and does not limit the number of first trenches 71 in the actually manufactured semiconductor device. In practical applications, the number of first trenches 71 in the trench structure 7 can be determined according to the needs of the actual application, and is not limited in this application.
  • the number of first trenches 71 in some trench structures 7 can also be made the same, while the number of first trenches 71 in the remaining trench structures 7 can be different. Alternatively, the number of first trenches 71 in different trench structures 7 may also be different. In practical applications, the number of first trenches 71 in the trench structure 7 can be determined according to the needs of the actual application, and is not limited in this application.
  • the two first trenches 71 at the edge in the trench structure 7 can be defined as the first edge trench and the second edge trench respectively, and the contact hole 121
  • the side of the first edge groove facing away from the second edge groove extends along the second direction to the side of the second edge groove facing away from the first edge groove.
  • the two first grooves 71 at the upper and lower edges of the two groove structures 7 are respectively defined as the first edge groove and the second edge groove, then the contact The hole 121 extends along the second direction y from a side of the first edge groove facing away from the second edge groove to a side of the second edge groove facing away from the first edge groove. That is to say, the contact hole 121 is a continuous opening, and the first trenches 71 in different trench structures 7 do not communicate with each other.
  • the epitaxial layer 100 may further include: a third P-type semiconductor region 9 and a fourth P-type semiconductor region 5 .
  • the third P-type semiconductor region 9 is disposed on at least one sidewall of the trench structure 7 , and the fourth P-type semiconductor region 5 and the source region 6 are disposed in the same layer.
  • the third P-type semiconductor region 9 and the first P-type semiconductor region 8 are in contact with each other, and the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 are arranged in one-to-one correspondence and are in contact with each other.
  • the voltage can be input to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 in sequence, so that the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7 can be effectively shielded, thereby improving the operation efficiency of the device. robustness.
  • the second P-type semiconductor region 4, the first P-type semiconductor region 8, the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 can be doped by doping the epitaxial layer 100 using an ion implantation process. Forming.
  • the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • the doping concentration of the first P-type semiconductor region 8 , the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 is greater than the doping concentration of the second P-type semiconductor region 4 .
  • the doping concentrations of the first P-type semiconductor region 8 , the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 may be the same or similar.
  • at least two of the first P-type semiconductor region 8 , the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 may have different doping concentrations. It should be noted that the doping concentrations of the first P-type semiconductor region 8 , the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 can be determined according to the requirements of the actual application environment and are not limited here.
  • each first groove 71 in the plurality of first grooves 71 may have an oppositely arranged first side wall S1 and a
  • the two sidewalls S2 and the third P-type semiconductor region 9 may be disposed on the first sidewall S1 and the second sidewall S2 of at least one of the plurality of first trenches 71 , that is, at least one
  • the first sidewall S1 and the second sidewall S2 of the first trench 71 respectively provide third P-type semiconductor regions 9 .
  • the third P-type semiconductor regions 9 are all in contact with the first P-type semiconductor region 8, so that the third P-type semiconductor regions 9 can be connected to the first P-type semiconductor region 8 for signal transmission, then the third P-type semiconductor region 9 can be connected to the first P-type semiconductor region 8 for signal transmission.
  • the voltages of the P-type semiconductor regions 9 are the same as those of the first P-type semiconductor region 8 .
  • the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 are in one-to-one correspondence and are arranged in contact.
  • the fourth P-type semiconductor region 5 can be in contact with the corresponding source electrode 13 through the contact hole 121 .
  • the third P-type semiconductor region 9 provided on the first sidewall S1 corresponds to a fourth P-type semiconductor region 5, and the fourth P-type semiconductor region 5 is provided in the third P-type semiconductor region 9 away from the first trench.
  • the third P-type semiconductor region 9 provided on the second sidewall S2 corresponds to a fourth P-type semiconductor region 5, and the fourth P-type semiconductor region 5 is provided in the third P-type semiconductor region 9 away from the first trench.
  • the source 13 is connected to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 which are arranged corresponding to each other in sequence, so that the voltage loaded by the source 13 passes through the fourth P-type semiconductor region in sequence. 5 and the third P-type semiconductor region 9 are input to the first P-type semiconductor region 8, so that the first P-type semiconductor region 8 has a voltage, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the device operation. of robustness.
  • multiple third P-type semiconductor regions 9 may be provided, and the first sidewall S1 of each first trench 71 is provided with one of the plurality of third P-type semiconductor regions 9 .
  • semiconductor region 9 , and the second sidewall S2 of each first trench 71 is also provided with a third P-type semiconductor region 9 among a plurality of third P-type semiconductor regions 9 . That is to say, the first sidewall S1 and the second sidewall S2 of each first trench 71 are respectively provided with the third P-type semiconductor region 9 .
  • these third P-type semiconductor regions 9 are all in contact with the first P-type semiconductor region 8, so that the third P-type semiconductor regions 9 can be connected to the first P-type semiconductor region 8 for signal transmission, then the third The P-type semiconductor regions 9 all have the same voltage as the first P-type semiconductor region 8 .
  • a plurality of fourth P-type semiconductor regions 5 may be provided. The plurality of fourth P-type semiconductor regions 5 correspond to the plurality of third P-type semiconductor regions 9 and are arranged in contact with each other.
  • the third P-type semiconductor region 9 provided on the first sidewall S1 corresponds to one of the plurality of fourth P-type semiconductor regions 5
  • the fourth P-type semiconductor region 5 is provided on The third P-type semiconductor region 9 is on one side away from the first sidewall S1 of the first trench 71 .
  • the third P-type semiconductor region 9 provided on the second sidewall S2 corresponds to one of the plurality of fourth P-type semiconductor regions 5
  • the fourth P-type semiconductor region 5 is provided on The third P-type semiconductor region 9 is away from the side of the second sidewall S2 of the first trench 71 .
  • the source 13 is connected to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 which are arranged corresponding to each other in sequence, so that the voltage loaded by the source 13 passes through the fourth P-type semiconductor region in sequence. 5 and the third P-type semiconductor region 9 are input to the first P-type semiconductor region 8, so that the first P-type semiconductor region 8 has a voltage, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the device operation. of robustness.
  • the third P-type semiconductor region 9 is respectively provided at the first sidewall S1 and the second sidewall S2 of the trench structure 7, the third P-type semiconductor region 9 is provided at the trench structure 7.
  • the second P-type semiconductor region 4 at the first sidewall S1 and the second sidewall S2 (that is, the second P-type semiconductor region 4 below the fourth P-type semiconductor region 5) is not controlled by the gate 11. Has channel performance. Therefore, in the second direction y, the portion of the sidewall of the trench structure 7 corresponding to the gate 11 is the channel.
  • multiple source regions 6 may also be provided, multiple source regions 6 located at the same end of the trench structure 7 and multiple fourth P-type The semiconductor regions 5 are arranged alternately.
  • a plurality of source regions 6 and a plurality of fourth P-type semiconductor regions 5 located at the first sidewalls S1 of the plurality of first trenches 71 in the same trench structure 7 are alternately arranged.
  • a plurality of source regions 6 and a plurality of fourth P-type semiconductor regions 5 located at the second sidewalls S2 of the plurality of first trenches 71 in the same trench structure 7 are alternately arranged.
  • this application does not limit the width of the fourth P-type semiconductor region 5 along the second direction y.
  • the width of the fourth P-type semiconductor region 5 along the second direction y can be made the same as the width of the first trench 71 Or similar.
  • the width of the source region 6 along the second direction y is the same as or similar to the trench pitch C between two adjacent first trenches 71 .
  • the width of the fourth P-type semiconductor region 5 along the second direction y can also be different from the width of the first trench 71, which is not limited here.
  • the trench spacing C may be less than 1 ⁇ m.
  • the trench pitch C ranges from 50nm to 0.5um. It should be noted that when the trench spacing C is less than 100nm, the semiconductor device provided by this application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly increase the carrier channel mobility, further Reduce the total on-resistance of the device.
  • Fin FET Fin Field-Effect Transistor
  • the first groove 71 has a groove length D in the first direction.
  • This application does not limit the trench length D.
  • the trench length D can be greater than 5um.
  • the first trench 71 has a trench width E in the second direction y.
  • This application does not limit the trench width E.
  • the trench width E may be less than 1 ⁇ m.
  • the contact hole 121 has a contact width F, so that the trench pitch C is no larger than the contact width F.
  • the trench pitch C can also be made larger than the contact width F.
  • the groove pitch C and the contact width F can be determined according to the environmental requirements of the actual application, and are not limited here.
  • the first P-type semiconductor region 8 is formed at the bottom of the trench structure 7 using a vertical ion implantation process after the channel structure 7 is formed. Therefore, the first P-type semiconductor region 8 is formed at the bottom of the trench structure 7 .
  • the projection in three directions z can cover the trench structure 7 .
  • the first P-type semiconductor region 8 will diffuse toward the bottom periphery of the trench structure 7 , that is, an orthographic projection of the first P-type semiconductor region 8 on the semiconductor substrate 1 will be presented. The edge is located at the periphery of the orthographic edge of the trench structure 7 on the semiconductor substrate 1 .
  • the first P-type semiconductor region 8 when the trench spacing C in the trench structure 7 is greater than the ion implantation diffusion size, for example, when the trench spacing C is greater than 0.4um, the first P-type semiconductor region 8 is in each There will be a certain distance between the bottom portions of a trench 71. At this time, the orthographic projection shape of the first P-type semiconductor region 8 on the semiconductor substrate 1 and the orthographic projection shape of the trench structure 7 on the semiconductor substrate 1 resemblance.
  • the spacing area between them can also cover the gap between two adjacent first trenches 71 . That is to say, the orthographic projection of the first P-type semiconductor region 8 on the semiconductor substrate 1 also covers the orthographic projection of the gap between the two adjacent first trenches 71 in the second direction y on the semiconductor substrate 1 .
  • the first P-type semiconductor region 8 can be considered as a planar region extending along the second direction y, and the shape of the first P-type semiconductor region 8 can be considered as a rectangle.
  • the projection of the first P-type semiconductor region 8 in the third direction z may also cover the third P-type semiconductor region 9 . That is to say, the orthographic projection of the first P-type semiconductor region 8 on the semiconductor substrate 1 not only covers the orthographic projection of the trench structure 7 on the semiconductor substrate 1 , but also covers all the orthographic projections of the third P-type semiconductor region 9 on the semiconductor substrate 1 . Orthographic projection on base 1.
  • one trench structure 7 is provided corresponding to a first P-type semiconductor region 8 . That is to say, if a trench structure 7 is provided, a first P-type semiconductor region 8 is correspondingly provided. If two trench structures 7 are provided, two first P-type semiconductor regions 8 are provided accordingly. Furthermore, there is a gap between the two first P-type semiconductor regions 8 . If multiple trench structures 7 are provided, multiple first P-type semiconductor regions 8 are provided accordingly. Moreover, there is a gap between every two adjacent first P-type semiconductor regions 8 .
  • the second P-type semiconductor region 4 at the two sidewalls of the first trench 71 in the second direction y of the trench structure 7 forms the channel region of the SiC MOSFET. Therefore, , by increasing the trench width D or reducing the trench spacing C, the conductive channel density of SiC MOSFET devices can be increased and the total on-resistance of SiC MOSFET devices can be reduced.
  • FIG11 shows some schematic diagrams of the semiconductor device provided in the embodiment of the present application when generating an on-current
  • FIG12 shows a schematic diagram of the cross-sectional structure along the C1C2 tangent direction in FIG11.
  • the black straight line with an arrow represents the flow direction of the on-current when the SiC MOSFET is turned on.
  • the MOSFET of the trench structure 7 provided in the present application can be controlled to be turned on.
  • Figure 13 shows some flow charts of a method for manufacturing a semiconductor device provided by an embodiment of the present application
  • Figures 14a to 14i respectively show a schematic structural diagram of a process of preparing a semiconductor device provided by an embodiment of the present application.
  • the preparation method may include the following steps:
  • step S10 includes:
  • an epitaxial process is used to epitaxially grow SiC material doped with N-type impurities to form an epitaxial layer 100.
  • This application does not limit the specific value of the thickness of the epitaxial layer 100 .
  • the specific value of the thickness can be determined according to the needs of the actual application environment.
  • S20 Use an ion implantation process to perform ion implantation in part of the epitaxial layer to form the second N-type semiconductor region, the second P-type semiconductor region and the source region.
  • the first N-type semiconductor region is formed in the region where ions are not implanted in the epitaxial layer. Semiconductor area.
  • an ion implantation process is used to perform N-type impurity doping on the surface of the epitaxial layer 100 to form the second N-type semiconductor region 3.
  • an ion implantation process is used to dope P-type impurities on the surface of the epitaxial layer to form the second P-type semiconductor region 4 .
  • an ion implantation process is used to perform N-type impurity doping on the surface of the epitaxial layer 100 to form the source region 6 and the epitaxial layer 100 at the first sidewall S1 and the second sidewall S2 of the first trench 71
  • the surface is doped with P-type impurities to form a fourth P-type semiconductor region 5 arranged in the same layer as the source region 6 .
  • the second N-type semiconductor region 3, the second P-type semiconductor region 4, the source region 6 and the fourth P-type semiconductor region 5 are formed in part of the epitaxial layer 100.
  • the first N-type semiconductor region 2 is formed in the region of the epitaxial layer 100 that is not ion implanted using this ion implantation process.
  • a trench mask is formed on the epitaxial layer (the trench mask can be a mask formed using photoresist or a hard mask), and there is no need to form a trench through the trench mask.
  • the area in the epitaxial layer of the trench structure 7 is covered, while the area in the epitaxial layer where the trench structure 7 needs to be formed is exposed.
  • a suitable etching process is selected from etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the areas in the epitaxial layer that are not covered by the trench mask are Etch until etching into the first N-type semiconductor region 2 and stop etching when the first P-type semiconductor region 8 is exposed to form a plurality of first trenches and second trenches in the epitaxial layer.
  • a vertical ion implantation process can be used to dope P-type impurities into the bottom of the trench structure 7 to form a first P-type semiconductor region 8 consistent with the bottom pattern of the trench structure 7 or in a planar region.
  • This application does not limit the thickness of the first P-type semiconductor region 8 (that is, the thickness in the third direction).
  • the specific value of the thickness of the first P-type semiconductor region 8 can be determined according to the requirements of the actual application environment.
  • a third P-type semiconductor region in contact with the first P-type semiconductor region is formed on the first side wall and the second side wall of each first trench along the first direction.
  • an oblique ion implantation process is used to perform P-type impurity doping on the surface of the first sidewall S1 and the second sidewall S2 of each first trench 71, respectively forming the first P-type impurity.
  • the semiconductor region 8 contacts the third P-type semiconductor region 9 .
  • an oxidation process is used to oxidize the surface of the trench structure 7 so that the gate dielectric layer 10 is formed on the surface of the trench structure 7 .
  • a deposition process is used to deposit polysilicon material on the entire epitaxial layer forming the trench structure, and the polysilicon material fills the trench structure.
  • the entire epitaxial layer covers the polysilicon material. film layer.
  • a suitable etching process is selected from the etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the polysilicon material area is etched until the source region 6 and The etching of the fourth P-type semiconductor region 5 is stopped to form the gate electrode 11 .
  • a deposition process is adopted to deposit an interlayer dielectric layer 12 on the entire epitaxial layer, and the interlayer dielectric layer 12 covers the entire epitaxial layer.
  • a contact hole mask is formed on the epitaxial layer (the contact hole mask can be a mask formed using photoresist or a hard mask), and no contact will need to be formed through the contact hole mask.
  • the area of the hole 121 is covered, while the area where the contact hole 121 needs to be formed is exposed.
  • a suitable etching process is selected from the etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the interlayer dielectric layer 12 is not covered by the contact hole 121 mask.
  • the region is etched to expose the portion of the source region 6 located on both sides of the gate electrode 11 in the first direction x and the portion of the fourth P-type semiconductor region 5 located on both sides of the gate electrode 11 .
  • the material forming the source electrode and the drain electrode may be a metal material.
  • the metallic material may include W, Al, Ti, Cu, Mo, or Pt.
  • a deposition process is used to deposit a metal material on the interlayer dielectric layer 12 to form the source electrode 13.
  • the contact hole is filled with metal material, so that the source electrode 13 contacts the source region 6 through the metal material filled in the contact hole 121 .
  • a deposition process may be used to deposit a metal material on the side of the semiconductor substrate 1 away from the epitaxial layer to form the drain electrode 14.
  • a deposition process may be used to deposit a metal material on the side of the semiconductor substrate 1 away from the epitaxial layer to form the drain electrode 14 .
  • Figure 15 shows a schematic three-dimensional structural diagram of a semiconductor device according to another embodiment of the present application.
  • Figure 16 shows a schematic three-dimensional structural diagram of the semiconductor device shown in Figure 15 when no interlayer dielectric layer and source are provided.
  • Figure 17 shows a schematic three-dimensional structural diagram of the trench structure in the semiconductor device shown in FIG. 15 .
  • the semiconductor device provided by the embodiment of the present application may specifically include: an N-type semiconductor substrate 1 , an epitaxial layer, a trench structure 7 , and a gate 11 , interlayer dielectric layer 12, source electrode 13 and drain electrode 14.
  • the epitaxial layer may include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, a source region 6, a first P-type semiconductor region 8, and a third P-type semiconductor region 9. and a fourth P-type semiconductor region 5 .
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • a plurality of third P-type semiconductor regions 9 are provided, and one of the plurality of third P-type semiconductor regions 9 is provided on the first sidewall S1 of each first trench 71 .
  • a third P-type semiconductor region 9 is provided, and the third P-type semiconductor region 9 is not provided on the second sidewall S2 of each first trench 71 . That is to say, the third P-type semiconductor region 9 is provided only at the first sidewall S1 of each first trench 71 .
  • these third P-type semiconductor regions 9 are all in contact with the first P-type semiconductor region 8, so that the third P-type semiconductor regions 9 are connected to the first P-type semiconductor region 8 for signal transmission, then the third P-type semiconductor region 9 is in contact with the first P-type semiconductor region 8.
  • the semiconductor regions 9 all have the same voltage as the first P-type semiconductor region 8 .
  • the positions of the first side wall S1 and the second side wall S2 of the first trench 71 can also be interchanged, that is, multiple third Ps can be provided on the second side wall S2 of the first trench 71
  • a third P-type semiconductor region 9 is provided in the P-type semiconductor region 9 , and the third P-type semiconductor region 9 is not provided on the first sidewall S1 of each first trench 71 .
  • a plurality of fourth P-type semiconductor regions 5 are also provided.
  • the plurality of fourth P-type semiconductor regions 5 correspond to the above-mentioned plurality of third P-type semiconductor regions 9 and are arranged in contact.
  • the third P-type semiconductor region 9 provided on the first sidewall S1 corresponds to one of the plurality of fourth P-type semiconductor regions 5
  • the fourth P-type semiconductor region 5 is provided on The third P-type semiconductor region 9 is on one side away from the first sidewall S1 of the first trench 71 .
  • the source 13 is connected to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 which are arranged corresponding to each other in sequence, so that the voltage loaded by the source 13 passes through the fourth P-type semiconductor region in sequence. 5 and the third P-type semiconductor region 9 are input to the first P-type semiconductor region 8, so that the first P-type semiconductor region 8 has a voltage, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the device operation. of robustness.
  • the epitaxial layer 100 may also include: a fifth P-type semiconductor region 15, the fifth P-type semiconductor region 15 and the source region 6 are arranged in the same layer, the fifth P-type semiconductor region 15 is arranged on the side of the second side wall S2 of the first trench 71 away from the first side wall S1, and the fifth P-type semiconductor region 15 is in contact with the source 13 through the contact hole 121.
  • a plurality of fifth P-type semiconductor regions 15 may be provided, and the plurality of fifth P-type semiconductor regions 15 may be provided in one-to-one correspondence with the second sidewall S2 of each first trench 71 . Furthermore, the plurality of source regions 6 and the plurality of fifth P-type semiconductor regions 15 located on the second sidewall S2 of the first trench 71 are alternately arranged.
  • the fifth P-type semiconductor region 15 may be formed by doping the epitaxial layer using an ion implantation process. Moreover, the fifth P-type semiconductor region 15 is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga). For example, the doping concentration of the fifth P-type semiconductor region 15 may be the same as or similar to the doping concentration of the fourth P-type semiconductor region 5 .
  • the third P-type semiconductor region 9 is provided at the first sidewall S1 of the first trench 71, and no channel is formed.
  • steps S10 to S40 and S60 to S90 may refer to the description of the above preparation method.
  • step S50 is: using an oblique ion implantation process to form third P-type semiconductor regions in contact with the first P-type semiconductor regions on the first sidewalls of each first trench along the first direction. Semiconductor area.
  • an oblique ion implantation process is used to perform P-type impurity doping on the surface of the first sidewall S1 of each first trench 71 to form a first P-type semiconductor region in contact with the first P-type semiconductor region 8 .
  • Figure 18 shows a schematic three-dimensional structure diagram of a semiconductor device provided by yet another embodiment of the present application.
  • Figure 19 shows a schematic three-dimensional structure diagram of the semiconductor device shown in Figure 18 when no interlayer dielectric layer and source electrode are provided.
  • Figure 20 shows a schematic three-dimensional structural diagram of the trench structure in the semiconductor device shown in FIG. 18 .
  • the semiconductor device may specifically include: N-type semiconductor substrate 1, epitaxial layer, trench structure 7, gate 11, interlayer dielectric layer 12, Source 13 and drain 14 .
  • the epitaxial layer may include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, a source region 6, a first P-type semiconductor region 8, and a third P-type semiconductor region 9. and a fourth P-type semiconductor region 5 .
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • a plurality of third P-type semiconductor regions 9 are provided, and one of the plurality of third P-type semiconductor regions 9 is provided on the first sidewall S1 of each first trench 71
  • the third P-type semiconductor region 9 is provided, and the second sidewall S2 of each first trench 71 is not provided with the third P-type semiconductor region 9 . That is to say, the third P-type semiconductor region 9 is provided only at the first sidewall S1 of each first trench 71 .
  • these third P-type semiconductor regions 9 are all in contact with the first P-type semiconductor region 8, so that the third P-type semiconductor regions 9 are connected to the first P-type semiconductor region 8 for signal transmission, then the third P-type semiconductor region 9 is in contact with the first P-type semiconductor region 8.
  • the semiconductor regions 9 all have the same voltage as the first P-type semiconductor region 8 .
  • the positions of the first side wall S1 and the second side wall S2 of the first trench 71 can also be interchanged, that is, multiple third Ps can be provided on the second side wall S2 of the first trench 71
  • a third P-type semiconductor region 9 is provided in the P-type semiconductor region 9 , and the third P-type semiconductor region 9 is not provided on the first sidewall S1 of each first trench 71 .
  • a plurality of fourth P-type semiconductor regions 5 are also provided.
  • the plurality of fourth P-type semiconductor regions 5 correspond to the plurality of third P-type semiconductor regions 9 and are arranged in contact.
  • the third P-type semiconductor region 9 provided on the first sidewall S1 corresponds to one of the plurality of fourth P-type semiconductor regions 5
  • the fourth P-type semiconductor region 5 is provided on The third P-type semiconductor region 9 is on one side away from the first sidewall S1 of the first trench 71 .
  • the source 13 is connected to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 which are arranged corresponding to each other in sequence, so that the voltage loaded by the source 13 passes through the fourth P-type semiconductor region in sequence. 5 and the third P-type semiconductor region 9 are input to the first P-type semiconductor region 8, so that the first P-type semiconductor region 8 has a voltage, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the device operation. of robustness.
  • the fourth P-type semiconductor region 5 is provided only at the first sidewall S1 of the first trench 71 , and is provided at the second sidewall S2 of the first trench 71 are all source area 6.
  • steps S10, S30-S40, S60-S90 may refer to the description of the above preparation method.
  • step S20 is: using an ion implantation process to perform ion implantation in part of the epitaxial layer to form the second N-type semiconductor region, the second P-type semiconductor region and the source region. No ions are implanted in the epitaxial layer. The implanted region forms a first N-type semiconductor region.
  • an ion implantation process is used to perform N-type impurity doping on the surface of the epitaxial layer to form the second N-type semiconductor region 3 .
  • an ion implantation process is used to dope P-type impurities on the surface of the epitaxial layer to form the second P-type semiconductor region 4 .
  • an ion implantation process is used to perform N-type impurity doping on the surface of the epitaxial layer to form the source region 6, and P-type impurity doping is performed on the surface of the epitaxial layer at the first sidewall S1 of the first trench 71.
  • a fourth P-type semiconductor region 5 is formed in the same layer as the source region 6 .
  • the second N-type semiconductor region 3, the second P-type semiconductor region 4, the source region 6 and the fourth P-type semiconductor region 5 are formed in part of the epitaxial layer.
  • the first N-type semiconductor region 2 is formed in the region of the epitaxial layer that is not ion implanted using the ion implantation process.
  • step S50 is: using an oblique ion implantation process to form third P-type semiconductor regions in contact with the first P-type semiconductor regions on the first sidewalls of each first trench along the first direction. Semiconductor area.
  • an oblique ion implantation process is used to perform P-type impurity doping on the surface of the first sidewall S1 of each first trench 71 to form a first P-type impurity in contact with the first P-type semiconductor region 8 respectively.
  • Figure 21 shows a schematic diagram of the top view of the semiconductor device provided by another embodiment of the present application
  • Figure 22 shows a schematic diagram of the cross-sectional structure along the B1B2 tangent direction in Figure 21
  • Figure 23 shows a schematic diagram of the cross-sectional structure along the B3B4 tangent direction in Figure
  • Figure 24a shows a schematic diagram of a cross-sectional structure along the X1X2 tangent direction in Figure 21
  • Figure 24b shows another schematic diagram of the cross-sectional structure along the X1X2 tangent direction in Figure
  • Figure 25 shows a schematic diagram of the cross-sectional structure along the X3X4 tangent direction in Figure
  • Figure 26 shows a schematic diagram of the local three-dimensional structure in Figure
  • Figure 27 shows a schematic diagram of the three-dimensional structure when the interlayer dielectric layer and the source are not set in the semiconductor device shown in Figure 26
  • Figure 28 shows a schematic diagram of the local three-dimensional structure in the semiconductor device shown in Figure 27.
  • the semiconductor device provided by the embodiment of the present application may specifically include: an N-type semiconductor substrate 1 , an epitaxial layer, a trench structure 7 , and a gate 11 , interlayer dielectric layer 12, source electrode 13 and drain electrode 14.
  • the epitaxial layer may include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, a source region 6, a first P-type semiconductor region 8, and a third P-type semiconductor region 9. and a fourth P-type semiconductor region 5 .
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the second groove 72 may protrude from the first groove 71 located at the edge of the plurality of first grooves 71.
  • the second groove 72 may have a The third P-type semiconductor region 9 may be disposed on the third sidewall S3 and/or the fourth sidewall S4 of the second trench 72 relative to the third sidewall S3 and the fourth sidewall S4.
  • both ends of the second groove 72 protrude from the first groove 71 located at the edge of the plurality of first grooves 71 .
  • the third P-type semiconductor region 9 may be disposed on the third sidewall S3 and the fourth sidewall S4 of the second trench 72 , that is, the third sidewall S3 and the fourth sidewall S4 of the second trench 72 .
  • the sidewalls S4 are respectively provided with third P-type semiconductor regions 9 .
  • the third P-type semiconductor regions 9 are all in contact with the first P-type semiconductor region 8, so that the third P-type semiconductor regions 9 can be connected to the first P-type semiconductor region 8 for signal transmission, then the third P-type semiconductor region 9 can be connected to the first P-type semiconductor region 8 for signal transmission.
  • the voltages of the P-type semiconductor regions 9 are the same as those of the first P-type semiconductor region 8 .
  • the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 correspond one to one and are arranged in contact.
  • the third P-type semiconductor region 9 provided on the third sidewall S3 corresponds to a fourth P-type semiconductor region 5, and the fourth P-type semiconductor region 5 is provided in the third P-type semiconductor region 9 away from the second trench.
  • the third P-type semiconductor region 9 provided on the fourth sidewall S4 corresponds to a fourth P-type semiconductor region 5, and the fourth P-type semiconductor region 5 is provided in the third P-type semiconductor region 9 away from the second trench.
  • One side of the fourth side wall S4 of the groove 72 One side of the fourth side wall S4 of the groove 72 .
  • the voltage can be input to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 in sequence, so that the first P-type semiconductor region 8 has a voltage, thereby effectively shielding the bottom of the trench structure 7
  • the electric field of the gate dielectric layer 10 thereby improves the robustness of the device operation.
  • the epitaxial layer 100 may further include: a fifth P-type semiconductor region 15 , the fifth P-type semiconductor region 15 and the source region 6 are provided in the same layer, and the fifth P-type semiconductor region 15 may be provided On the side of the second sidewall S2 of the first trench 71 facing away from the first sidewall S1, the fifth P-type semiconductor region 15 may also be disposed on the side of the first sidewall S1 of the first trench 71 facing away from the second sidewall S2. side, and the fifth P-type semiconductor region 15 is in contact with the source electrode 13 through the contact hole 121 .
  • a plurality of fifth P-type semiconductor regions 15 may be provided, and the plurality of fifth P-type semiconductor regions 15 may be provided in one-to-one correspondence with the first sidewall S1 and the second sidewall S2 of each first trench 71 . Furthermore, the plurality of source regions 6 and the plurality of fifth P-type semiconductor regions 15 located on the first sidewall S1 of the first trench 71 are alternately arranged, and the multiple source regions located on the second sidewall S2 of the first trench 71 are alternately arranged. 6 and a plurality of fifth P-type semiconductor regions 15 are arranged alternately.
  • the fifth P-type semiconductor region 15 may be formed by doping the epitaxial layer using an ion implantation process. Moreover, the fifth P-type semiconductor region 15 is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga). For example, the doping concentration of the fifth P-type semiconductor region 15 may be the same as or similar to the doping concentration of the fourth P-type semiconductor region 5 .
  • the third P-type semiconductor region 9 is provided at the third sidewall S3 and the fourth sidewall S4 of the second trench 72, and no channel is formed.
  • steps S10 to S40 and S60 to S90 may refer to the description of the above preparation method.
  • step S50 is: using an oblique ion implantation process to form a third sidewall in contact with the first P-type semiconductor region on the third sidewall and the fourth sidewall of the second trench along the second direction. Three P-type semiconductor regions.
  • an oblique ion implantation process may be used to perform P-type impurity doping on the surfaces of the third sidewall S3 and the fourth sidewall S4 of the second trench 72 , respectively to form the first P-type semiconductor region 8 .
  • the third P-type semiconductor region 9 may be used to perform P-type impurity doping on the surfaces of the third sidewall S3 and the fourth sidewall S4 of the second trench 72 , respectively to form the first P-type semiconductor region 8 .
  • the third P-type semiconductor region 9 may be used to perform P-type impurity doping on the surfaces of the third sidewall S3 and the fourth sidewall S4 of the second trench 72 , respectively to form the first P-type semiconductor region 8 .
  • FIG. 29 shows a schematic top structural view of a semiconductor device provided by another embodiment of the present application
  • FIG. 30 shows a schematic top structural view of a semiconductor device provided by yet another embodiment of the present application.
  • the semiconductor device may specifically include: N-type semiconductor substrate 1, epitaxial layer, trench structure 7, gate 11, interlayer dielectric layer 12, Source 13 and drain 14 .
  • the epitaxial layer may include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, a source region 6, a first P-type semiconductor region 8, and a third P-type semiconductor region 9. and a fourth P-type semiconductor region 5 .
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the first trenches 71 arranged along the first direction x pass through them. That is, the plurality of first trenches 71 may include first gate trenches and second gate trenches penetrating along the first direction x, where the first gate trenches and the second gate trenches may be considered to be located respectively at Two adjacent trench structures.
  • the first edge trench in the left trench structure 7 (can be considered as the first gate trench) and the first edge trench in the right trench structure 7 (can be considered as the second gate trench) ) are arranged along the first direction x, and the two first edge grooves penetrate each other.
  • the second edge trench (can be considered as the first gate trench) in the left trench structure 7 and the second edge trench (can be considered as the second gate trench) in the right trench structure 7 are along the The first direction x is arranged, and the two second edge grooves penetrate each other. Referring to FIG. 30 , a first groove 71 in the middle of the left groove structure 7 may also penetrate through a first groove 71 in the middle of the right groove structure 7 .
  • the contact hole 121 may include a plurality of sub-contact holes spaced apart from each other, and at least one first through-going trench is provided between two adjacent sub-contact holes in the same contact hole 121 .
  • FIG. 30 illustrates two sub-contact holes.
  • This application does not limit the number of sub-contact holes into which the contact hole 121 is divided. For example, it may be two, three, four or more.
  • the present application does not limit the number of the first through-going trenches 71 provided between two adjacent sub-contact holes in the same contact hole 121. For example, it may be one, two, three, four or more. Multiple. This can improve the design freedom of the contact hole 121 and improve the flow uniformity of the SiC MOSFET device.
  • Figure 31 shows a schematic three-dimensional structural diagram of a semiconductor device provided by yet another embodiment of the present application.
  • the semiconductor device may specifically include: N-type semiconductor substrate 1, epitaxial layer, trench structure 7, gate 11, interlayer dielectric layer 12, source 13 and drain 14.
  • the epitaxial layer may include: a third N-type semiconductor region 16 , a first N-type semiconductor region 2 , a second N-type semiconductor region 3 , a second P-type semiconductor region 4 , a source region 6 , and a first P-type semiconductor region 8 , the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 .
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the third N-type semiconductor region 16 may be disposed between the first N-type semiconductor region 2 and the semiconductor substrate 1 . Since the third N-type semiconductor region 16 is provided, the thickness of the first P-type semiconductor region 8 in the epitaxial layer 100 in the third direction z can be set thicker. For example, the first P-type semiconductor region can be made thicker in the third direction z. 8The thickness in the third direction z is set to be greater than 1um.
  • the third N-type semiconductor region 16 may be SiC doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).
  • N-type impurities such as nitrogen (N), phosphorus (P) or arsenic (As).
  • the doping concentration of the third N-type semiconductor region 16 may be smaller than the doping concentration of the first N-type semiconductor region 2 .
  • steps S10 to S90 may refer to the description of the above preparation method.
  • step S10 is to epitaxially grow an epitaxial layer on an N-type semiconductor substrate, which can be implemented in the following manner.
  • an epitaxial process is used to epitaxially grow SiC material doped with N-type impurities on the N-type SiC semiconductor substrate 1 to form the third N-type semiconductor region 16 .
  • an epitaxial process is used to epitaxially grow the SiC material doped with N-type impurities in the third N-type semiconductor region 16 to form an epitaxial layer 100 reaching the first set thickness DS1.
  • Embodiments of the present application also provide a power conversion circuit, which may be an AC-DC conversion circuit and/or a DC-DC conversion circuit.
  • the power conversion circuit may include a circuit board and one or more semiconductor devices, and the semiconductor device is connected to the circuit board. Since the performance of the above-mentioned semiconductor device is better, the performance of the power conversion circuit including the above-mentioned semiconductor device is also better.
  • the principle of the power conversion circuit to solve the problem is similar to the principle of the aforementioned semiconductor device to solve the problem. Therefore, the technical effect of the power conversion circuit can be referred to the technical effect of the aforementioned semiconductor device, and the repeated parts will not be repeated.
  • An embodiment of the present application also provides a vehicle, which includes the power conversion circuit provided by the embodiment of the present application. Since the performance of the above-mentioned power conversion circuit is better, the circuit performance of the vehicle including the above-mentioned power conversion circuit is also better. Moreover, the principle of solving problems of this vehicle is similar to the principle of solving problems of the aforementioned power conversion circuit. Therefore, the technical effect of this vehicle can be referred to the technical effect of the aforementioned power conversion circuit, and the repeated parts will not be repeated.

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Abstract

本申请公开了一种半导体器件、其制备方法、功率转换电路及车辆，包括：N型的半导体衬底、外延层、沟槽结构、栅极、层间介质层、源极以及漏极。外延层包括第一P型半导体区；沟槽结构底部与第一P型半导体区接触，沟槽结构包括多个第一沟槽和一个第二沟槽，第一沟槽沿第一方向延伸，第二沟槽与多个第一沟槽中的每个第一沟槽交叉设置且相互导通；栅极隔着栅介质层填充于沟槽结构中；层间介质层覆盖于栅极上，且具有沿第二方向延伸的接触孔；源极设置于层间介质层上，源极通过接触孔与源区接触且与第一P型半导体区导通；漏极设置于半导体衬底远离外延层的一侧。这样降低了器件的导通总电阻。

Description

半导体器件、其制备方法、功率转换电路及车辆 技术领域
本申请涉及半导体技术领域，尤其涉及到一种半导体器件、其制备方法、功率转换电路及车辆。
背景技术
碳化硅(silicon carbide，SiC)材料相对硅(silicon，Si)材料具有宽禁带、高临界击穿电场、高热导率及高电子饱和漂移速度等优势，利用SiC材料制作的金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)相比Si材料制作的绝缘栅双极型晶体管(insulated gate bipolar transistor，IGBT)具有高击穿电压、低导通压降等特性。且单极导电特性使得SiC MOSFET相比Si IGBT具有更快的开关速度、更低的导通损耗和更低的开关损耗，因此，SiC MOSFET已经在部分应用场景诸如车载微控制单元(micro controller unit，MCU)、车载电池充电器(on-board battery charger，OBC)等领域取代Si IGBT。
相比于普通平面栅结构的器件，采用沟槽栅结构的SiC MOSFET器件通过将栅极嵌入到SiC体内，使器件的导电沟道由平面方向转向垂直方向，因而明显减小了器件的元胞尺寸、极大提高了器件的导电沟道密度，进而可以显著降低芯片的导通电阻、提升通流能力，沟槽栅结构已经成为未来器件的主流技术方向。
但沟槽栅结构的SiC MOSFET器件中，沟道区电阻和结型场效应晶体管(junction field effect transistor，JFET)区电阻之间存在明显的矛盾关系：参照图1，横坐标代表元胞尺寸，纵坐标代表电阻，由图1可知，通过减小SiC MOSFET器件中的沟槽栅结构的间距，可以缩小SiC MOSFET器件的元胞尺寸，增大导电沟道密度，减小沟道区电阻，但同时JFET区通流宽度也会随之减小，导致JFET区电阻增大，从而使得SiC MOSFET器件整体的导通总电阻反而会增加，降低器件性能、增加芯片损耗。并且，在沟槽栅结构的SiC MOSFET器件中，在沟槽栅结构的底部及拐角处的栅介质层在器件工作时会承受极高的电场强度，是电场击穿的薄弱点，易造成器件长期工作可靠性失效，因而如何有效屏蔽栅介质层免受高电场应力作用成为器件高鲁棒性/可靠性设计的关键。
发明内容
本申请提供一种半导体器件、其制备方法、功率转换电路及车辆，用于降低器件的导通总电阻，提升器件工作的鲁棒性，提升器件性能，降低器件损耗。
第一方面，本申请提供了一种半导体器件，包括：N型的半导体衬底、外延层、沟槽结构、栅极、层间介质层、源极以及漏极。其中，外延层可以包括第一P型半导体区。沟槽结构设置于外延层中，且在垂直于半导体衬底所在平面的第三方向上，沟槽结构与第一P型半导体区接触。第一P型半导体区在第三方向上的投影可以覆盖沟槽结构。沟槽结构具体可以包括多个第一沟槽和一个第二沟槽，多个第一沟槽中的每个第一沟槽沿平行于半导体衬底所在平面的第一方向延伸，且沿平行于半导体衬底所在平面的第二方向间隔排列，第二沟槽沿第二方向延伸，且第二沟槽与多个第一沟槽中的每个第一沟槽交叉设置且相互 导通，第二沟槽的主要作用为连通各第一沟槽，在外延层中通过设置第一沟槽和第二沟槽可以形成紧密排列的沟槽结构。其中，第一方向、第二方向以及第三方向相互交叉设置，例如，第一方向、第二方向以及第三方向相互垂直设置。栅极隔着栅介质层填充设置于沟槽结构内，栅极中设置于多个第一沟槽的各部分沿第一方向延伸，栅极中设置于第二沟槽的部分沿第二方向延伸，并用于连通栅极中沿第一方向延伸的各部分。示例性地，外延层可以包括：依次设置于半导体衬底上的第一N型半导体区、第二N型半导体区、第二P型半导体区以及源区；第一P型半导体区可以设置于第一N型半导体区内，在第三方向上，沟槽结构可以延伸至第一N型半导体区中。沟槽结构的存在使栅极嵌入在材料的外延层内部，栅极通过栅介质层与第二P型半导体区一起形成SiC MOSFET器件的沟槽栅结构，使本申请实施例提供的半导体器件为沟槽栅结构的SiC MOSFET。层间介质层设置在栅极上且覆盖栅极。源极设置于层间介质层上，即源极覆盖于整个层间介质层上。漏极设置于半导体衬底远离外延层的一侧，即漏极覆盖于半导体衬底未设置有外延层的一侧上。在实际应用中，源极与漏极之间需要传输信号，则可在层间介质层中设置沿第二方向延伸的接触孔。为了避免源极与栅极接触，可使接触孔在第三方向上的投影与栅极互不交叠，则接触孔与栅极互不交叠。并且，接触孔可以暴露出外延层的部分区域，例如接触孔可以暴露出源区的部分区域，从而使源极通过接触孔与源区接触，且源极可以与第一P型半导体区导通。在栅极控制沟道导通时，源极与漏极之间即可传输信号，其中，沟槽结构中的各第一沟槽在第二方向上相对设置的两个侧壁的部分即为沟道。
本申请实施例提供的半导体器件，由于层间介质层中设置的接触孔的延伸方向为第二方向，沟槽结构的各第一沟槽的延伸方向为第一方向，则接触孔的延伸方向与各第一沟槽的延伸方向相互垂直，即将接触孔放置在垂直于第一沟道的方向上，进而相比现有技术中沟槽结构与接触孔相互平行的设置方式，本申请实施例提供的半导体器件，降低了接触孔对相邻第一沟槽在第二方向上的沟槽间距的限制，能够使沟槽结构制备的更加紧密，即栅极也会更加紧密。因此，本申请实施例提供的半导体器件的沟槽结构阵列密度，可远高于现有技术中器件结构的沟槽结构阵列密度，因而提高了SiC MOSFET的沟道密度，明显降低了器件的导通总电阻，提升器件性能，降低器件损耗。
并且，在SiC MOSFET器件工作时，源极会加载电压，由于第一P型半导体区与源极导通，则源极上加载的电压会输入到第一P型半导体区中，使第一P型半导体区也具有相应的电压，从而能够有效屏蔽沟槽结构的底部的栅介质层电场，进而提升器件工作的鲁棒性。
示例性地，本申请实施例提供的SiC MOSFET在应用到电子设备中时，其源极可接地，其漏极可连接其他元件，则SiC MOSFET的源极的电压为接地电压(0V)。由于第一P型半导体区与源极导通，则第一P型半导体区的电压也为接地电压，从而能够有效屏蔽沟槽结构底部的栅介质层电场，进而提升器件工作的鲁棒性。
示例性地，本申请实施例提供的SiC MOSFET在应用到电子设备中时，其源极也可连接其他元件，其漏极也连接其他元件，则SiC MOSFET的源极的电压为其他元件输入的信号的电压。由于第一P型半导体区与源极导通，则第一P型半导体区的电压也为该输入的信号的电压，从而能够有效屏蔽沟槽结构底部的栅介质层电场，进而提升器件工作的鲁棒性。
本申请对第一P型半导体区在第三方向上的厚度不作限定。在本申请一些实施例中， 第一P型半导体区在第三方向上的厚度的范围可以小于1um，例如，第一P型半导体区在第三方向上的厚度的范围可以为0.3um～0.8um。
在本申请中，半导体衬底可以为掺杂有五价元素的SiC单晶衬底。外延层可以采用外延生长生成的掺杂有相应杂质的SiC材料。例如，第一N型半导体区可以是采用外延生长形成的外延层的部分区域，第二N型半导体区和源区可以是采用离子注入工艺，通过对外延层进行掺杂形成的。并且，N型半导体区中掺杂的主要是N型杂质，例如氮(N)、磷(P)或砷(As)等。示例性地，半导体衬底的掺杂浓度一般大于第二N型半导体区的掺杂浓度，第二N型半导体区的掺杂浓度一般大于第一N型半导体区的掺杂浓度，源区的掺杂浓度一般大于第二N型半导体区的掺杂浓度。
在本申请中，第二P型半导体区和第一P型半导体区可以是采用离子注入工艺，通过对外延层进行掺杂形成的。并且，P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。
本申请对栅极11的材料不作限定，例如，栅极的材料可以是多晶硅材料，也可以是金属(例如W、Al、Ti、Cu、Mo或Pt)等其它具有良好导电特性的材料。
本申请对形成层间介质层的材料不作限定，例如，形成层间介质层的材料可以是介电材料，该介电材料包括但不限于二氧化硅(SiO 2)、氮氧化硅(SiNO)、碳氧化硅(SiCO)、氮化硅(SiNx)等。
本申请对形成源极和漏极的材料不作限定，例如，形成源极和漏极的材料可以为金属材料。示例性地，该金属材料可以包括W、Al、Ti、Cu、Mo或Pt等。
在本申请一些可能的实现方式中，半导体器件中可以存在多个沟槽结构和多个接触孔，具体可以在相邻的两个接触孔之间设置一个沟槽结构，这样可以使信号流通较均匀。当存在多个沟槽结构时，各沟槽结构中的结构参数可以相同，可以保证沟槽结构均匀分布。例如第一沟槽的数量可以相同，第一沟槽之间的沟槽间距可以相同，各第一沟槽的沟槽长度可以相同，第二沟槽的长度可以相同。在实际应用中，沟槽结构中的第一沟槽的数量，可以根据实际应用的需求进行确定，本申请对此不作限定。
在本申请一些可能的实现方式中，也可以使部分沟槽结构中的第一沟槽的数量相同，其余部分沟槽结构中的第一沟槽的数量不同。或者，也可以使不同沟槽结构中的第一沟槽的数量不同。在实际应用中，沟槽结构中的第一沟槽的数量，可以根据实际应用的需求进行确定，本申请对此不作限定。
在本申请一些可能的实现方式中，在第二方向上，可以将沟槽结构中处于边缘的两个第一沟槽分别定义为第一边缘沟槽和第二边缘沟槽，接触孔由第一边缘沟槽背离第二边缘沟槽的一侧沿第二方向延伸至第二边缘沟槽背离第一边缘沟槽的一侧。也就是说，接触孔是连续的开口，并且不同沟槽结构中的第一沟槽之间并未贯通。
在本申请一些可能的实施方式中，外延层还可以包括：第三P型半导体区和第四P型半导体区。第三P型半导体区设置于沟槽结构的至少一个侧壁，第四P型半导体区和源区同层设置。第三P型半导体区与第一P型半导体区相互接触，第四P型半导体区与第三P型半导体区一一对应设置且相互接触。电压可以依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，从而能够有效屏蔽沟槽结构底部的栅介质层电场，进而提升器件工作的鲁棒性。
具体地，第二P型半导体区、第一P型半导体区、第三P型半导体区以及第四P型半 导体区，可以是采用离子注入工艺，通过对外延层进行掺杂形成的。并且，P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。
示例性地，第一P型半导体区、第三P型半导体区以及第四P型半导体区的掺杂浓度大于第二P型半导体区的掺杂浓度。可选地，第一P型半导体区、第三P型半导体区以及第四P型半导体区的掺杂浓度可相同或相似。当然，也可以使第一P型半导体区、第三P型半导体区以及第四P型半导体区的掺杂浓度至少两个不相同。需要说明的是，第一P型半导体区、第三P型半导体区以及第四P型半导体区的掺杂浓度，可以根据实际应用环境的需求进行确定，在此不作限定。
在本申请一些可能的实施方式中，在第一方向上，多个第一沟槽中的每个第一沟槽可以具有相对设置的第一侧壁和第二侧壁，第三P型半导体区可以设置于多个第一沟槽中的至少一个第一沟槽的第一侧壁和第二侧壁，也就是说，至少一个第一沟槽的第一侧壁和第二侧壁分别设置了第三P型半导体区。并且，第三P型半导体区均与第一P型半导体区相互接触，从而可以使第三P型半导体区均与第一P型半导体区连接，进行信号传输，则第三P型半导体区均与第一P型半导体区的电压相同。相应地，第四P型半导体区与第三P型半导体区一一对应且接触设置，第四P型半导体区通过接触孔与对应的源极接触。其中，设置于第一侧壁的第三P型半导体区对应设置一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离第一沟槽的第一侧壁的一侧。以及，设置于第二侧壁的第三P型半导体区对应设置一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离第一沟槽的第二侧壁的一侧。源极依次通过相互对应设置的第四P型半导体区和第三P型半导体区与第一P型半导体区连接，以使源极加载的电压依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，使第一P型半导体区具有电压，从而能够有效屏蔽沟槽结构底部的栅介质层电场，进而提升器件工作的鲁棒性。
在本申请一些可能的实施方式中，可以设置多个第三P型半导体区，每一个第一沟槽的第一侧壁设置多个第三P型半导体区中的一个第三P型半导体区，并且每一个第一沟槽的第二侧壁也设置多个第三P型半导体区中的一个第三P型半导体区。也就是说，每一个第一沟槽的第一侧壁和第二侧壁分别设置了第三P型半导体区。并且，这些第三P型半导体区均与第一P型半导体区相互接触，从而可以使第三P型半导体区均与第一P型半导体区连接，进行信号传输，则第三P型半导体区均与第一P型半导体区的电压相同。相应地，可以设置多个第四P型半导体区，该多个第四P型半导体区与上述多个第三P型半导体区一一对应且接触设置。其中，设置于第一侧壁的第三P型半导体区对应设置多个第四P型半导体区中的一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离第一沟槽的第一侧壁的一侧。以及，设置于第二侧壁的第三P型半导体区对应设置多个第四P型半导体区中的一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离第一沟槽的第二侧壁的一侧。源极依次通过相互对应设置的第四P型半导体区和第三P型半导体区与第一P型半导体区连接，以使源极加载的电压依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，使第一P型半导体区具有电压，从而能够有效屏蔽沟槽结构底部的栅介质层电场，进而提升器件工作的鲁棒性。
在本申请一些可能的实施方式中，也可以设置了多个源区，位于沟槽结构同一端的多个源区和多个第四P型半导体区交替设置。例如，位于同一沟槽结构中多个第一沟槽的第一侧壁处的多个源区和多个第四P型半导体区交替设置。以及，位于同一沟槽结构中多个 第一沟槽的第二侧壁处的多个源区和多个第四P型半导体区交替设置。
具体地，本申请对第四P型半导体区沿第二方向的宽度不作限定，例如，可以使第四P型半导体区沿第二方向的宽度与第一沟槽的宽度相同或相似，相应地，源区沿第二方向的宽度与相邻两个第一沟槽之间的沟槽间距相同或相似。当然，也可以使第四P型半导体区沿第二方向的宽度与第一沟槽的宽度不同，在此不作限定。
具体地，在第二方向上，相邻两个第一沟槽之间具有沟槽间距。本申请对沟槽间距的具体数值不作限定，例如，沟槽间距可以小于1um。可选地，沟槽间距的范围为50nm～0.5um。需要说明的是，沟槽间距小于100nm时，本申请提供的半导体器件将形成鳍式场效应晶体管(Fin Field-Effect Transistor，Fin FET)效应，可显著提高载流子沟道迁移率，进一步降低器件导通总电阻。
具体地，在第一方向上，第一沟槽具有沟槽长度。本申请对沟槽长度不作限定，例如，沟槽长度可以大于5um。
具体地，在第二方向上，第一沟槽具有沟槽宽度。本申请对沟槽宽度不作限定，例如，沟槽宽度可以小于1um。
具体地，在第一方向上，接触孔具有接触宽度，可以使沟槽间距不大于接触宽度。当然，也可以使沟槽间距大于接触宽度。在实际应用中，沟槽间距与接触宽度可以根据实际应用的环境需求进行确定，在此不作限定。
在本申请一些可能的实施方式中，第一P型半导体区是在沟道结构形成后，在沟槽结构的底部采用垂直离子注入工艺形成的，因此，第一P型半导体区在第三方向上的投影可以覆盖沟槽结构。并且，由于离子注入工艺过程中离子的扩散性，第一P型半导体区会向沟槽结构的底部外围扩散，即呈现出第一P型半导体区在半导体衬底上的正投影边缘位于沟槽结构在半导体衬底1的正投影边缘的外围。
在本申请一些可能的实施方式中，沟槽结构中的沟槽间距大于离子注入扩散尺寸时，例如在沟槽间距大于0.4um时，第一P型半导体区在各第一沟槽底部的部分之间会存在一定的间距，此时，第一P型半导体区在半导体衬底1上的正投影形状与沟槽结构在半导体衬底上的正投影形状相似。
在本申请一些可能的实施方式中，沟槽结构中的沟槽间距小于离子注入扩散尺寸时，例如在沟槽间距小于0.4um时，离子会扩散并充满第一沟槽之间的间距区域，即在第三方向上，第一P型半导体区还可以覆盖相邻两个第一沟槽之间的间隙。也就是说，第一P型半导体区在半导体衬底1上的正投影还覆盖相邻两个第一沟槽之间在第二方向上的间隙在半导体衬底上的正投影。此时，第一P型半导体区可以认为是沿第二方向延伸的面状区域，第一P型半导体区的形状可认为是矩形。
在本申请一些可能的实施方式中，第一P型半导体区在第三方向上的投影还可以覆盖第三P型半导体区。也就是说，第一P型半导体区在半导体衬底上的正投影不仅覆盖沟槽结构在半导体衬底上的正投影，还覆盖所有的第三P型半导体区在半导体衬底上的正投影。
在本申请一些可能的实施方式中，一般一个沟槽结构对应设置一个第一P型半导体区。也就是说，若设置了一个沟槽结构，则相应地设置一个第一P型半导体区。若设置了两个沟槽结构，则相应地设置两个第一P型半导体区。并且，这两个第一P型半导体区之间存在间隙。若设置了多个沟槽结构，则相应地设置多个第一P型半导体区。并且，每相邻两个第一P型半导体区之间存在间隙。
本申请实施例提供的半导体器件中，沟槽结构在第二方向上的第一沟槽的两个侧壁处的第二P型半导体区形成了SiC MOSFET的沟道区，因而，通过增大沟槽宽度或减小沟槽间距，可提高SiC MOSFET器件的导电沟道密度，降低SiC MOSFET器件的导通总电阻。
在本申请一些可能的实施方式中，半导体器件具体可以包括：N型的半导体衬底、外延层、沟槽结构、栅极、层间介质层、源极以及漏极。并且，外延层可以包括：第一N型半导体区、第二N型半导体区、第二P型半导体区、源区、第一P型半导体区、第三P型半导体区以及第四P型半导体区。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本实施例中，设置多个第三P型半导体区，在每一个第一沟槽的第一侧壁设置多个第三P型半导体区中的一个第三P型半导体区，并且在每一个第一沟槽的第二侧壁未设置第三P型半导体区。也就是说，仅在每一个第一沟槽的第一侧壁处分别设置第三P型半导体区。并且，这些第三P型半导体区均与第一P型半导体区相互接触，使第三P型半导体区均与第一P型半导体区连接，进行信号传输，则第三P型半导体区均与第一P型半导体区的电压相同。
相应地，也设置多个第四P型半导体区，该多个第四P型半导体区与上述多个第三P型半导体区一一对应且接触设置。其中，设置于第一侧壁的第三P型半导体区对应设置多个第四P型半导体区中的一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离第一沟槽的第一侧壁的一侧。源极依次通过相互对应设置的第四P型半导体区和第三P型半导体区与第一P型半导体区连接，以使源极加载的电压依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，使第一P型半导体区具有电压，从而能够有效屏蔽沟槽结构底部的栅介质层电场，进而提升器件工作的鲁棒性。
在本实施例中，外延层还可以包括：第五P型半导体区，第五P型半导体区和源区同层设置，第五P型半导体区设置于第一沟槽的第二侧壁背离第一侧壁的一侧，且第五P型半导体区通过接触孔与源极接触。
在本实施例中，可以设置多个第五P型半导体区，该多个第五P型半导体区与每一个第一沟槽的第二侧壁一一对应设置。并且，位于第一沟槽的第二侧壁的多个源区和多个第五P型半导体区交替设置。
可选地，第五P型半导体区可以是采用离子注入工艺，通过对外延层进行掺杂形成的。并且，第五P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。示例性地，第五P型半导体区的掺杂浓度可以与第四P型半导体区的掺杂浓度相同或相似。
本申请实施例中，第一沟槽的第一侧壁处设置第三P型半导体区，不形成沟道。
在本申请一些可能的实施方式中，半导体器件可以具体包括：N型的半导体衬底、外延层、沟槽结构、栅极、层间介质层、源极以及漏极。并且，外延层可以包括：第一N型半导体区、第二N型半导体区、第二P型半导体区、源区、第一P型半导体区、第三P型半导体区以及第四P型半导体区。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本实施例中，设置多个第三P型半导体区，每一个第一沟槽的第一侧壁设置多个第三P型半导体区中的一个第三P型半导体区，并且每一个第一沟槽的第二侧壁未设置第三P型半导体区。也就是说，仅在每一个第一沟槽的第一侧壁处分别设置第三P型半导体区。并且，这些第三P型半导体区均与第一P型半导体区相互接触，使第三P型半导体区均与 第一P型半导体区连接，进行信号传输，则第三P型半导体区均与第一P型半导体区的电压相同。
在本实施例中，也设置多个第四P型半导体区，该多个第四P型半导体区与上述多个第三P型半导体区一一对应且接触设置。其中，设置于第一侧壁的第三P型半导体区对应设置多个第四P型半导体区中的一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离第一沟槽的第一侧壁的一侧。源极依次通过相互对应设置的第四P型半导体区和第三P型半导体区与第一P型半导体区连接，以使源极加载的电压依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，使第一P型半导体区具有电压，从而能够有效屏蔽沟槽结构底部的栅介质层电场，进而提升器件工作的鲁棒性。
在本实施例中，仅在第一沟槽的第一侧壁处设置了第四P型半导体区，而在第一沟槽的第二侧壁处设置的均为源区。
在本申请一些可能的实施例中，第一沟槽的第一侧壁和第二侧壁位置也可以互换，即可以在第一沟槽的第二侧壁设置多个第三P型半导体区中的一个第三P型半导体区，并且在每一个第一沟槽的第一侧壁未设置第三P型半导体区。
在本申请一些可能的实施方式中，半导体器件具体可以包括：N型的半导体衬底、外延层、沟槽结构、栅极、层间介质层、源极以及漏极。并且，外延层可以包括：第一N型半导体区、第二N型半导体区、第二P型半导体区、源区、第一P型半导体区、第三P型半导体区以及第四P型半导体区。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本实施例中，第二沟槽的至少一个端部可以伸出多个第一沟槽中位于边缘的第一沟槽，在第二方向上，第二沟槽可以具有相对设置的第三侧壁和第四侧壁，第三P型半导体区可以设置于第二沟槽的第三侧壁和/或第四侧壁。示例性地，第二沟槽的两个端部可以均伸出多个第一沟槽中位于边缘的第一沟槽，第三P型半导体区可以设置于第二沟槽的第三侧壁和第四侧壁，也就是说，第二沟槽的第三侧壁和第四侧壁分别设置第三P型半导体区。并且，第三P型半导体区均与第一P型半导体区相互接触，从而可以使第三P型半导体区均与第一P型半导体区连接，进行信号传输，则第三P型半导体区均与第一P型半导体区的电压相同。相应地，第四P型半导体区与第三P型半导体区一一对应且接触设置。其中，设置于第三侧壁的第三P型半导体区对应设置一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离第二沟槽的第三侧壁的一侧。以及，设置于第四侧壁的第三P型半导体区对应设置一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离第二沟槽的第四侧壁的一侧。电压可以依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，使第一P型半导体区具有电压，从而能够有效屏蔽沟槽结构底部的栅介质层电场，进而提升器件工作的鲁棒性。
在本实施例中，外延层还可以包括：第五P型半导体区，第五P型半导体区和源区同层设置，第五P型半导体区可以设置于第一沟槽的第二侧壁背离第一侧壁的一侧，第五P型半导体区还可以设置于第一沟槽的第一侧壁背离第二侧壁的一侧，且第五P型半导体区通过接触孔与源极接触。
在本实施例中，可以设置多个第五P型半导体区，该多个第五P型半导体区与每一个第一沟槽的第一侧壁和第二侧壁一一对应设置。并且，位于第一沟槽的第一侧壁的多个源区和多个第五P型半导体区交替设置，位于第一沟槽的第二侧壁的多个源区和多个第五P 型半导体区交替设置。
可选地，第五P型半导体区可以是采用离子注入工艺，通过对外延层进行掺杂形成的。并且，第五P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。示例性地，第五P型半导体区的掺杂浓度可以与第四P型半导体区的掺杂浓度相同或相似。
本申请实施例中，第二沟槽的第三侧壁和第四侧壁处设置第三P型半导体区，不形成沟道。
在本申请一些可能的实施方式中，半导体器件具体可以包括：N型的半导体衬底、外延层、沟槽结构、栅极、层间介质层、源极以及漏极。并且，外延层可以包括：第一N型半导体区、第二N型半导体区、第二P型半导体区、源区、第一P型半导体区、第三P型半导体区以及第四P型半导体区。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
本申请实施例中，相邻两个沟槽结构中的部分沟槽结构中，沿第一方向排列的第一沟槽贯通。例如，左右相邻的两个沟槽结构中的第一边缘沟槽沿第一方向排列，且两个第一边缘沟槽相互贯通。左右相邻的两个沟槽结构中的第二边缘沟槽沿第一方向排列，且两个第二边缘沟槽相互贯通。又如，左侧沟槽结构中间的一条第一沟槽也可以和右侧沟槽结构中间的一条第一沟槽相互贯通。
相应地，接触孔可以划分为多个相互间隔设置的子接触孔，同一接触孔中相邻的两个子接触孔之间设置有至少一个贯通的第一沟槽。本申请对接触孔划分为的子接触孔的数量不作限定，例如，可以为两个、三个、四个或更多个。并且，本申请对同一接触孔中相邻的两个子接触孔之间设置的贯通的第一沟槽的数量也不作限定，例如，可以为一个、两个、三个、四个或更多个。这样可以提高接触孔的设计自由度，可提升SiC MOSFET器件的通流均匀性。
在本申请一些可能的实施方式中，半导体器件可以具体包括：N型的半导体衬底、外延层、沟槽结构、栅极、层间介质层、源极以及漏极。并且，外延层可以包括：第三N型半导体区、第一N型半导体区、第二N型半导体区、第二P型半导体区、源区、第一P型半导体区、第三P型半导体区以及第四P型半导体区。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本实施例中，第三N型半导体区可以设置于第一N型半导体区与半导体衬底之间。由于设置了第三N型半导体区，则可以使外延层中的第一P型半导体区在第三方向上的厚度设置的较厚一些，例如，可使第一P型半导体区在第三方向上的厚度设置大于1um。
在本实施例中，第三N型半导体区可以为掺杂有N型杂质的SiC，该N型杂质例如为氮(N)、磷(P)或砷(As)等。示例性地，第三N型半导体区的掺杂浓度可以小于第一N型半导体区的掺杂浓度。
第二方面，本申请实施例还提供了半导体器件的制备方法，在该制备方法中，可以包括以下步骤：在N型的半导体衬底上外延生长外延层；刻蚀外延层形成沟槽结构，沟槽结构包括多个第一沟槽和一个第二沟槽，多个第一沟槽中的每个第一沟槽沿平行于半导体衬底所在平面的第一方向延伸，且沿平行于半导体衬底所在平面的第二方向间隔排列，第二沟槽沿第二方向延伸，且第二沟槽与多个第一沟槽中的每个第一沟槽交叉设置且相互导通；在沟槽结构的底部形成第一P型半导体区，第一P型半导体区在第三方向上的投影覆盖沟 槽结构；在沟槽结构内依次形成栅介质层和栅极；在栅极上形成覆盖外延层的层间介质层；刻蚀层间介质层形成沿第二方向延伸的接触孔，接触孔暴露出外延层的部分区域，且接触孔在第三方向上的投影与栅极互不交叠；第一方向、第二方向以及第三方向相互交叉设置；在层间介质层上形成源极，源极通过接触孔与接触孔暴露出的外延层接触；在半导体衬底远离外延层的一侧形成漏极。
在一些可能的实施方式中，制备方法还可以包括：在沟槽结构内依次形成栅介质层和栅极之前，在沟槽结构的至少一个侧壁采用倾斜离子注入工艺，形成与第一P型半导体区接触的第三P型半导体区；采用离子注入工艺，在外延层中形成与源区同层设置的第四P型半导体区。
在一些可能的实施方式中，为了形成外延层，在N型的半导体衬底上外延生长外延层，可以包括如下步骤：采用外延工艺，在N型的SiC半导体衬底上，外延生长掺杂有N型杂质的SiC材料，形成外延层。本申请对外延层厚度的具体数值不作限定。在实际应用中，可以根据实际应用环境的需求，确定外延层厚度的具体数值。
在一些可能的实施方式中，在N型的半导体衬底上外延生长外延层之后，制备方法还可以包括：采用离子注入工艺，在外延层的部分区域中进行离子注入，依次形成第二N型半导体区、第二P型半导体区以及源区，外延层中未进行离子注入的区域形成第一N型半导体区。示例性地，为了形成第二N型半导体区、第二P型半导体区以及源区，外延层中未进行离子注入的区域形成第一N型半导体区。采用离子注入工艺，在外延层的部分区域中进行离子注入，形成第二N型半导体区、第二P型半导体区以及源区，第一外延层中未进行离子注入的区域形成第一N型半导体区，可以包括如下步骤：
采用离子注入工艺，在外延层的表面进行N型杂质掺杂，形成第二N型半导体区。之后，采用离子注入工艺，在外延层的表面进行P型杂质掺杂，形成第二P型半导体区。之后，采用离子注入工艺，在外延层的表面进行N型杂质掺杂，形成源区，以及在第一沟槽的第一侧壁和第二侧壁处的外延层的表面进行P型杂质掺杂，形成与源区同层设置的第四P型半导体区。因此，本申请实施例中，经过该离子注入工艺后，外延层的部分区域形成了第二N型半导体区、第二P型半导体区、源区以及第四P型半导体区，而外延层中未采用该离子注入工艺进行离子注入的区域，则形成了第一N型半导体区。
在一些可能的实施方式中，为了形成沟槽结构，刻蚀外延层至第一N型半导体区，在外延层中形成沟槽结构，可以包括如下步骤：
首先，在外延层上形成沟槽掩膜(该沟槽掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该沟槽掩膜将不需要形成沟槽结构的外延层中的区域遮盖上，而将需要形成沟槽结构的外延层中的区域暴露出来。之后，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对外延层中未被沟槽掩膜遮盖的区域进行刻蚀，直至刻蚀至第一N型半导体区中，且暴露出第一P型半导体区时停止刻蚀，以在外延层中形成由多个第一沟槽和第二沟槽构成的沟槽结构。
在一些可能的实施方式中，为了形成第一P型半导体区，在沟槽结构的底部形成第一P型半导体区，在第三方向上，第一P型半导体区覆盖沟槽结构，可以包括如下步骤：
采用垂直离子注入工艺，向沟槽结构的底部掺杂P型杂质，形成与沟槽结构底部图形一致或面状区域的第一P型半导体区。本申请对第一P型半导体区的厚度(即在第三方向上的厚度)不作限定。在实际应用中，可以根据实际应用环境的需求，确定第一P型半导 体区的厚度的具体数值。
在一些可能的实施方式中，为了形成第三P型半导体区，采用倾斜离子注入工艺，在每一个第一沟槽沿第一方向上的第一侧壁和第二侧壁上，分别形成与第一P型半导体区接触的第三P型半导体区，可以包括如下步骤：
采用倾斜离子注入工艺，在每一个第一沟槽的第一侧壁和第二侧壁的表面进行P型杂质掺杂，分别形成与第一P型半导体区接触的第三P型半导体区。
在一些可能的实施方式中，为了形成栅介质层，在沟槽结构中形成栅介质层，可以包括如下步骤：采用氧化工艺，对沟槽结构的表面进行氧化处理，使沟槽结构的表面形成栅介质层。
在一些可能的实施方式中，为了形成栅极，在形成有栅介质层的沟槽结构中形成栅极，可以包括如下步骤：
首先，采用沉积工艺，在形成有沟槽结构的外延层的整体上沉积多晶硅材料，并使该多晶硅材料填充沟槽结构，且在采用多晶硅材料填充沟槽结构后外延层的整体上覆盖多晶硅材料膜层。接着，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对未被沟槽掩膜遮盖的多晶硅材料区域进行刻蚀，直至刻蚀至暴露出源区和第四P型半导体区时停止刻蚀，以形成栅极。
在一些可能的实施方式中，为了形成层间介质层，在栅极上形成覆盖整个外延层的层间介质层，可以包括如下步骤：采用沉积工艺，在整个外延层上沉积层间介质层，并使层间介质层覆盖整个外延层。
在一些可能的实施方式中，为了形成接触孔，刻蚀层间介质层，形成沿第二方向延伸的接触孔，可以包括如下步骤：
首先，在外延层上形成接触孔掩膜(该接触孔掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该接触孔掩膜将不需要形成接触孔的区域遮盖上，而将需要形成接触孔的区域暴露出来。之后，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对层间介质层未被接触孔掩膜遮盖的区域进行刻蚀，暴露出源区的部分区域，例如源区在第一方向上位于栅极两侧的部分，以及暴露出第四P型半导体区位于栅极两侧的部分。
在一些可能的实施方式中，为了形成源极和漏极，在层间介质层上形成源极，并使源极通过接触孔与源区接触。以及在半导体衬底远离外延层的一侧形成漏极，可以包括如下步骤：
采用沉积工艺，在层间介质层上沉积金属材料，形成源极。并通过金属材料填充接触孔，使源极通过接触孔中填充的金属材料与源区接触。示例性地，可以在形成源极之前，采用沉积工艺，在半导体衬底远离外延层的一侧沉积金属材料，形成漏极。或者，也可以在形成源极之后，采用沉积工艺，在半导体衬底远离外延层的一侧沉积金属材料，形成漏极。
本申请对源极和漏极的材料不作限定，例如，形成源极和漏极的材料可以为金属材料。示例性地，该金属材料可以包括W、Al、Ti、Cu、Mo或Pt。
第三方面，本申请实施例还提供了一种功率转换电路，该功率转换电路可以为交流-直流转换电路和/或直流-直流转换电路。该功率转换电路可以包括：电路板和一个或多个半导体器件，并且该半导体器件与电路板连接。其中，该半导体器件可以为如第一方面或 第一方面的各种可能设计中的半导体器件，或者如采用第二方面或第二方面的各种可能设计中制备的半导体器件。由于上述半导体器件的性能较好，因而，包括上述半导体器件的功率转换电路的性能也较好。以及，该功率转换电路解决问题的原理与前述半导体器件可以解决问题的原理相似，因此该功率转换电路的技术效果可以参照前述半导体器件的技术效果，重复之处不再赘述。
第四方面，本申请实施例还提供了一种车辆，该车辆可以包括功率转换电路。其中，该功率转换电路可以为如第三方面或第三方面的各种可能设计中的功率转换电路。由于上述功率转换电路的性能较好，因而，包括上述功率转换电路的车辆的电路性能也较好。以及，该车辆解决问题的原理与前述功率转换电路可以解决问题的原理相似，因此该车辆的技术效果可以参照前述功率转换电路的技术效果，重复之处不再赘述。
附图说明
图1为SiC MOSFET器件中沟道区电阻和JFET区电阻之间的关系图；
图2a为本申请一种实施例提供的电动汽车的结构示意图；
图2b为本申请一种实施例提供的电子设备的结构示意图；
图3为本申请一种实施例提供的半导体器件的俯视结构示意图；
图4为图3中沿A1A2切线方向上的剖视结构示意图；
图5为图3中沿A3A4切线方向上的剖视结构示意图；
图6a为图3中沿V1V2切线方向上的一种剖视结构示意图；
图6b为图3中沿V1V2切线方向上的另一种剖视结构示意图；
图7为图3中沿V3V4切线方向上的剖视结构示意图；
图8为图3中的局部立体结构示意图；
图9为图8所示的半导体器件中未设置层间介质层和源极时的立体结构示意图；
图10为图8所示的半导体器件中的沟槽结构的立体结构示意图；
图11为本申请实施例提供的半导体器件产生导通电流时的一些示意图；
图12为图11中沿C1C2切线方向上的剖视结构示意图；
图13为本申请实施例提供的半导体器件的制备方法的一些流程图；
图14a至图14i分别为本申请实施例提供的一种制备半导体器件的过程的结构示意图；
图15为本申请另一种实施例提供的半导体器件的立体结构示意图；
图16为图15所示的半导体器件中未设置层间介质层和源极时的立体结构示意图；
图17为图15所示的半导体器件中的沟槽结构的结构示意图；
图18为本申请又一种实施例提供的半导体器件的立体结构示意图；
图19为图18所示的半导体器件中未设置层间介质层和源极时的立体结构示意图；
图20为图18所示的半导体器件中的沟槽结构的立体结构示意图；
图21为本申请另一种实施例提供的半导体器件的俯视结构示意图；
图22为图21中沿B1B2切线方向上的剖视结构示意图；
图23为图21中沿B3B4切线方向上的剖视结构示意图；
图24a为图21中沿X1X2切线方向上的一种剖视结构示意图；
图24b为图21中沿X1X2切线方向上的另一种剖视结构示意图；
图25为图21中沿X3X4切线方向上的剖视结构示意图；
图26为图21中的局部立体结构示意图；
图27为图26所示的半导体器件中未设置层间介质层和源极时的立体结构示意图；
图28为图27所示的半导体器件中的局部立体结构示意图；
图29为本申请另一种实施例提供的半导体器件的俯视结构示意图；
图30为本申请又一种实施例提供的半导体器件的俯视结构示意图；
图31为本申请又一种实施例提供的半导体器件的立体结构示意图。
附图标记：
010-电动汽车，012-蓄电池，0100-电子设备，0110-功率转换电路，0120-负载模块，0200-电源，0111-DC-DC转换器，1-半导体衬底，100-外延层，2-第一N型半导体区，3-第二N型半导体区，4-第二P型半导体区，5-第四P型半导体区，6-源区，7-沟槽结构，8-第一P型半导体区，9-第三P型半导体区，10-栅介质层，11-栅极，12-层间介质层，13-源极，14-漏极，15-第五P型半导体区，16-第三N型半导体区，71-第一沟槽，72-第二沟槽，121-接触孔，x-第一方向，y-第二方向，z-第三方向，C-沟槽间距；D-沟槽长度，E-沟槽宽度，F-接触宽度，S1-第一侧壁，S2-第二侧壁，S3-第三侧壁，S4-第四侧壁。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。方法实施例中的具体操作方法也可以应用于装置实施例或系统实施例中。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本申请实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
需要指出的是，本申请实施例中“连接”指的是电连接，两个电学元件连接可以是两个电学元件之间的直接或间接连接。例如，A与B连接，既可以是A与B直接连接，也可以是A与B之间通过一个或多个其它电学元件间接连接，例如A与B连接，也可以是A与C直接连接，C与B直接连接，A与B之间通过C实现了连接。
并且，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本申请更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
需要说明的是，在以下描述中阐述了具体细节以便于充分理解本申请。但是本申请能够以多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广。因此本申请不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式，然而描述是以说明本申请的一般原则为目的，并非用以限定本申请的范围。
为了方便理解本申请实施例提供的半导体器件、其制备方法、功率转换电路及车辆，下面首先介绍一下其应用场景。
本申请实施例提供的半导体器件可以应用在车辆(例如电动汽车)中，例如可以应用于车载微控制单元(micro controller unit，MCU)、车载电池充电器(on-board battery charger，OBC)等。应注意的是，本申请实施例提出的半导体器件，旨在包括但不限于应用在这些和任意其它适合类型的器件中。下面以车辆为电动汽车为例进行说明。
图2a为本申请实施例提供的电动汽车的结构示意图。参照图2a，电动汽车010中可以包括功率转换电路0110和蓄电池012。
在一种可能的实现方式中，该功率转换电路0110可以包括交流(Alternating Current，AC)-直流(Direct Current，DC)转换电路和DC-DC转换电路，功率转换电路0110也可以称为逆变器。示例性地，在电动汽车充电时，电动汽车010可以与三相电网连接，接收三相电网提供的三相交流电。通过控制功率转换电路0110中的AC-DC转换电路的功率开关管工作，可使AC-DC转换电路将三相交流电转换为直流电，并且通过控制功率转换电路0110中的DC-DC转换电路的功率开关管工作，可使DC-DC转换电路对AC-DC转换电路输出的直流电进行调压，从而为蓄电池012提供电压适配的直流电，进而使蓄电池012可以存储该直流电，实现充电的功能。
在另一种可能的实现方式中，功率转换电路0110还可以是DC-DC转换电路，电动汽车010还可以包括负载013，该负载013可以是电动汽车010的车载设备、动力系统等等。示例性地，通过控制功率转换电路0110的DC-DC转换电路的功率开关管工作，可使功率转换电路0110将蓄电池输出的直流电进行调压后输出给负载013，从而为负载013提供电压适配的直流电。
本申请实施例提供的半导体器件，为沟槽栅结构的MOSFET，可以提高导通沟道密度，同时也不会提高JFET区电阻，从而使导通总电阻降低，进而提升器件性能，降低器件损耗。示例性地，本申请实施例提供的半导体器件可以应用到车辆的功率转换电路0110中，作为AC-DC转换器和/或DC-DC转换器中的功率开关管。由于本申请实施例提供的半导体器件的器件性能较好，在该半导体器件应用于AC-DC转换器和/或DC-DC转换器中时，可以提高AC-DC转换器和/或DC-DC转换器的性能以及降低驱动损耗，从而提高整个电路的性能以及降低驱动损耗。
本申请实施例提供的半导体器件也可以被广泛应用在各种电子设备中，例如可以应用于具有逻辑器件或存储器件等的电子设备中。示例性地，该电子设备可以为智能手机、智能电视、笔记本电脑、掌上电脑(personal digital assistant，PDA)、具备无线通讯功能的可穿戴设备(如智能手表、智能眼镜、智能手环)等。应注意的是，本申请实施例提出的半导体器件，旨在包括但不限于应用在这些和任意其它适合类型的电子设备中。
图2b为本申请实施例提供的电子设备的结构示意图。参照图2b，本申请实施例提供的电子设备0100包括功率转换电路0110及负载模块0120，功率转换电路0110与负载模块0120电性连接。示例性地，电子设备0100可以是任何用电设备。例如，智能手机、智能电视、笔记本电脑、掌上电脑(personal digital assistant，PDA)、具备无线通讯功能的可穿戴设备(如智能手表、智能眼镜、智能手环)、车载微控制单元(micro controller unit，MCU)、车载电池充电器(on-board battery charger，OBC)等。应注意的是，本申请对电子设备的具体类型不作任何限定。
在一些实施例中，功率转换电路0110可以为直流(direct current，DC)-直流功率转换电路，用于将直流电进行升压或降压变化处理后输出直流电，以为负载模块0120供电。例如，功率转换电路0110可将电源0200输出的直流电(例如48V)变换为用于所有类型负载模块0120的直流电，并输出至负载模块0120，以供负载模块0120工作。本申请对电源0200及负载模块0120不作任何限制，电源0200可以是任何能输出直流电的设备或元件，例如，电源0200可以是电池(例如蓄电池)，则功率转换电路0110可以接收电池提供的电池电压，并将电池电压转换为负载模块0120的工作电压后，输出给负载模块0120。负载模块0120可以是任何使用直流电的功能模块，例如负载模块0120可以是处理器、芯片等。
参照图2a，功率转换电路0110可以包括DC-DC转换器0111。具体工作时，DC-DC转换器0111中的MOSFET工作在一定的开关频率下，使DC-DC转换器0111将电源0200的直流电，进行升压或降压变化处理后，输出至负载模块0120以提供工作电压的直流电。示例性地，DC-DC转换器例如可以为：Buck(降压式)转换器、Boost(升压式)转换器、半桥转换器、全桥转换器和电感-电感-电容(inductor-inductor-capacitor，LLC)谐振转换器等。
本申请实施例提供的半导体器件，为沟槽栅结构的MOSFET，可以提高导通沟道密度，同时也不会提高JFET区电阻，从而使导通总电阻降低，进而提升器件性能，降低器件损耗。示例性地，本申请实施例提供的半导体器件可以应用到DC-DC转换器0111中，作为DC-DC转换器0111中的MOSFET。由于本申请实施例提供的半导体器件的器件性能较好，在该半导体器件应用于DC-DC转换器0111中的MOSFET中时，可以提高DC-DC转换器0111的性能以及降低驱动损耗，从而提高整个电子设备的性能以及降低驱动损耗。
需要说明的是，上述场景描述仅是举例说明本申请的半导体器件的一些可实现的应用方式。本申请对本申请实施例提供的半导体器件的具体应用的场景不作限定，可以根据实际应用的需求进行确定。
在本申请提供的一些实施例中，半导体衬底1和外延层100的材料可以为SiC，则本申请实施例提供的半导体器件为SiC MOSFET。
需要明说的是，在本申请中，在前缀有N或P的层和区域中，分别表示电子或者空穴为多数载流子。此外，标记于N或P的“+”表示掺杂浓度比未标记+的层或区域的掺杂浓度高，且“+”的数量越多，表示掺杂浓度越高。且包含有相同数量“+”的N或P表示为相近的掺杂浓度并不限于掺杂浓度相同。以及，标记于N或P的“-”表示掺杂浓度比未标记-的层或区域的掺杂浓度低，且“-”的数量越多，表示掺杂浓度越低。包含有相同数量“-”的N或P表示为相近的掺杂浓度并不限于掺杂浓度相同。
另外还需要说明的是，本申请中两个区的掺杂浓度的比较仅是指该两个区所掺杂的杂质的浓度大小的比较，对杂质的成分，用于掺杂该杂质的衬底不作限定，即杂质的成分可以相同，也可以不相同；用于掺杂该杂质的衬底的材料可以相同，也可以不相同。
图3示出了本申请一种实施例提供的半导体器件的俯视结构示意图，图4示出了图3中沿A1A2切线方向上的剖视结构示意图，图5示出了图3中沿A3A4切线方向上的剖视结构示意图，图6a示出了图3中沿V1V2切线方向上的一种剖视结构示意图，图6b示出了图3中沿V1V2切线方向上的另一种剖视结构示意图，图7示出了图3中沿V3V4切线方向上的剖视结构示意图，图8示出了图3中的局部立体结构示意图，图9示出了图8所示的半导体器件中未设置层间介质层12和源极13时的立体结构示意图，图10示出了图8 所示的半导体器件中沟槽结构的立体结构示意图。
参照图3至图10，本申请实施例提供的半导体器件，具体可以包括：N型的半导体衬底1、外延层100、沟槽结构7、栅极11、层间介质层12、源极13以及漏极14。其中，外延层100可以包括第一P型半导体区8。示例性地，外延层100还可以包括：依次设置于半导体衬底1上的第一N型半导体区2、第二N型半导体区3、第二P型半导体区4以及源区6，第一P型半导体区8设置于第一N型半导体区2内。
在本申请中，半导体衬底1可以为掺杂有五价元素的SiC单晶衬底。外延层100可以采用外延生长生成的掺杂有相应杂质的SiC材料。例如，第一N型半导体区2可以是采用外延生长形成的外延层100的部分区域，第二N型半导体区3和源区6可以是采用离子注入工艺，通过对外延层100进行掺杂形成的。并且，N型半导体区中掺杂的主要是N型杂质，例如氮(N)、磷(P)或砷(As)等。示例性地，半导体衬底1的掺杂浓度一般大于第二N型半导体区3的掺杂浓度，第二N型半导体区3的掺杂浓度一般大于第一N型半导体区2的掺杂浓度，源区6的掺杂浓度一般大于第二N型半导体区3的掺杂浓度。
在本申请中，第二P型半导体区4和第一P型半导体区8可以是采用离子注入工艺，通过对外延层100进行掺杂形成的。并且，P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。
继续参照图3至图10，沟槽结构7设置于外延层100中，且在垂直于半导体衬底1所在平面的第三方向z上，沟槽结构7延伸至第一N型半导体区2中且与第一P型半导体区8接触。第一P型半导体区8在第三方向z上的投影可以覆盖沟槽结构7。沟槽结构7具体可以包括多个第一沟槽71和一个第二沟槽72，多个第一沟槽71中的每个第一沟槽71沿平行于半导体衬底1所在平面的第一方向x延伸，且沿平行于半导体衬底1所在平面的第二方向y间隔排列，第二沟槽72沿第二方向y延伸，且第二沟槽72与多个第一沟槽71中的每个第一沟槽71交叉设置且相互导通，第二沟槽72的主要作用为连通各第一沟槽71，在外延层100中通过设置第一沟槽71和第二沟槽72可以形成紧密排列的沟槽结构7。其中，第一方向x、第二方向y以及第三方向z相互交叉设置，例如，第一方向x、第二方向y以及第三方向z相互垂直设置。
继续参照图3至图10，栅极11隔着栅介质层10填充设置于沟槽结构7内，栅极11中设置于多个第一沟槽71的各部分沿第一方向x延伸，栅极11中设置于第二沟槽72的部分沿第二方向y延伸，并用于连通栅极11中沿第一方向x延伸的各部分。沟槽结构7的存在使栅极11嵌入在SiC材料的外延层100内部，栅极11通过栅介质层10与第二P型半导体区4一起形成SiC MOSFET器件的沟槽栅结构，使本申请实施例提供的半导体器件为沟槽栅结构的SiC MOSFET。
本申请对栅极11的材料不作限定，例如，栅极11的材料可以是多晶硅材料，也可以是金属(例如W、Al、Ti、Cu、Mo或Pt)等其它具有良好导电特性的材料。
继续参照图3至图10，层间介质层12设置在栅极11上且覆盖栅极11。源极13设置于层间介质层12上，即源极13覆盖于整个层间介质层12上。漏极14设置于半导体衬底1远离外延层100的一侧，即漏极14覆盖于半导体衬底1未设置有外延层100的一侧上。在实际应用中，源极13与漏极14之间需要传输信号，则可在层间介质层12中设置沿第二方向y延伸的接触孔121。为了避免源极13与栅极11接触，可使接触孔121在第三方向z上的投影与栅极11互不交叠，即接触孔121与栅极11互不交叠。并使接触孔121暴 露出源区6的部分区域，如接触孔121可以暴露出源区6在第一方向x上位于栅极11两侧的部分，从而使源极13能够通过接触孔121与源区6接触，实现源极13与源区6连接的效果，且源极13可以与第一P型半导体区8导通。在栅极11控制沟道导通时，源极13与漏极14之间即可传输信号，其中，沟槽结构7中的各第一沟槽71在第二方向y上相对设置的两个侧壁的部分即为沟道。
本申请对形成层间介质层12的材料不作限定，例如，形成层间介质层12的材料可以是介电材料，该介电材料包括但不限于二氧化硅(SiO 2)、氮氧化硅(SiNO)、碳氧化硅(SiCO)、氮化硅(SiNx)等。
本申请对形成源极13和漏极14的材料不作限定，例如，形成源极13和漏极14的材料可以为金属材料。示例性地，该金属材料可以包括W、Al、Ti、Cu、Mo或Pt等。
本申请实施例提供的半导体器件，由于层间介质层12中设置的接触孔121的延伸方向为第二方向y，沟槽结构7的各第一沟槽71的延伸方向为第一方向x，则接触孔121的延伸方向与各第一沟槽71的延伸方向相互垂直，即将接触孔121放置在垂直于第一沟道71的方向上，进而相比现有技术中沟槽结构与接触孔相互平行的设置方式，本申请实施例提供的半导体器件，降低了接触孔121对相邻第一沟槽71在第二方向y上的沟槽间距C的限制，能够使沟槽结构制备的更加紧密，即栅极11也会更加紧密。因此，本申请实施例提供的半导体器件的沟槽结构阵列密度，可远高于现有技术中器件结构的沟槽结构阵列密度，因而提高了SiC MOSFET的沟道密度，明显降低了器件的导通总电阻，提升器件性能，降低器件损耗。
并且，在SiC MOSFET器件工作时，源极13会加载电压，由于第一P型半导体区8与源极13导通，则源极13上加载的电压会输入到第一P型半导体区8中，使第一P型半导体区8也具有相应的电压，从而能够有效屏蔽沟槽结构7的底部的栅介质层10电场，进而提升器件工作的鲁棒性。
示例性地，本申请实施例提供的SiC MOSFET在应用到电子设备中时，其源极13可接地，其漏极14可连接其他元件，则SiC MOSFET的源极13的电压为接地电压(0V)。由于第一P型半导体区8与源极13导通，则第一P型半导体区8的电压也为接地电压，从而能够有效屏蔽沟槽结构7底部的栅介质层10电场，进而提升器件工作的鲁棒性。
示例性地，本申请实施例提供的SiC MOSFET在应用到电子设备中时，其源极13也可连接其他元件，其漏极14也连接其他元件，则SiC MOSFET的源极13的电压为其他元件输入的信号的电压。由于第一P型半导体区8与源极13导通，则第一P型半导体区8的电压也为该输入的信号的电压，从而能够有效屏蔽沟槽结构7底部的栅介质层10电场，进而提升器件工作的鲁棒性。
本申请对第一P型半导体区8在第三方向z上的厚度不作限定。在本申请一些实施例中，第一P型半导体区8在第三方向z上的厚度的范围可以小于1um，例如，第一P型半导体区8在第三方向z上的厚度的范围可以为0.3um～0.8um。
在本申请一些实施例中，半导体器件中可以存在多个沟槽结构7和多个接触孔121，具体可以在相邻的两个接触孔121之间设置一个沟槽结构7，这样可以使信号流通较均匀。示例性地，参照图3至图5，示例出两个沟槽结构7和三个接触孔121。当存在多个沟槽结构7时，各沟槽结构7中的结构参数可以相同，可以保证沟槽结构7均匀分布。例如第一沟槽71的数量可以相同，第一沟槽71之间的沟槽间距可以相同，各第一沟槽71的沟 槽长度可以相同，第二沟槽72的长度可以相同。示例性地，参照图3，两个沟槽结构7分别设置了5个第一沟槽71。需要说明的是，图3示出的沟槽结构7中设置的第一沟槽71的数量仅是为了进行解释说明，并不限制实际制备出的半导体器件中的第一沟槽71的数量。在实际应用中，沟槽结构7中的第一沟槽71的数量，可以根据实际应用的需求进行确定，本申请对此不作限定。
在本申请一些实施例中，也可以使部分沟槽结构7中的第一沟槽71的数量相同，其余部分沟槽结构7中的第一沟槽71的数量不同。或者，也可以使不同沟槽结构7中的第一沟槽71的数量不同。在实际应用中，沟槽结构7中的第一沟槽71的数量，可以根据实际应用的需求进行确定，本申请对此不作限定。
在本申请一些实施例中，在第二方向y上，可以将沟槽结构7中处于边缘的两个第一沟槽71分别定义为第一边缘沟槽和第二边缘沟槽，接触孔121由第一边缘沟槽背离第二边缘沟槽的一侧沿第二方向延伸至第二边缘沟槽背离第一边缘沟槽的一侧。示例性地，参照图3，在第二方向y上，将两个沟槽结构7处于上下边缘的两个第一沟槽71分别定义为第一边缘沟槽和第二边缘沟槽，则接触孔121由第一边缘沟槽背离第二边缘沟槽的一侧沿第二方向y延伸至第二边缘沟槽背离第一边缘沟槽的一侧。也就是说，接触孔121是连续的开口，并且不同沟槽结构7中的第一沟槽71之间并未贯通。
在本申请一些实施例中，参照图4、图8至图10，外延层100还可以包括：第三P型半导体区9和第四P型半导体区5。第三P型半导体区9设置于沟槽结构7的至少一个侧壁，第四P型半导体区5和源区6同层设置。第三P型半导体区9与第一P型半导体区8相互接触，第四P型半导体区5与第三P型半导体区9一一对应设置且相互接触。电压可以依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，从而能够有效屏蔽沟槽结构7底部的栅介质层10电场，进而提升器件工作的鲁棒性。
具体地，第二P型半导体区4、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5，可以是采用离子注入工艺，通过对外延层100进行掺杂形成的。并且，P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。
示例性地，第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5的掺杂浓度大于第二P型半导体区4的掺杂浓度。可选地，第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5的掺杂浓度可相同或相似。当然，也可以使第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5的掺杂浓度至少两个不相同。需要说明的是，第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5的掺杂浓度，可以根据实际应用环境的需求进行确定，在此不作限定。
在本申请一些实施例中，参照图4和图10，在第一方向x上，多个第一沟槽71中的每个第一沟槽71可以具有相对设置的第一侧壁S1和第二侧壁S2，第三P型半导体区9可以设置于多个第一沟槽71中的至少一个第一沟槽71的第一侧壁S1和第二侧壁S2，也就是说，至少一个第一沟槽71的第一侧壁S1和第二侧壁S2分别设置了第三P型半导体区9。并且，第三P型半导体区9均与第一P型半导体区8相互接触，从而可以使第三P型半导体区9均与第一P型半导体区8连接，进行信号传输，则第三P型半导体区9均与第一P型半导体区8的电压相同。相应地，第四P型半导体区5与第三P型半导体区9一一对应且接触设置，第四P型半导体区5可以通过接触孔121与对应的源极13接触。其中，设置于第一侧壁S1的第三P型半导体区9对应设置一个第四P型半导体区5，且该第 四P型半导体区5设置于第三P型半导体区9远离第一沟槽71的第一侧壁S1的一侧。以及，设置于第二侧壁S2的第三P型半导体区9对应设置一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离第一沟槽71的第二侧壁S2的一侧。源极13依次通过相互对应设置的第四P型半导体区5和第三P型半导体区9与第一P型半导体区8连接，以使源极13加载的电压依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，使第一P型半导体区8具有电压，从而能够有效屏蔽沟槽结构7底部的栅介质层10电场，进而提升器件工作的鲁棒性。
在本申请一些实施例中，可以设置多个第三P型半导体区9，每一个第一沟槽71的第一侧壁S1设置多个第三P型半导体区9中的一个第三P型半导体区9，并且每一个第一沟槽71的第二侧壁S2也设置多个第三P型半导体区9中的一个第三P型半导体区9。也就是说，每一个第一沟槽71的第一侧壁S1和第二侧壁S2分别设置了第三P型半导体区9。并且，这些第三P型半导体区9均与第一P型半导体区8相互接触，从而可以使第三P型半导体区9均与第一P型半导体区8连接，进行信号传输，则第三P型半导体区9均与第一P型半导体区8的电压相同。相应地，可以设置多个第四P型半导体区5，该多个第四P型半导体区5与上述多个第三P型半导体区9一一对应且接触设置。其中，设置于第一侧壁S1的第三P型半导体区9对应设置多个第四P型半导体区5中的一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离第一沟槽71的第一侧壁S1的一侧。以及，设置于第二侧壁S2的第三P型半导体区9对应设置多个第四P型半导体区5中的一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离第一沟槽71的第二侧壁S2的一侧。源极13依次通过相互对应设置的第四P型半导体区5和第三P型半导体区9与第一P型半导体区8连接，以使源极13加载的电压依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，使第一P型半导体区8具有电压，从而能够有效屏蔽沟槽结构7底部的栅介质层10电场，进而提升器件工作的鲁棒性。
值得注意的是，本申请实施例提供的半导体器件，由于在沟槽结构7的第一侧壁S1和第二侧壁S2处分别设置了第三P型半导体区9，设置于沟槽结构7的第一侧壁S1和第二侧壁S2处的第二P型半导体区4(即第四P型半导体区5下方的第二P型半导体区4)并不会受栅极11的控制而具备沟道的性能。因此，在第二方向y上，栅极11对应的沟槽结构7侧壁的部分即为沟道。
示例性地，参照图8至图10，本申请实施例提供的半导体器件中，也可以设置了多个源区6，位于沟槽结构7同一端的多个源区6和多个第四P型半导体区5交替设置。例如，位于同一沟槽结构7中多个第一沟槽71的第一侧壁S1处的多个源区6和多个第四P型半导体区5交替设置。以及，位于同一沟槽结构7中多个第一沟槽71的第二侧壁S2处的多个源区6和多个第四P型半导体区5交替设置。
具体地，本申请对第四P型半导体区5沿第二方向y的宽度不作限定，例如，可以使第四P型半导体区5沿第二方向y的宽度与第一沟槽71的宽度相同或相似，相应地，源区6沿第二方向y的宽度与相邻两个第一沟槽71之间的沟槽间距C相同或相似。当然，也可以使第四P型半导体区5沿第二方向y的宽度与第一沟槽71的宽度不同，在此不作限定。
具体地，参照图3与图9，在第二方向y上，相邻两个第一沟槽71之间具有沟槽间距 C。本申请对沟槽间距C的具体数值不作限定，例如，沟槽间距C可以小于1um。可选地，沟槽间距C的范围为50nm～0.5um。需要说明的是，沟槽间距C小于100nm时，本申请提供的半导体器件将形成鳍式场效应晶体管(Fin Field-Effect Transistor，Fin FET)效应，可显著提高载流子沟道迁移率，进一步降低器件导通总电阻。
具体地，继续参照图3、图4和图9，在第一方向上，第一沟槽71具有沟槽长度D。本申请对沟槽长度D不作限定，例如，沟槽长度D可以大于5um。
具体地，继续参照图3，在第二方向y上，第一沟槽71具有沟槽宽度E。本申请对沟槽宽度E不作限定，例如，沟槽宽度E可以小于1um。
具体地，继续参照图3，在第一方向x上，接触孔121具有接触宽度F，可以使沟槽间距C不大于接触宽度F。当然，也可以使沟槽间距C大于接触宽度F。在实际应用中，沟槽间距C与接触宽度F可以根据实际应用的环境需求进行确定，在此不作限定。
在本申请一些实施例中，第一P型半导体区8是在沟道结构7形成后，在沟槽结构7的底部采用垂直离子注入工艺形成的，因此，第一P型半导体区8在第三方向z上的投影可以覆盖沟槽结构7。并且，由于离子注入工艺过程中离子的扩散性，第一P型半导体区8会向沟槽结构7的底部外围扩散，即呈现出第一P型半导体区8在半导体衬底1上的正投影边缘位于沟槽结构7在半导体衬底1上的正投影边缘的外围。
在本申请一些实施例中，参照图6a，沟槽结构7中的沟槽间距C大于离子注入扩散尺寸时，例如在沟槽间距C大于0.4um时，第一P型半导体区8在各第一沟槽71底部的部分之间会存在一定的间距，此时，第一P型半导体区8在半导体衬底1上的正投影形状与沟槽结构7在半导体衬底1上的正投影形状相似。
在本申请另一些实施例中，参照图6b，沟槽结构7中的沟槽间距C小于离子注入扩散尺寸时，例如在沟槽间距C小于0.4um时，离子会扩散并充满第一沟槽之间的间距区域，即第一P型半导体区8在第三方向z上的投影还可以覆盖相邻两个第一沟槽71之间的间隙。也就是说，第一P型半导体区8在半导体衬底1上的正投影还覆盖相邻两个第一沟槽71之间在第二方向y上的间隙在半导体衬底1上的正投影。此时，第一P型半导体区8可以认为是沿第二方向y延伸的面状区域，第一P型半导体区8的形状可认为是矩形。
在本申请一些实施例中，参照图3至图10，第一P型半导体区8在第三方向z上的投影还可以覆盖第三P型半导体区9。也就是说，第一P型半导体区8在半导体衬底1上的正投影不仅覆盖沟槽结构7在半导体衬底1上的正投影，还覆盖所有的第三P型半导体区9在半导体衬底1上的正投影。
在本申请一些实施例中，参照图3至图10，一般一个沟槽结构7对应设置一个第一P型半导体区8。也就是说，若设置了一个沟槽结构7，则相应地设置一个第一P型半导体区8。若设置了两个沟槽结构7，则相应地设置两个第一P型半导体区8。并且，这两个第一P型半导体区8之间存在间隙。若设置了多个沟槽结构7，则相应地设置多个第一P型半导体区8。并且，每相邻两个第一P型半导体区8之间存在间隙。
本申请实施例提供的半导体器件中，沟槽结构7在第二方向y上的第一沟槽71的两个侧壁处的第二P型半导体区4形成了SiC MOSFET的沟道区，因而，通过增大沟槽宽度D或减小沟槽间距C，可提高SiC MOSFET器件的导电沟道密度，降低SiC MOSFET器件的导通总电阻。
图11示出了本申请实施例提供的半导体器件产生导通电流时的一些示意图，图12示 出了图11中沿C1C2切线方向上的剖视结构示意图。参照图11与图12，黑色带箭头的直线代表SiC MOSFET导通时的导通电流的流动方向。示例性地，在SiC MOSFET的栅极11上加载正电平的电压时，可以控制本申请提供的沟槽结构7的MOSFET导通，此时若在源极13和漏极14上加载不同的电压(例如，源极13上加载的电压大于漏极14上加载的电压)，则源极13和漏极14之间会产生，如图11与图12所示的由源极13流向漏极14的导通电流。
图13示出了本申请实施例提供的半导体器件的制备方法的一些流程图；图14a至图14i分别示出了本申请实施例提供的一种制备半导体器件的过程的结构示意图。参照图13，以制备图8所示的结构为例，在该制备方法中，可以包括以下步骤：
S10、在N型的半导体衬底上外延生长外延层。
示例性地，步骤S10，包括：
参照图14a，采用外延工艺，外延生长掺杂有N型杂质的SiC材料，形成外延层100。
本申请对外延层100厚度的具体数值不作限定。在实际应用中，可以根据实际应用环境的需求，确定厚度的具体数值。
S20、采用离子注入工艺，在外延层的部分区域中进行离子注入，形成第二N型半导体区、第二P型半导体区以及源区，外延层中未进行离子注入的区域形成第一N型半导体区。
示例性地，参照图14b，采用离子注入工艺，在外延层100的表面进行N型杂质掺杂，形成第二N型半导体区3。之后，采用离子注入工艺，在外延层的表面进行P型杂质掺杂，形成第二P型半导体区4。之后，采用离子注入工艺，在外延层100的表面进行N型杂质掺杂，形成源区6，以及在第一沟槽71的第一侧壁S1和第二侧壁S2处的外延层100的表面进行P型杂质掺杂，形成与源区6同层设置的第四P型半导体区5。
因此，本申请实施例中，经过该离子注入工艺后，外延层100的部分区域形成了第二N型半导体区3、第二P型半导体区4、源区6以及第四P型半导体区5，而外延层100中未采用该离子注入工艺进行离子注入的区域，则形成了第一N型半导体区2。
S30、刻蚀外延层至第一N型半导体区，形成沟槽结构。
示例性地，首先，在外延层上形成沟槽掩膜(该沟槽掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该沟槽掩膜将不需要形成沟槽结构7的外延层中的区域遮盖上，而将需要形成沟槽结构7的外延层中的区域暴露出来。之后，参照图14c，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对外延层中未被沟槽掩膜遮盖的区域进行刻蚀，直至刻蚀至第一N型半导体区2中，且暴露出第一P型半导体区8时停止刻蚀，以在外延层中形成由多个第一沟槽和第二沟槽构成的沟槽结构7。
S40、在沟槽结构的底部形成第一P型半导体区，在第三方向上，第一P型半导体区覆盖沟槽结构；
示例性地，参照图14d，可以采用垂直离子注入工艺，向沟槽结构7的底部掺杂P型杂质，形成与沟槽结构7底部图形一致或面状区域的第一P型半导体区8。
本申请对第一P型半导体区8的厚度(即在第三方向上的厚度)不作限定。在实际应用中，可以根据实际应用环境的需求，确定第一P型半导体区8的厚度的具体数值。
S50、采用倾斜离子注入工艺，在每一个第一沟槽沿第一方向上的第一侧壁和第二侧 壁上，分别形成与第一P型半导体区接触的第三P型半导体区。
示例性地，参照图14e，采用倾斜离子注入工艺，在每一个第一沟槽71的第一侧壁S1和第二侧壁S2的表面进行P型杂质掺杂，分别形成与第一P型半导体区8接触的第三P型半导体区9。
S60、在沟槽结构中形成栅介质层和栅极。
示例性地，参照图14f，首先，采用氧化工艺，对沟槽结构7的表面进行氧化处理，使沟槽结构7的表面形成栅介质层10。
之后，采用沉积工艺，在形成有沟槽结构的外延层的整体上沉积多晶硅材料，并使该多晶硅材料填充沟槽结构，且在采用多晶硅材料填充沟槽结构后外延层的整体上覆盖多晶硅材料膜层。接着，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对多晶硅材料区域进行刻蚀，直至刻蚀至暴露出源区6和第四P型半导体区5时停止刻蚀，以形成栅极11。
S70、在栅极上形成覆盖整个外延层的层间介质层。
示例性地，参照图14g，采用沉积工艺，在整个外延层上沉积层间介质层12，并使层间介质层12覆盖整个外延层。
S80、刻蚀层间介质层，形成沿第二方向延伸的接触孔。
示例性地，首先，在外延层上形成接触孔掩膜(该接触孔掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该接触孔掩膜将不需要形成接触孔121的区域遮盖上，而将需要形成接触孔121的区域暴露出来。之后，参照图14h，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对层间介质层12未被接触孔121掩膜遮盖的区域进行刻蚀，暴露出源区6在第一方向x上位于栅极11两侧的部分以及暴露出第四P型半导体区5位于栅极11两侧的部分。
S90、在层间介质层上形成源极，源极通过接触孔与源区接触，以及在半导体衬底远离外延层的一侧形成漏极。
本申请对源极和漏极的材料不作限定，例如，形成源极和漏极的材料可以为金属材料。示例性地，该金属材料可以包括W、Al、Ti、Cu、Mo或Pt。
示例性地，参照图14i，采用沉积工艺，在层间介质层12上沉积金属材料，形成源极13。并通过金属材料填充接触孔，使源极13通过接触孔121中填充的金属材料与源区6接触。
示例性地，参照图14i，可以在形成源极13之前，采用沉积工艺，在半导体衬底1远离外延层的一侧沉积金属材料，形成漏极14。或者，也可以在形成源极13之后，采用沉积工艺，在半导体衬底1远离外延层的一侧沉积金属材料，形成漏极14。
图15示出了本申请又一种实施例提供的半导体器件的立体结构示意图，图16示出了图15所示的半导体器件中未设置层间介质层和源极时的立体结构示意图，图17示出了图15所示的半导体器件中的沟槽结构的立体结构示意图。
参照图15至图17，在本申请提供的又一些实施例中，本申请实施例提供的半导体器件，具体可以包括：N型的半导体衬底1、外延层、沟槽结构7、栅极11、层间介质层12、源极13以及漏极14。并且，外延层可以包括：第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、源区6、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例 与上述实施例的区别之处，其相同之处在此不作赘述。
参照图15至图17，在本实施例中，设置多个第三P型半导体区9，在每一个第一沟槽71的第一侧壁S1设置多个第三P型半导体区9中的一个第三P型半导体区9，并且在每一个第一沟槽71的第二侧壁S2未设置第三P型半导体区9。也就是说，仅在每一个第一沟槽71的第一侧壁S1处分别设置第三P型半导体区9。并且，这些第三P型半导体区9均与第一P型半导体区8相互接触，使第三P型半导体区9均与第一P型半导体区8连接，进行信号传输，则第三P型半导体区9均与第一P型半导体区8的电压相同。在本申请实施例中，第一沟槽71的第一侧壁S1和第二侧壁S2位置也可以互换，即可以在第一沟槽71的第二侧壁S2设置多个第三P型半导体区9中的一个第三P型半导体区9，并且在每一个第一沟槽71的第一侧壁S1未设置第三P型半导体区9。
相应地，参照图15至图17，也设置多个第四P型半导体区5，该多个第四P型半导体区5与上述多个第三P型半导体区9一一对应且接触设置。其中，设置于第一侧壁S1的第三P型半导体区9对应设置多个第四P型半导体区5中的一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离第一沟槽71的第一侧壁S1的一侧。源极13依次通过相互对应设置的第四P型半导体区5和第三P型半导体区9与第一P型半导体区8连接，以使源极13加载的电压依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，使第一P型半导体区8具有电压，从而能够有效屏蔽沟槽结构7底部的栅介质层10电场，进而提升器件工作的鲁棒性。
示例性地，参照图15至图17，外延层100还可以包括：第五P型半导体区15，第五P型半导体区15和源区6同层设置，第五P型半导体区15设置于第一沟槽71的第二侧壁S2背离第一侧壁S1的一侧，且第五P型半导体区15通过接触孔121与源极13接触。
示例性地，可以设置多个第五P型半导体区15，该多个第五P型半导体区15与每一个第一沟槽71的第二侧壁S2一一对应设置。并且，位于第一沟槽71的第二侧壁S2的多个源区6和多个第五P型半导体区15交替设置。
可选地，第五P型半导体区15可以是采用离子注入工艺，通过对外延层进行掺杂形成的。并且，第五P型半导体区15中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。示例性地，第五P型半导体区15的掺杂浓度可以与第四P型半导体区5的掺杂浓度相同或相似。
本申请实施例中，第一沟槽71的第一侧壁S1处设置第三P型半导体区9，不形成沟道。
以制备图15所示的结构为例，对应的制备方法的流程图可以参照图13。其中，步骤S10～S40、S60～S90可以参照上述的制备方法的描述。
在本实施例中，步骤S50为：采用倾斜离子注入工艺，在每一个第一沟槽沿第一方向上的第一侧壁上，分别形成与第一P型半导体区接触的第三P型半导体区。
示例性地，参照图17，采用倾斜离子注入工艺，在每一个第一沟槽71的第一侧壁S1的表面进行P型杂质掺杂，分别形成与第一P型半导体区8接触的第三P型半导体区9。
图18示出了本申请又一种实施例提供的半导体器件的立体结构示意图，图19示出了图18所示的半导体器件中未设置层间介质层和源极时的立体结构示意图，图20示出了图18所示的半导体器件中的沟槽结构的立体结构示意图。
参照图18至图20，在本申请提供的又一些实施例中，半导体器件可以具体包括：N 型的半导体衬底1、外延层、沟槽结构7、栅极11、层间介质层12、源极13以及漏极14。并且，外延层可以包括：第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、源区6、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图18至图20，在本实施例中，设置多个第三P型半导体区9，每一个第一沟槽71的第一侧壁S1设置多个第三P型半导体区9中的一个第三P型半导体区9，并且每一个第一沟槽71的第二侧壁S2未设置第三P型半导体区9。也就是说，仅在每一个第一沟槽71的第一侧壁S1处分别设置第三P型半导体区9。并且，这些第三P型半导体区9均与第一P型半导体区8相互接触，使第三P型半导体区9均与第一P型半导体区8连接，进行信号传输，则第三P型半导体区9均与第一P型半导体区8的电压相同。在本申请实施例中，第一沟槽71的第一侧壁S1和第二侧壁S2位置也可以互换，即可以在第一沟槽71的第二侧壁S2设置多个第三P型半导体区9中的一个第三P型半导体区9，并且在每一个第一沟槽71的第一侧壁S1未设置第三P型半导体区9。
相应地，参照图18至图20，也设置多个第四P型半导体区5，该多个第四P型半导体区5与上述多个第三P型半导体区9一一对应且接触设置。其中，设置于第一侧壁S1的第三P型半导体区9对应设置多个第四P型半导体区5中的一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离第一沟槽71的第一侧壁S1的一侧。源极13依次通过相互对应设置的第四P型半导体区5和第三P型半导体区9与第一P型半导体区8连接，以使源极13加载的电压依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，使第一P型半导体区8具有电压，从而能够有效屏蔽沟槽结构7底部的栅介质层10电场，进而提升器件工作的鲁棒性。
示例性地，参照图18至图20，仅在第一沟槽71的第一侧壁S1处设置了第四P型半导体区5，而在第一沟槽71的第二侧壁S2处设置的均为源区6。
以制备图18所示的结构为例，对应的制备方法的流程图可以参照图13。其中，步骤S10、S30～S40、S60～S90可以参照上述的制备方法的描述。
在本实施例中，步骤S20为：采用离子注入工艺，在外延层的部分区域中进行离子注入，形成第二N型半导体区、第二P型半导体区以及源区，外延层中未进行离子注入的区域形成第一N型半导体区。
示例性地，参照图20，采用离子注入工艺，在外延层的表面进行N型杂质掺杂，形成第二N型半导体区3。之后，采用离子注入工艺，在外延层的表面进行P型杂质掺杂，形成第二P型半导体区4。之后，采用离子注入工艺，在外延层的表面进行N型杂质掺杂，形成源区6，以及在第一沟槽71的第一侧壁S1处的外延层的表面进行P型杂质掺杂，形成与源区6同层设置的第四P型半导体区5。因此，本申请实施例中，经过该离子注入工艺后，外延层的部分区域形成了第二N型半导体区3、第二P型半导体区4、源区6以及第四P型半导体区5，而外延层中未采用该离子注入工艺进行离子注入的区域，则形成了第一N型半导体区2。
在本实施例中，步骤S50为：采用倾斜离子注入工艺，在每一个第一沟槽沿第一方向上的第一侧壁上，分别形成与第一P型半导体区接触的第三P型半导体区。
示例性地，参照图20，采用倾斜离子注入工艺，在每一个第一沟槽71的第一侧壁S1 的表面进行P型杂质掺杂，分别形成与第一P型半导体区8接触的第三P型半导体区9。
图21示出了本申请另一种实施例提供的半导体器件的俯视结构示意图，图22示出了图21中沿B1B2切线方向上的剖视结构示意图，图23示出了图21中沿B3B4切线方向上的剖视结构示意图，图24a示出了图21中沿X1X2切线方向上的一种剖视结构示意图，图24b示出了图21中沿X1X2切线方向上的另一种剖视结构示意图，图25示出了图21中沿X3X4切线方向上的剖视结构示意图，图26示出了图21中的局部立体结构示意图，图27示出了图26所示的半导体器件中未设置层间介质层和源极时的立体结构示意图，图28示出了图27所示的半导体器件中的局部立体结构示意图。
参照图21至图28，在本申请提供的又一些实施例中，本申请实施例提供的半导体器件，具体可以包括：N型的半导体衬底1、外延层、沟槽结构7、栅极11、层间介质层12、源极13以及漏极14。并且，外延层可以包括：第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、源区6、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本实施例中，第二沟槽72的至少一个端部可以伸出多个第一沟槽71中位于边缘的第一沟槽71，在第二方向y上，第二沟槽72可以具有相对设置的第三侧壁S3和第四侧壁S4，第三P型半导体区9可以设置于第二沟槽72的第三侧壁S3和/或第四侧壁S4。示例性地，参照图21，第二沟槽72的两个端部均伸出多个第一沟槽71中位于边缘的第一沟槽71。参照图25，第三P型半导体区9可以设置于第二沟槽72的第三侧壁S3和第四侧壁S4，也就是说，第二沟槽72的第三侧壁S3和第四侧壁S4分别设置了第三P型半导体区9。并且，第三P型半导体区9均与第一P型半导体区8相互接触，从而可以使第三P型半导体区9均与第一P型半导体区8连接，进行信号传输，则第三P型半导体区9均与第一P型半导体区8的电压相同。相应地，第四P型半导体区5与第三P型半导体区9一一对应且接触设置。其中，设置于第三侧壁S3的第三P型半导体区9对应设置一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离第二沟槽72的第三侧壁S3的一侧。以及，设置于第四侧壁S4的第三P型半导体区9对应设置一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离第二沟槽72的第四侧壁S4的一侧。电压可以依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，使第一P型半导体区8具有电压，从而能够有效屏蔽沟槽结构7底部的栅介质层10电场，进而提升器件工作的鲁棒性。
示例性地，参照图21至图28，外延层100还可以包括：第五P型半导体区15，第五P型半导体区15和源区6同层设置，第五P型半导体区15可以设置于第一沟槽71的第二侧壁S2背离第一侧壁S1的一侧，第五P型半导体区15还可以设置于第一沟槽71的第一侧壁S1背离第二侧壁S2的一侧，且第五P型半导体区15通过接触孔121与源极13接触。
示例性地，可以设置多个第五P型半导体区15，该多个第五P型半导体区15与每一个第一沟槽71的第一侧壁S1和第二侧壁S2一一对应设置。并且，位于第一沟槽71的第一侧壁S1的多个源区6和多个第五P型半导体区15交替设置，位于第一沟槽71的第二侧壁S2的多个源区6和多个第五P型半导体区15交替设置。
可选地，第五P型半导体区15可以是采用离子注入工艺，通过对外延层进行掺杂形成的。并且，第五P型半导体区15中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或 镓(Ga)等。示例性地，第五P型半导体区15的掺杂浓度可以与第四P型半导体区5的掺杂浓度相同或相似。
本申请实施例中，第二沟槽72的第三侧壁S3和第四侧壁S4处设置第三P型半导体区9，不形成沟道。
以制备图26所示的结构为例，对应的制备方法的流程图可以参照图13。其中，步骤S10～S40、S60～S90可以参照上述的制备方法的描述。
在本实施例中，步骤S50为：采用倾斜离子注入工艺，在第二沟槽沿第二方向上的第三侧壁和第四侧壁上，分别形成与第一P型半导体区接触的第三P型半导体区。
示例性地，可以采用倾斜离子注入工艺，在第二沟槽72的第三侧壁S3和第四侧壁S4的表面进行P型杂质掺杂，分别形成与第一P型半导体区8接触的第三P型半导体区9。
图29示出了本申请另一种实施例提供的半导体器件的俯视结构示意图；图30示出了本申请又一种实施例提供的半导体器件的俯视结构示意图。
参照图29和图30，在本申请提供的又一些实施例中，半导体器件具体可以包括：N型的半导体衬底1、外延层、沟槽结构7、栅极11、层间介质层12、源极13以及漏极14。并且，外延层可以包括：第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、源区6、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图29和图30，相邻两个沟槽结构7中的部分沟槽结构7中，沿第一方向x排列的第一沟槽71贯通。即多个第一沟槽71可以包括沿第一方向x贯通的第一栅极沟槽和第二栅极沟槽，其中，第一栅极沟槽和第二栅极沟槽可以认为分别位于相邻的两个沟槽结构。例如，左侧沟槽结构7中的第一边缘沟槽(可以认为是第一栅极沟槽)和右侧沟槽结构7中的第一边缘沟槽(可以认为是第二栅极沟槽)沿第一方向x排列，且两个第一边缘沟槽相互贯通。左侧沟槽结构7中的第二边缘沟槽(可以认为是第一栅极沟槽)和右侧沟槽结构7中的第二边缘沟槽(可以认为是第二栅极沟槽)沿第一方向x排列，且两个第二边缘沟槽相互贯通。参照图30，左侧沟槽结构7中间的一条第一沟槽71也可以和右侧沟槽结构7中间的一条第一沟槽71相互贯通。
相应地，接触孔121可以包括多个相互间隔设置的子接触孔，同一接触孔121中相邻的两个子接触孔之间设置有至少一个贯通的第一沟槽。图30中示意出了两个子接触孔，本申请对接触孔121划分为的子接触孔的数量不作限定，例如，可以为两个、三个、四个或更多个。并且，本申请对同一接触孔121中相邻的两个子接触孔之间设置的贯通的第一沟槽71的数量也不作限定，例如，可以为一个、两个、三个、四个或更多个。这样可以提高接触孔121的设计自由度，可提升SiC MOSFET器件的通流均匀性。
图31示出了本申请又一种实施例提供的半导体器件的立体结构示意图。
参照图31，在本申请提供的又一些实施例中，半导体器件具体可以包括：N型的半导体衬底1、外延层、沟槽结构7、栅极11、层间介质层12、源极13以及漏极14。并且，外延层可以包括：第三N型半导体区16、第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、源区6、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图31，第三N型半导体区16可以设置于第一N型半导体区2与半导体衬底1之间。由于设置了第三N型半导体区16，则可以使外延层100中的第一P型半导体区8在第三方向z上的厚度设置的较厚一些，例如，可使第一P型半导体区8在第三方向z上的厚度设置大于1um。
参照图31，在本实施例中，第三N型半导体区16可以为掺杂有N型杂质的SiC，该N型杂质例如为氮(N)、磷(P)或砷(As)等。示例性地，第三N型半导体区16的掺杂浓度可以小于第一N型半导体区2的掺杂浓度。
以制备图31所示的结构为例，对应的制备方法的流程图可以参照图13。其中，步骤S10～S90可以参照上述的制备方法的描述。
在本实施例中，步骤S10在N型的半导体衬底上外延生长外延层，具体可以采用如下方式实现。
示例性地，参照图31，采用外延工艺，在N型的SiC半导体衬底1上，外延生长掺杂有N型杂质的SiC材料，形成第三N型半导体区16。之后，采用外延工艺，第三N型半导体区16，外延生长掺杂有N型杂质的SiC材料，形成达到第一设定厚度DS1的外延层100。
本申请实施例还提供了功率转换电路，该功率转换电路可以为交流-直流转换电路和/或直流-直流转换电路。该功率转换电路可以包括：电路板和一个或多个半导体器件，并且该半导体器件与电路板连接。由于上述半导体器件的性能较好，因而，包括上述半导体器件的功率转换电路的性能也较好。以及，该功率转换电路解决问题的原理与前述半导体器件可以解决问题的原理相似，因此该功率转换电路的技术效果可以参照前述半导体器件的技术效果，重复之处不再赘述。
本申请实施例还提供了车辆，该车辆包括本申请实施例提供的功率转换电路。由于上述功率转换电路的性能较好，因而，包括上述功率转换电路的车辆的电路性能也较好。以及，该车辆解决问题的原理与前述功率转换电路可以解决问题的原理相似，因此该车辆的技术效果可以参照前述功率转换电路的技术效果，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (22)

  1. 一种半导体器件，其特征在于，包括：
    N型的半导体衬底；
    外延层，所述外延层设置于所述半导体衬底上，所述外延层包括第一P型半导体区；
    沟槽结构，所述沟槽结构设置于所述外延层内，且在垂直于所述半导体衬底所在平面的第三方向上，所述沟槽结构与所述第一P型半导体区接触，所述第一P型半导体区在所述第三方向上的投影覆盖所述沟槽结构；所述沟槽结构包括多个第一沟槽和一个第二沟槽，所述多个第一沟槽中的每个第一沟槽沿平行于所述半导体衬底所在平面的第一方向延伸，且沿平行于所述半导体衬底所在平面的第二方向间隔排列，所述第二沟槽沿所述第二方向延伸，且所述第二沟槽与所述多个第一沟槽中的每个第一沟槽交叉设置且相互导通；所述第一方向、所述第二方向以及所述第三方向相互交叉设置；
    栅极，所述栅极隔着栅介质层填充设置于所述沟槽结构内；
    层间介质层，所述层间介质层设置于所述栅极上且覆盖所述栅极，所述层间介质层具有沿所述第二方向延伸的接触孔，所述接触孔暴露出所述外延层的部分区域，且所述接触孔在所述第三方向上的投影与所述栅极互不交叠；
    源极，所述源极设置于所述层间介质层上，所述源极通过所述接触孔与所述接触孔暴露出的外延层接触，且所述源极与所述第一P型半导体区导通；
    漏极，所述漏极设置于所述半导体衬底远离所述外延层的一侧。
  2. 如权利要求1所述的半导体器件，其特征在于，所述第一P型半导体区在所述半导体衬底上的正投影边缘位于所述沟槽结构在所述半导体衬底上的正投影边缘的外围。
  3. 如权利要求1或2所述的半导体器件，其特征在于，所述第一P型半导体区在所述半导体衬底上的正投影形状与所述沟槽结构在所述半导体衬底上的正投影形状相似；
    或，所述第一P型半导体区在所述第三方向上的投影覆盖所述多个第一沟槽中相邻第一沟槽之间的间隙。
  4. 如权利要求1-3任一项所述的半导体器件，其特征在于，所述外延层还包括：依次设置于所述半导体衬底上的第一N型半导体区、第二N型半导体区、第二P型半导体区以及源区；
    所述第一P型半导体区设置于所述第一N型半导体区内，在所述第三方向上，所述沟槽结构延伸至所述第一N型半导体区中；
    所述接触孔暴露出所述源区的部分区域。
  5. 如权利要求4所述的半导体器件，其特征在于，所述外延层还包括：
    第三P型半导体区，所述第三P型半导体区设置于所述沟槽结构的至少一个侧壁，且所述第三P型半导体区与所述第一P型半导体区接触；
    第四P型半导体区，所述第四P型半导体层与所述源区同层设置，所述第四P型半导体区与所述第三P型半导体区一一对应设置且相互接触。
  6. 如权利要求5所述的半导体器件，其特征在于，所述多个第一沟槽中的每个第一沟槽在所述第一方向上具有相对设置的第一侧壁和第二侧壁；
    所述第三P型半导体区设置于所述多个第一沟槽中的至少一个第一沟槽的第一侧壁和/或第二侧壁，所述第四P型半导体区通过所述接触孔与所述源极接触。
  7. 如权利要求6所述的半导体器件，其特征在于，所述第三P型半导体区仅设置于所述多个第一沟槽中的至少一个第一沟槽的第一侧壁或第二侧壁；
    所述外延层还包括：第五P型半导体区，所述第五P型半导体层与所述源区同层设置，所述第五P型半导体层设置于所述多个第一沟槽侧壁的未设置所述第三P型半导体区的一侧，第五P型半导体区与所述第四P型半导体区的掺杂浓度相同；
    所述第五P型半导体区与所述多个第一沟槽中的对应的第一沟槽的侧壁接触，所述第五P型半导体区通过所述接触孔与对应的所述源极接触；
    在所述第一沟槽朝向所述侧壁的一侧，所述第五P型半导体区与所述源区交替设置。
  8. 如权利要求6或7所述的半导体器件，其特征在于，所述第四P型半导体区的宽度等于所述第一沟槽的宽度，相邻两个所述第一沟槽之间的沟槽间距等于所述源区的宽度。
  9. 如权利要求5所述的半导体器件，其特征在于，所述第二沟槽的至少一个端部伸出至所述多个第一沟槽中位于边缘的第一沟槽；
    所述第二沟槽在所述第二方向上具有相对设置的第三侧壁和第四侧壁；
    所述第三P型半导体区设置于所述第二沟槽的第三侧壁和/或第四侧壁。
  10. 如权利要求9所述的半导体器件，其特征在于，所述外延层还包括：与所述源区同层且与对应的所述源区交替设置的第五P型半导体区，第五P型半导体区与所述第四P型半导体区的掺杂浓度相同；
    所述第五P型半导体区与所述多个第一沟槽中的至少一个第一沟槽的侧壁接触，所述第五P型半导体区通过所述接触孔与对应的所述源极接触。
  11. 如权利要求5-10任一项所述的半导体器件，其特征在于，所述第一P型半导体区、所述第三P型半导体区和所述第四P型半导体区的掺杂浓度均大于所述第二P型半导体区的掺杂浓度。
  12. 如权利要求5-11任一项所述的半导体器件，其特征在于，在所述第三方向上，所述第一P型半导体区覆盖所述第三P型半导体区。
  13. 如权利要求1-12任一项所述的半导体器件，其特征在于，所述多个第一沟槽包括沿所述第一方向贯通的第一栅极沟槽和第二栅极沟槽，其中，所述第一栅极沟槽和第二栅极沟槽分别位于相邻的两个所述沟槽结构；
    所述接触孔包括多个相互间隔设置的子接触孔，同一所述接触孔中相邻的两个子接触 孔之间设置有至少一个贯通的第一沟槽。
  14. 如权利要求4-13任一项所述的半导体器件，其特征在于，所述外延层还包括：设置于所述第一N型半导体区和所述半导体衬底之间的第三N型半导体区，所述第三N型半导体区的掺杂浓度小于所述第一N型半导体区的掺杂浓度；
    所述第一P型半导体区的厚度大于1um。
  15. 如权利要求4-14任一项所述的半导体器件，其特征在于，所述半导体衬底的掺杂浓度大于所述第二N型半导体区的掺杂浓度，所述第二N型半导体区的掺杂浓度大于所述第一N型半导体区的掺杂浓度。
  16. 如权利要求1-15任一项所述的半导体器件，其特征在于，所述半导体衬底和所述外延层的材料为SiC。
  17. 一种半导体器件的制备方法，其特征在于，包括：
    在N型的半导体衬底上外延生长外延层；
    刻蚀所述外延层形成沟槽结构，所述沟槽结构包括多个第一沟槽和一个第二沟槽，所述多个第一沟槽中的每个第一沟槽沿平行于所述半导体衬底所在平面的第一方向延伸，且沿平行于所述半导体衬底所在平面的第二方向间隔排列，所述第二沟槽沿所述第二方向延伸，且所述第二沟槽与所述多个第一沟槽中的每个第一沟槽交叉设置且相互导通；
    在所述沟槽结构的底部形成第一P型半导体区，所述第一P型半导体区在垂直于所述半导体衬底所在平面的第三方向上的投影覆盖所述沟槽结构；所述第一方向、所述第二方向以及所述第三方向相互交叉设置；
    在所述沟槽结构内依次形成栅介质层和栅极；
    在所述栅极上形成覆盖所述外延层的层间介质层；
    刻蚀所述层间介质层形成沿所述第二方向延伸的接触孔，所述接触孔暴露出所述外延层的部分区域，且所述接触孔在所述第三方向上的投影与所述栅极互不交叠；
    在所述层间介质层上形成源极，所述源极通过所述接触孔与所述接触孔暴露出的所述外延层接触，且所述源极与所述第一P型半导体区导通；
    在所述半导体衬底远离所述外延层的一侧形成漏极。
  18. 如权利要求17所述的制备方法，其特征在于，所述在所述沟槽结构的底部形成第一P型半导体区，包括：
    采用垂直离子注入工艺，在所述沟槽结构的底部形成所述第一P型半导体区。
  19. 如权利要求17或18所述的制备方法，其特征在于，在N型的半导体衬底上外延生长外延层之后，所述制备方法还包括：
    采用离子注入工艺，在所述外延层的部分区域中进行离子注入，依次形成第二N型半导体区、第二P型半导体区以及源区，所述外延层中未进行离子注入的区域形成第一N型半导体区；
    所述接触孔暴露出所述源区的部分区域。
  20. 如权利要求19所述的制备方法，其特征在于，还包括：
    在所述沟槽结构内依次形成栅介质层和栅极之前，在所述沟槽结构的至少一个侧壁采用倾斜离子注入工艺，形成与所述第一P型半导体区接触的第三P型半导体区；
    采用离子注入工艺，在所述外延层中形成与所述源区同层设置的第四P型半导体区。
  21. 一种功率转换电路，其特征在于，包括电路板以及一个或多个如权利要求1-16任一项所述的半导体器件，所述半导体器件与所述电路板连接。
  22. 一种车辆，其特征在于，包括如权利要求21所述的功率转换电路，所述功率转换电路用于对交流电和/或直流电进行转换后输出直流电。
PCT/CN2022/121112 2022-09-23 2022-09-23 半导体器件、其制备方法、功率转换电路及车辆 WO2024060259A1 (zh)

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WO2022111160A1 (zh) * 2020-11-27 2022-06-02 株洲中车时代半导体有限公司 碳化硅器件的元胞结构、其制备方法及碳化硅器件

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US20100044792A1 (en) * 2008-08-20 2010-02-25 Alpha & Omega Semiconductor, Inc. Charged balanced devices with shielded gate trench
US20130001592A1 (en) * 2011-06-29 2013-01-03 Toyota Jidosha Kabushiki Kaisha Silicon carbide semiconductor device
US20180182886A1 (en) * 2016-12-28 2018-06-28 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
WO2022111160A1 (zh) * 2020-11-27 2022-06-02 株洲中车时代半导体有限公司 碳化硅器件的元胞结构、其制备方法及碳化硅器件

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