WO2024060260A1 - 半导体器件、制备方法、功率转换电路及车辆 - Google Patents

半导体器件、制备方法、功率转换电路及车辆 Download PDF

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WO2024060260A1
WO2024060260A1 PCT/CN2022/121113 CN2022121113W WO2024060260A1 WO 2024060260 A1 WO2024060260 A1 WO 2024060260A1 CN 2022121113 W CN2022121113 W CN 2022121113W WO 2024060260 A1 WO2024060260 A1 WO 2024060260A1
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type semiconductor
gate
semiconductor region
trench
epitaxial layer
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PCT/CN2022/121113
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English (en)
French (fr)
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滨田公守
胡飞
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华为数字能源技术有限公司
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Priority to CN202280008429.8A priority Critical patent/CN118140314A/zh
Priority to PCT/CN2022/121113 priority patent/WO2024060260A1/zh
Priority to EP22959262.1A priority patent/EP4407691A1/en
Publication of WO2024060260A1 publication Critical patent/WO2024060260A1/zh
Priority to US18/732,351 priority patent/US20240321950A1/en

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L15/00—Methods, circuits, or devices for controlling the traction-motor speed of electrically-propelled vehicles
    • B60L15/007—Physical arrangements or structures of drive train converters specially adapted for the propulsion motors of electric vehicles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L2210/00—Converter types
    • B60L2210/10—DC to DC converters

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to semiconductor devices, preparation methods, power conversion circuits and vehicles.
  • SiC materials have advantages over silicon (Si) materials, such as wide bandgap, high critical breakdown electric field, high thermal conductivity and high electron saturation drift velocity.
  • Metal-oxide-semiconductor field-effect transistors (MOSFETs) made of SiC materials have high breakdown voltage and low on-state voltage drop compared to insulated gate bipolar transistors (IGBTs) made of Si materials.
  • IGBTs insulated gate bipolar transistors
  • SiC MOSFETs have faster switching speeds, lower conduction losses and lower switching losses than Si IGBTs. Therefore, SiC MOSFETs have replaced Si IGBTs in some application scenarios, such as on-board microcontroller units (MCUs) and on-board battery chargers (OBCs).
  • MCUs on-board microcontroller units
  • OBCs on-board battery chargers
  • SiC MOSFET devices with trench gate structures embed the gate into the SiC body, causing the conductive channel of the device to shift from the plane direction to the vertical direction, thus significantly reducing the unit cell size of the device.
  • the size greatly increases the conductive channel density of the device, which can significantly reduce the on-resistance of the chip and improve the flow capacity.
  • the trench gate structure has become the mainstream technology direction of future devices.
  • JFET junction field effect transistor
  • the cell size of the SiC MOSFET device can be reduced and the conductive trench can be increased.
  • the channel density reduces the channel area resistance, but at the same time the flow width of the JFET area will also decrease, resulting in an increase in the JFET area resistance, which will increase the overall conduction resistance of the SiC MOSFET device and reduce the device performance. Increase chip loss.
  • the gate dielectric layer at the bottom and corners of the trench gate structure will withstand extremely high electric field intensity when the device is operating. It is a weak point for electric field breakdown and can easily cause the device to fail. Long-term operating reliability fails, so how to effectively shield the gate dielectric layer from high electric field stress has become the key to high robustness/reliability design of the device.
  • This application provides a semiconductor device, a preparation method, a power conversion circuit and a vehicle, which are used to reduce the total on-resistance of the device, improve device performance, reduce device loss and improve the robustness of device operation.
  • embodiments of the present application provide a semiconductor device, including: an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches spaced apart from each other, a gate electrode, an interlayer dielectric layer, and a source electrode. and the drain.
  • the first epitaxial layer is disposed on the semiconductor substrate, and the first epitaxial layer includes: a plurality of first P-type semiconductor regions.
  • the plurality of gate trenches extend into the first epitaxial layer along a third direction perpendicular to the plane of the semiconductor substrate (for example, the first epitaxial layer further includes: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region and source region, the first N-type semiconductor region is disposed between the second N-type semiconductor region and the semiconductor substrate, the second P-type semiconductor region is disposed on the side of the first N-type semiconductor region away from the semiconductor substrate, The source region is disposed on a side of the second P-type semiconductor region away from the semiconductor substrate, and in a third direction perpendicular to the plane of the semiconductor substrate, the gate trench extends into the first N-type semiconductor region).
  • the gate electrode includes a first gate electrode and a second gate electrode that are in contact with each other.
  • the first gate electrode is filled in the gate electrode trench through the gate dielectric layer, so that the first gate electrode is embedded inside the first epitaxial layer of SiC material.
  • the second gate electrode is disposed on the top of the first epitaxial layer of SiC material through the gate dielectric layer.
  • the first gate passes through the gate dielectric layer and together with the second P-type semiconductor region forms a trench gate structure of the SiC MOSFET device.
  • the semiconductor device provided in the embodiment of the present application is a SiC MOSFET with a trench gate structure.
  • the interlayer dielectric layer covers the side of the gate away from the semiconductor substrate, that is, the interlayer dielectric layer covers the side of the entire semiconductor substrate with the gate.
  • the source electrode is disposed on a side of the interlayer dielectric layer away from the semiconductor substrate, that is, the source electrode covers the entire interlayer dielectric layer.
  • the drain electrode is disposed on a side of the semiconductor substrate away from the first epitaxial layer, that is, the drain electrode covers the side of the semiconductor substrate where the first epitaxial layer is not disposed.
  • a contact hole extending along the second direction can be provided in the interlayer dielectric layer.
  • the orthographic projection of the contact hole on the semiconductor substrate and the orthographic projection of the gate on the semiconductor substrate can not overlap each other, that is, in the third direction, the contact hole and the gate can be arranged not to intersect with each other.
  • the contact hole exposes a part of the first epitaxial layer (for example, the contact hole exposes a part of the source region), so that the source contacts the first epitaxial layer (such as the source region) through the contact hole.
  • a plurality of first P-type semiconductor regions are provided in the first epitaxial layer, and the plurality of first P-type semiconductor regions are provided in one-to-one correspondence with the plurality of gate trenches. Moreover, the first P-type semiconductor region is disposed under the corresponding gate trench. And in this application, each first P-type semiconductor region can be connected to the source. When the SiC MOSFET device is working, the source will be loaded with voltage.
  • the voltage loaded on the source will be input into the first P-type semiconductor region, causing the first P-type semiconductor region to It also has a corresponding voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device.
  • each first P-type semiconductor region is directly in contact with the bottom of the corresponding gate trench.
  • the orthographic projection of each first P-type semiconductor region on the semiconductor substrate covers the orthographic projection of the bottom of the corresponding gate trench on the semiconductor substrate, further effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation.
  • each first P-type semiconductor region is located at the bottom end of the corresponding gate trench at the edge of the orthographic projection of the semiconductor substrate and at the periphery of the orthogonal projection edge of the semiconductor substrate, further effectively shielding the gate trench.
  • the electric field of the gate dielectric layer at the bottom improves the robustness of the device.
  • first P-type semiconductor regions corresponding to the same trench group there is a separation distance between adjacent first P-type semiconductor regions. That is to say, a plurality of first P-type semiconductor regions corresponding to the same trench group are spaced apart from each other.
  • the first P-type semiconductor region is formed at the bottom of the gate trench using a vertical ion implantation process after the gate trench is formed. Therefore, in the third direction, the first P-type semiconductor region can cover Gate trench. Moreover, due to the diffusion of ions during the ion implantation process, the first P-type semiconductor region will diffuse toward the bottom periphery of the gate trench, that is, the orthographic projection edge of the first P-type semiconductor region on the semiconductor substrate is located at the gate The pole trench is at the periphery of the orthographic projection edge on the semiconductor substrate.
  • first P-type semiconductor regions corresponding to the same trench group adjacent first P-type semiconductor regions are in contact with each other. That is to say, there is no separation distance between the plurality of first P-type semiconductor regions corresponding to the same trench group or the separation distance is 0.
  • the trench spacing in the gate trench is smaller than the ion implantation diffusion size, for example, when the trench spacing is less than 0.4um, ions will diffuse and fill the spacing area between the gate trenches, that is, multiple third A P-type semiconductor region contacts each other to form a planar region, and the shape of the planar region can be considered as a rectangle.
  • a closely arranged gate trench array is fabricated in the first epitaxial layer, and a first gate electrode is disposed in the gate trench, and in the second direction, the first gate electrode corresponds to The two sidewalls of the gate trench are the channels.
  • the extending direction of the contact hole provided in the interlayer dielectric layer is the second direction, and the extending direction of the gate trench (or first gate) is the first direction, then the extending direction of the contact hole is consistent with the extending direction of the gate trench (or the first gate electrode).
  • the extension direction of the first gate is perpendicular to each other, that is, the contact hole is placed in a direction perpendicular to the gate trench (or the first gate).
  • the gate trench and the interface hole are parallel to each other.
  • the semiconductor device provided by the embodiment of the present application reduces the restriction of the contact hole on the trench spacing of adjacent gate trenches in the second direction, and can make the gate trenches more compact, that is, the first The gates will also be tighter. Therefore, the gate trench array density of the semiconductor device provided by the embodiment of the present application can be much higher than the gate trench array density of the device structure in the prior art, thereby increasing the channel density of SiC MOSFET and significantly reducing The total on-resistance of the device improves device performance and reduces device loss.
  • the semiconductor substrate may be a silicon carbide single crystal substrate doped with pentavalent elements.
  • the first epitaxial layer may be made of SiC material grown by epitaxial growth and doped with corresponding impurities.
  • the first N-type semiconductor region is a partial region of the first epitaxial layer formed by epitaxial growth, and the second N-type semiconductor region and the source region may be formed by doping the first epitaxial layer using an ion implantation process.
  • the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).
  • the doping concentration of the semiconductor substrate is greater than the doping concentration of the second N-type semiconductor region
  • the doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region
  • the doping concentration of the source region The concentration is greater than the doping concentration of the second N-type semiconductor region.
  • the second P-type semiconductor region may be formed by doping the first epitaxial layer using an ion implantation process.
  • the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • the first gate is disposed in the gate trench, which is equivalent to the first gate extending along the first direction.
  • the second gate can be arranged to extend along the second direction, so that a part of the second gate is arranged on the first epitaxial layer through the gate dielectric layer, and the other part is arranged on the first gate, directly connected to the first gate. touch.
  • the material of the gate may be polysilicon, or other materials with good conductive properties such as metal (such as W, Al, Ti, Cu, Mo or Pt).
  • the material forming the interlayer dielectric layer may be a dielectric material, and the dielectric material includes but is not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), Silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.
  • the material used to form the source electrode and the drain electrode may be a metal material.
  • the metallic material may include W, Al, Ti, Cu, Mo, or Pt.
  • first direction, the second direction and the third direction are arranged to cross each other.
  • first direction, the second direction and the third direction are arranged perpendicularly to each other.
  • third P-type semiconductor regions are respectively provided at the first sidewall and the second sidewall of the gate trench, so that the third P-type semiconductor region is provided at the first sidewall and the second sidewall of the gate trench.
  • the second P-type semiconductor region at the sidewall (that is, the second P-type semiconductor region below the fourth P-type semiconductor region) is not controlled by the first gate and has channel performance. Therefore, in the second direction, the portion of the sidewall of the gate trench corresponding to the first gate is the channel.
  • multiple gate trenches in the semiconductor device can be divided into one or more trench groups, and two or more contact holes are provided. Furthermore, a trench group is provided between two adjacent contact holes, and the contact holes penetrate the trench group in the second direction to make the signal flow more even.
  • the number of gate trenches in different trench groups can be made the same. In this way, the gate trenches can be evenly distributed. Exemplarily, five gate trenches are provided in each trench group. It should be noted that in actual applications, the number of gate trenches in a trench group can be determined according to the needs of actual applications, and the present application does not limit this.
  • the number of gate trenches in some trench groups can also be made the same, and the number of gate trenches in the remaining trench groups can be different.
  • the number of gate trenches in different trench groups may also be different.
  • the number of gate trenches in the trench group can be determined according to the needs of the actual application, which is not limited in this application.
  • the two gate trenches at the edge in the trench group are respectively defined as the first edge trench and the second edge trench, and the contact hole is formed by the first edge trench.
  • a side of the edge groove facing away from the second edge groove extends along the second direction to a side of the second edge groove facing away from the first edge groove. That is to say, the contact holes are continuous openings, and the gate trenches in different trench groups do not penetrate through.
  • the semiconductor device provided by the embodiment of the present application is a SiC MOSFET device with a trench gate structure.
  • the bottom of the trench gate structure and the gate dielectric layer at the corners will withstand stress when the device is operating. Extremely high electric field intensity is the weak point of electric field breakdown, which can easily cause long-term device reliability failure. Therefore, how to effectively shield the gate dielectric layer from high electric field stress has become the key to high robustness/reliability design of the device.
  • a plurality of first P-type semiconductor regions are provided in the first epitaxial layer.
  • the first P-type semiconductor region is disposed below the gate trench, and the first P-type semiconductor region is in direct contact with the bottom end of the gate trench. And in this application, the first P-type semiconductor region can be connected to the source.
  • the source When the SiC MOSFET device is working, the source will be loaded with voltage. Since the first P-type semiconductor region is connected to the source, the voltage loaded on the source will be input into the first P-type semiconductor region, causing the first P-type semiconductor region to It also has a corresponding voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device.
  • This application does not limit the thickness of the first P-type semiconductor region in the third direction x.
  • the thickness of the first P-type semiconductor region in the third direction may be less than 1 ⁇ m.
  • the thickness in three directions can range from 0.3um to 0.8um.
  • the SiC MOSFET provided in the embodiment of the present application when the SiC MOSFET provided in the embodiment of the present application is applied to a power conversion circuit, its source can be connected to the ground and its drain can be connected to other components. Then the voltage of the source of the SiC MOSFET is the ground voltage (0V). Since the first P-type semiconductor region is connected to the source, the voltage of the first P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation. sex.
  • the SiC MOSFET provided in the embodiment of the present application when the SiC MOSFET provided in the embodiment of the present application is applied to a power conversion circuit, its source can also be connected to other components, and its drain can also be connected to other components. Then the voltage of the source of the SiC MOSFET is the input of other components. the voltage of the signal. Since the first P-type semiconductor region is connected to the source, the voltage of the first P-type semiconductor region is also the voltage of the input signal, which can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the device Robustness of work.
  • the first epitaxial layer further includes: a third P-type semiconductor region and a fourth P-type semiconductor region.
  • the third P-type semiconductor region is disposed at the sidewall of the gate trench along the first direction, and the fourth P-type semiconductor region and the source region are disposed in the same layer.
  • the second P-type semiconductor region, the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region may be formed by doping the first epitaxial layer using an ion implantation process.
  • the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • the doping concentration of the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region is greater than the doping concentration of the second P-type semiconductor region.
  • the doping concentrations of the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region may be the same or similar.
  • at least two of the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region may have different doping concentrations. It should be noted that the doping concentrations of the first P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region can be determined according to the requirements of the actual application environment, and are not limited here.
  • the third P-type semiconductor region corresponding to the same gate trench and the first P-type semiconductor region are in contact with each other, and the fourth P-type semiconductor region corresponding to the same gate trench is in contact with the first P-type semiconductor region.
  • the three P-type semiconductor regions are in contact, and the fourth P-type semiconductor region is in contact with the source electrode through the contact hole.
  • the source is connected to the first P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence, so that the voltage loaded on the source is input to the source through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence.
  • the first P-type semiconductor region can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation.
  • the gate trench in the first direction, has first sidewalls and second sidewalls arranged oppositely; the third P-type semiconductor region is disposed on at least one The first sidewall and/or the second sidewall of the gate trench, the third P-type semiconductor region and the first P-type semiconductor region are in contact with each other.
  • the fourth P-type semiconductor region and the source region are arranged in the same layer, and the fourth P-type semiconductor region is arranged on a side of the third P-type semiconductor region away from the gate trench, and the fourth P-type semiconductor region The P-type semiconductor region is in contact with the third P-type semiconductor region, and the fourth P-type semiconductor region is in contact with the source electrode through the contact hole.
  • the gate trench has first sidewalls and second sidewalls arranged oppositely.
  • a plurality of third P-type semiconductor regions are provided, and one of the plurality of third P-type semiconductor regions is provided on the first side wall of each gate trench, and the first side wall of each gate trench is provided with a third P-type semiconductor region.
  • the second sidewall is also provided with a third P-type semiconductor region among a plurality of third P-type semiconductor regions. That is to say, the first sidewall and the second sidewall of each gate trench are respectively provided with third P-type semiconductor regions.
  • these third P-type semiconductor regions are all in contact with the corresponding first P-type semiconductor regions, so that the third P-type semiconductor regions can be connected to the corresponding first P-type semiconductor regions for signal transmission, then the third The P-type semiconductor regions all have the same voltage as the first P-type semiconductor region.
  • a plurality of fourth P-type semiconductor regions are also provided, and the plurality of fourth P-type semiconductor regions correspond to the plurality of third P-type semiconductor regions one by one and are arranged in contact with each other.
  • each of the third P-type semiconductor regions provided on the first sidewall corresponds to a fourth P-type semiconductor region among a plurality of fourth P-type semiconductor regions, and the fourth P-type semiconductor region
  • the third P-type semiconductor region is disposed on a side of the third P-type semiconductor region away from the first sidewall of the gate trench.
  • each of the third P-type semiconductor regions provided on the second sidewall corresponds to a fourth P-type semiconductor region among a plurality of fourth P-type semiconductor regions, and the fourth P-type semiconductor region
  • the third P-type semiconductor region is disposed on a side of the third P-type semiconductor region away from the second sidewall of the gate trench.
  • the source is connected to the first P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region that are arranged corresponding to each other in sequence, so that the voltage loaded on the source electrode passes through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence.
  • the semiconductor region is input to the first P-type semiconductor region, so that the first P-type semiconductor region has a voltage, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation.
  • multiple source regions are also provided, and multiple source regions and multiple fourth P-type semiconductor regions located at the same end of the gate trench are alternately provided.
  • a plurality of source regions and a plurality of fourth P-type semiconductor regions located at the first sidewalls of the gate trenches in the same trench group are alternately arranged.
  • a plurality of source regions and a plurality of fourth P-type semiconductor regions located at the second sidewalls of the gate trenches in the same trench group are alternately arranged.
  • width of the fourth P-type semiconductor region along the second direction does not limit the width of the fourth P-type semiconductor region along the second direction.
  • the width of the fourth P-type semiconductor region along the second direction may be the same as or similar to the trench width.
  • the width of the fourth P-type semiconductor region along the second direction can also be different from the trench width, which is not limited here.
  • the orthographic projection of the first P-type semiconductor region on the semiconductor substrate also covers the third sidewall at at least one of the first sidewall and the second sidewall of the corresponding gate trench.
  • Orthographic projection of the triple P-type semiconductor region on the semiconductor substrate For example, in the third direction, the first P-type semiconductor region also covers the correspondingly arranged third P-type semiconductor region. That is to say, the orthographic projection of the first P-type semiconductor region on the semiconductor substrate not only covers the orthographic projection of the corresponding gate trench on the semiconductor substrate, but also covers the corresponding third P-type semiconductor region on the semiconductor substrate. orthographic projection.
  • the present application does not limit the specific value of the trench spacing, for example, the trench spacing is less than 1um.
  • the range of the trench spacing is 50nm to 0.5um. It should be noted that when the trench spacing is less than 100nm, the semiconductor device provided by the present application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly improve the carrier channel mobility and further reduce the total on-resistance of the device.
  • Fin FET Fin Field-Effect Transistor
  • the separation distance is smaller than the trench pitch.
  • the gate trench has a trench length. This application does not limit the trench length.
  • the trench length is greater than 5um.
  • the gate trench has a trench width. This application does not limit the width of the trench.
  • the width of the trench is less than 1um.
  • the contact holes have a contact width such that the trench spacing is no larger than the contact width.
  • the trench spacing can also be made larger than the contact width.
  • the groove spacing and contact width can be determined according to the environmental requirements of the actual application, and are not limited here.
  • width of the source region along the second direction does not limit the width of the source region along the second direction.
  • the width of the source region along the second direction can be the same as or similar to the trench pitch, which is not limited here.
  • the second P-type semiconductor region at the two sidewalls of the gate trench in the second direction of the trench gate structure forms the channel region of the SiC MOSFET. Therefore, by increasing Large trench width or reduced trench spacing can increase the conductive channel density of SiC MOSFET devices and reduce the total on-resistance of SiC MOSFET devices.
  • the SiC MOSFET device can be improved stability.
  • the semiconductor device includes: an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches spaced apart from each other, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode.
  • the first epitaxial layer includes: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, a source region, a first P-type semiconductor region, a third P-type semiconductor region and a fourth P-type semiconductor region.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • a plurality of third P-type semiconductor regions are provided, and one of the plurality of third P-type semiconductor regions is provided on the first side wall of each gate trench, and each third P-type semiconductor region is provided with a third P-type semiconductor region.
  • the third P-type semiconductor region is not provided on the second sidewall of one gate trench. That is to say, the third P-type semiconductor region is provided only at the first sidewall of each gate trench.
  • these third P-type semiconductor regions are all in contact with the corresponding first P-type semiconductor regions, so that the third P-type semiconductor regions can be connected to the corresponding first P-type semiconductor regions for signal transmission, then the third The P-type semiconductor regions all have the same voltage as the first P-type semiconductor region.
  • a plurality of fourth P-type semiconductor regions are also provided, and the plurality of fourth P-type semiconductor regions correspond to and are contacted with the plurality of third P-type semiconductor regions.
  • each of the third P-type semiconductor regions provided on the first sidewall corresponds to a fourth P-type semiconductor region in the plurality of fourth P-type semiconductor regions, and the fourth P-type semiconductor region is provided on the side of the first sidewall of the third P-type semiconductor region away from the gate trench.
  • the source is connected to the first P-type semiconductor region in sequence through the fourth P-type semiconductor region and the third P-type semiconductor region provided in correspondence with each other, so that the voltage loaded on the source is input to the first P-type semiconductor region in sequence through the fourth P-type semiconductor region and the third P-type semiconductor region, so that the first P-type semiconductor region has a voltage, thereby being able to effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation.
  • the first epitaxial layer further includes: a fifth P-type semiconductor region, the fifth P-type semiconductor region and the source region are arranged in the same layer, and the fifth P-type semiconductor region is arranged on the second sidewall of the gate trench away from the third One side of one side wall, and the fifth P-type semiconductor region is in contact with the source electrode through the contact hole.
  • the plurality of fifth P-type semiconductor regions are arranged in one-to-one correspondence with the second sidewalls of the plurality of gate trenches, that is, the second side of one gate trench.
  • the wall is arranged in one-to-one correspondence with a fifth P-type semiconductor region.
  • a plurality of source regions and a plurality of fifth P-type semiconductor regions located on the second sidewall of the gate trench are alternately arranged. That is, a plurality of source regions and a plurality of fifth P-type semiconductor regions located at the same sidewall of the gate trench are alternately arranged along the second direction.
  • the plurality of fifth P-type semiconductor regions are arranged in one-to-one correspondence with the second sidewalls of the plurality of gate trenches, that is, the second side of one gate trench.
  • the wall is arranged in one-to-one correspondence with a fifth P-type semiconductor region.
  • there are multiple source regions and the gate trenches and the multiple source regions are alternately arranged. That is, the gate trenches and the source regions are alternately arranged along the second direction.
  • the fifth P-type semiconductor region may be formed by doping the first epitaxial layer using an ion implantation process.
  • the fifth P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • P-type impurities such as boron (B), aluminum (Al) or gallium (Ga).
  • the doping concentration of the fifth P-type semiconductor region is the same as or similar to the doping concentration of the fourth P-type semiconductor region.
  • a third P-type semiconductor region is provided at the first sidewall of the gate trench, and no channel is formed.
  • the semiconductor device includes: an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches spaced apart from each other, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode.
  • the first epitaxial layer includes: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, a source region, a first P-type semiconductor region, a third P-type semiconductor region and a fourth P-type semiconductor region.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • a plurality of third P-type semiconductor regions are provided, and one of the plurality of third P-type semiconductor regions is provided on the first side wall of each gate trench, and each third P-type semiconductor region is provided with a third P-type semiconductor region.
  • the third P-type semiconductor region is not provided on the second sidewall of one gate trench. That is to say, the third P-type semiconductor region is only provided at the first sidewall of each gate trench.
  • these third P-type semiconductor regions are all in contact with the corresponding first P-type semiconductor regions, so that the third P-type semiconductor regions can be connected to the corresponding first P-type semiconductor regions for signal transmission, then the third The P-type semiconductor regions all have the same voltage as the first P-type semiconductor region.
  • a plurality of fourth P-type semiconductor regions are also provided, and the plurality of fourth P-type semiconductor regions correspond to the plurality of third P-type semiconductor regions one by one and are arranged in contact with each other.
  • each of the third P-type semiconductor regions provided on the first sidewall corresponds to a fourth P-type semiconductor region among a plurality of fourth P-type semiconductor regions, and the fourth P-type semiconductor region
  • the third P-type semiconductor region is disposed on a side of the third P-type semiconductor region away from the first sidewall of the gate trench.
  • the source electrode can be connected to the first P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region that are arranged corresponding to each other in sequence, so that the voltage loaded on the source electrode passes through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence.
  • the three P-type semiconductor regions are input to the first P-type semiconductor region, so that the first P-type semiconductor region has a voltage, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation.
  • the fourth P-type semiconductor region is provided only at the first sidewall of the gate trench, and the source regions are provided at the second sidewall of the gate trench.
  • the second P-type semiconductor region at the second sidewall of the gate trench can be controlled by the first gate to form a channel, and at the same time, a source region is provided at the second sidewall of the gate trench, so that The conduction current can be transmitted from the second P-type semiconductor region at the second sidewall of the gate trench to the drain electrode, further improving the flow path of the conduction current.
  • the semiconductor device includes: an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches spaced apart from each other, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode.
  • the first epitaxial layer includes: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, a source region, a first P-type semiconductor region, a third P-type semiconductor region and a fourth P-type semiconductor region.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the plurality of gate trenches include a first gate trench and a second gate trench that pass through in the first direction, wherein the first gate trench and the second gate trench are respectively located in the same phase.
  • Two adjacent trench groups That is, the first gate trench is located in one of the two adjacent trench groups, and the second gate trench is located in the other of the two adjacent trench groups, And the first gate trench and the second gate trench penetrate each other.
  • At least part of the gate trenches in two adjacent trench groups are connected by gate trenches arranged along the first direction.
  • the contact hole includes a plurality of sub-contact holes spaced apart from each other, and at least one through gate trench is provided between two adjacent sub-contact holes in the same contact hole.
  • This application does not limit the number of sub-contact holes into which a contact hole is divided. For example, it may be two, three, four or more.
  • the present application does not limit the number of through gate trenches provided between two adjacent sub-contact holes in the same contact hole. For example, it may be one, two, three, four or more. This can improve the design freedom of contact holes and improve the flow uniformity of SiC MOSFET devices.
  • the semiconductor device includes: an N-type semiconductor substrate, a first epitaxial layer, a second epitaxial layer, a plurality of gate trenches spaced apart from each other, a gate electrode, and an interlayer dielectric layer. source and drain.
  • the first epitaxial layer includes: a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, a source region, a first P-type semiconductor region, a third P-type semiconductor region and a fourth P-type semiconductor region. Semiconductor area. This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the second epitaxial layer is disposed between the first epitaxial layer (eg, the first N-type semiconductor region) and the semiconductor substrate. Due to the provision of the second epitaxial layer, the thickness of the first P-type semiconductor region in the third direction in the first epitaxial layer can be made thicker. For example, the thickness of the first P-type semiconductor region in the third direction can be made thicker. The thickness setting is greater than 1um.
  • the second epitaxial layer is an N-type semiconductor region.
  • the second epitaxial layer is SiC doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).
  • N nitrogen
  • P phosphorus
  • As arsenic
  • the doping concentration of the second epitaxial layer is less than the doping concentration of the first N-type semiconductor region.
  • embodiments of the present application also provide a method for manufacturing a semiconductor device, in which the preparation method may include the following steps:
  • a first epitaxial layer is epitaxially grown on the N-type semiconductor substrate.
  • the first epitaxial layer is etched to form a plurality of mutually spaced gate trenches extending into the first epitaxial layer along a third direction perpendicular to the plane of the semiconductor substrate.
  • the plurality of gate trenches extend in a first direction parallel to the plane of the semiconductor substrate
  • the plurality of gate trenches are arranged in a second direction parallel to the plane of the semiconductor substrate
  • the first direction, The second direction and the third direction are arranged to cross each other.
  • a corresponding first P-type semiconductor region is formed below each gate trench.
  • a gate dielectric layer is formed in the gate trench.
  • a first gate in the gate is formed in a gate trench formed with a gate dielectric layer, and a second gate in the gate is formed on the top of the first epitaxial layer, and the first gate and the second gate are in contact with each other.
  • An interlayer dielectric layer covering the entire first epitaxial layer is formed on the gate electrode.
  • the interlayer dielectric layer is etched to form a contact hole extending along the second direction.
  • the contact hole exposes a part of the first epitaxial layer, and the orthographic projection of the contact hole on the semiconductor substrate and the orthographic projection of the gate on the semiconductor substrate do not overlap with each other.
  • a source electrode is formed on a side of the interlayer dielectric layer away from the semiconductor substrate, and the source electrode contacts the first epitaxial layer exposed by the contact hole through the contact hole. and forming a drain electrode on a side of the semiconductor substrate away from the first epitaxial layer.
  • epitaxially growing the first epitaxial layer on the N-type semiconductor substrate may include the following steps:
  • An epitaxial process is used to epitaxially grow SiC material doped with N-type impurities on an N-type SiC semiconductor substrate to form a first epitaxial layer reaching a set thickness.
  • This application does not limit the specific value of the set thickness. In actual applications, the specific value of the set thickness can be determined according to the needs of the actual application environment.
  • the following steps may also be included: using an ion implantation process to perform ion implantation in part of the first epitaxial layer to form a third epitaxial layer.
  • the second N-type semiconductor region, the second P-type semiconductor region and the source region, and the region in the first epitaxial layer that has not been ion implanted form the first N-type semiconductor region.
  • the first N-type semiconductor region is formed in a region of the first epitaxial layer that has not been ion implanted.
  • the N-type semiconductor region may include the following steps: using an ion implantation process to dope N-type impurities on the surface of the first epitaxial layer to form a second N-type semiconductor region. After that, an ion implantation process is used to dope P-type impurities on the surface of the first epitaxial layer to form a second P-type semiconductor region.
  • an ion implantation process is used to perform N-type impurity doping on the surface of the first epitaxial layer to form a source region, and on the surface of the first epitaxial layer at the first sidewall and the second sidewall of the gate trench.
  • P-type impurities are doped to form a fourth P-type semiconductor region located in the same layer as the source region. Therefore, in the embodiment of the present application, after the ion implantation process, the second N-type semiconductor region, the second P-type semiconductor region, the source region and the fourth P-type semiconductor region are formed in part of the first epitaxial layer, and the third A first N-type semiconductor region is formed in a region of the epitaxial layer that is not ion implanted using the ion implantation process.
  • etching the first epitaxial layer to the first N-type semiconductor region and forming a plurality of gate trenches spaced apart from each other in the first epitaxial layer may include the following: Steps: First, form a trench mask on the first epitaxial layer (the trench mask can be a mask formed using photoresist or a hard mask), through which the gate trench will be formed. The area in the first epitaxial layer of the trench is covered, and the area of the first epitaxial layer where the gate trench needs to be formed is exposed.
  • the trench mask can be a mask formed using photoresist or a hard mask
  • a suitable etching process is selected from plasma etching process, ion sputtering etching process and reactive ion etching process to etch the area of the first epitaxial layer that is not covered by the trench mask. , until it is etched into the first N-type semiconductor region, and a plurality of gate trenches extending along the first direction and arranged along the second direction are formed in the first epitaxial layer.
  • an ion implantation process is used to form a corresponding first P-type semiconductor region below each gate trench, which may include the following steps: a vertical ion implantation process is used to dope P-type impurities to the bottom of the gate trench to form a first P-type semiconductor region that is consistent with the bottom pattern of the gate trench or a planar region.
  • the present application does not limit the thickness of the first P-type semiconductor region (i.e., the thickness in the third direction). In practical applications, the specific value of the thickness of the first P-type semiconductor region can be determined according to the requirements of the actual application environment.
  • a third P-type semiconductor region in contact with the first P-type semiconductor region is formed on the first sidewall and the second sidewall of each gate trench along the first direction.
  • an oblique ion implantation process is used to form the first P-type semiconductor region on the first sidewall and the second sidewall of each gate trench along the first direction.
  • the third P-type semiconductor region in contact with the semiconductor region may include the following steps: using an oblique ion implantation process, doping P-type impurities on the surfaces of the first sidewall and the second sidewall of each gate trench, respectively forming a third P-type semiconductor region in contact with the first P-type semiconductor region.
  • forming the gate dielectric layer in the gate trench may include the following steps: using an oxidation process to oxidize the entire first epitaxial layer to make the first epitaxial layer A gate dielectric layer is formed on the surface. That is, a gate dielectric layer is formed on the surface of each gate trench, and a gate dielectric layer is also formed on the side of the first epitaxial layer facing away from the semiconductor substrate.
  • a first gate electrode among the gate electrodes is formed in a gate electrode trench formed with a gate dielectric layer, and a second gate electrode among the gate electrodes is formed on top of the first epitaxial layer.
  • electrode, and making the first gate electrode and the second gate electrode contact each other may include the following steps: first, using a deposition process, deposit polysilicon material on the entire first epitaxial layer where the gate trench is formed, and make the polysilicon material The material fills the gate trench, and after filling the gate trench with polysilicon material, the entire first epitaxial layer covers the polysilicon material film layer.
  • a gate mask is formed on the first epitaxial layer (the gate mask can be a mask formed using photoresist or a hard mask), and the second gate will be formed through the gate mask. Areas are covered, leaving the rest exposed.
  • an appropriate etching process is selected from etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the polysilicon material area not covered by the trench mask is etched until the etching process is completed. The etching is stopped when the source region and the fourth P-type semiconductor region are exposed to form a first gate electrode and a second gate electrode.
  • forming an interlayer dielectric layer covering the entire first epitaxial layer on the gate may include the following steps: using a deposition process to deposit a layer on the entire first epitaxial layer The interlayer dielectric layer covers the entire first epitaxial layer.
  • etching the interlayer dielectric layer and forming a contact hole extending along the second direction may include the following steps: first, forming a contact hole mask (the The contact hole mask may be a mask formed of photoresist or a hard mask), and the contact hole mask covers the areas where the contact holes are not required to be formed, and exposes the areas where the contact holes need to be formed.
  • an appropriate etching process is selected from plasma etching process, ion sputtering etching process, reactive ion etching process and other etching processes to etch the area of the interlayer dielectric layer that is not covered by the contact hole mask. Partial regions of the source region are exposed (for example, partial regions of the source region located on both sides of the first gate in the first direction) and parts of the fourth P-type semiconductor region located on both sides of the first gate are exposed.
  • the source electrode in order to form the source electrode and the drain electrode, is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, and the source electrode is contacted with the source region through the contact hole.
  • forming the drain electrode on the side of the semiconductor substrate away from the first epitaxial layer may include the following steps: using a deposition process to deposit a metal material on the side of the interlayer dielectric layer away from the semiconductor substrate to form the source electrode.
  • the interface hole is filled with metal material, so that the source electrode contacts the source area through the metal material filled in the contact hole.
  • a deposition process may be used to deposit a metal material on the side of the semiconductor substrate away from the first epitaxial layer to form the drain electrode.
  • a deposition process may be used to deposit a metal material on the side of the semiconductor substrate away from the first epitaxial layer to form the drain electrode.
  • the material forming the source electrode and the drain electrode may be a metal material.
  • the metallic material may include W, Al, Ti, Cu, Mo, or Pt.
  • embodiments of the present application also provide a power conversion circuit, which may be an AC-DC conversion circuit and/or a DC-DC conversion circuit.
  • the power conversion circuit may include a circuit board and one or more semiconductor devices, and the semiconductor device is connected to the circuit board.
  • the semiconductor device may be a semiconductor device in the first aspect or various possible designs of the first aspect, or a semiconductor device prepared in the second aspect or various possible designs of the second aspect. Since the performance of the above-mentioned semiconductor device is better, the performance of the power conversion circuit including the above-mentioned semiconductor device is also better.
  • the principle of the power conversion circuit to solve the problem is similar to the principle of the aforementioned semiconductor device to solve the problem. Therefore, the technical effect of the power conversion circuit can be referred to the technical effect of the aforementioned semiconductor device, and the repeated parts will not be repeated.
  • embodiments of the present application further provide a vehicle, which may include a power conversion circuit.
  • the power conversion circuit may be the power conversion circuit in the third aspect or various possible designs of the third aspect. Since the performance of the above-mentioned power conversion circuit is better, the circuit performance of the vehicle including the above-mentioned power conversion circuit is also better. Moreover, the principle of solving problems of this vehicle is similar to the principle of solving problems of the aforementioned power conversion circuit. Therefore, the technical effect of this vehicle can be referred to the technical effect of the aforementioned power conversion circuit, and the repeated parts will not be repeated.
  • Figure 1 shows the relationship between the channel area resistance and JFET area resistance in SiC MOSFET devices
  • Figure 2a is a schematic structural diagram of an electric vehicle provided by an embodiment of the present application.
  • Figure 2b is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 3 is a schematic top structural view of a semiconductor device provided by an embodiment of the present application.
  • Figure 4 is a schematic cross-sectional structural diagram along the tangent direction AA' in Figure 3;
  • Figure 5 is a schematic cross-sectional structural diagram along the BB’ tangent direction in Figure 3;
  • Figure 6a is a schematic cross-sectional structural diagram along the tangential direction VV’ in Figure 3;
  • Figure 6b is another sectional structural schematic diagram along the tangential direction VV’ in Figure 3;
  • Figure 7 is a schematic diagram of the partial three-dimensional structure in Figure 3.
  • Figure 8 is a schematic three-dimensional structural diagram of the semiconductor device shown in Figure 7 when no interlayer dielectric layer and source electrode are provided;
  • Figure 9 is a schematic three-dimensional structural diagram of the gate trench in the semiconductor device shown in Figure 7;
  • FIG10 is a schematic diagram of a semiconductor device provided in an embodiment of the present application generating a conduction current
  • Figure 11 is a schematic cross-sectional structural diagram along the GG' tangent direction in Figure 10;
  • Figure 12 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figures 13a to 13i are structural schematic diagrams of a process for preparing a semiconductor device according to embodiments of the present application.
  • Figure 14 is a schematic three-dimensional structural diagram of a semiconductor device provided by another embodiment of the present application.
  • Figure 15 is a schematic three-dimensional structural diagram of the semiconductor device shown in Figure 14 when no interlayer dielectric layer and source electrode are provided;
  • Figure 16 is a schematic three-dimensional structural diagram of the gate trench in the semiconductor device shown in Figure 14;
  • Figure 17 is a schematic three-dimensional structural diagram of a semiconductor device provided by another embodiment of the present application.
  • Figure 18 is a schematic three-dimensional structural diagram of the semiconductor device shown in Figure 17 when no interlayer dielectric layer and source electrode are provided;
  • FIG19 is a schematic diagram of the three-dimensional structure of a gate trench in the semiconductor device shown in FIG17 ;
  • Figure 20 is a schematic top structural view of a semiconductor device provided by another embodiment of the present application.
  • Figure 21 is a schematic three-dimensional structural diagram of a semiconductor device provided by another embodiment of the present application.
  • FIG. 22 is another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application.
  • connection in the embodiments of this application refers to electrical connection, and the connection between two electrical components may be a direct or indirect connection between two electrical components.
  • a and B can be connected directly, or A and B can be connected indirectly through one or more other electrical components.
  • a and B can be connected, or A and C can be connected directly.
  • C and B are directly connected, and A and B are connected through C.
  • the semiconductor device provided by the embodiment of the present application can be applied in vehicles (such as electric vehicles), for example, can be used in vehicle-mounted micro-controller units (micro controller units, MCUs), vehicle-mounted battery chargers (on-board battery chargers, OBCs), etc. It should be noted that the semiconductor devices proposed in the embodiments of the present application are intended to include, but are not limited to, applications in these and any other suitable types of devices. The following description takes the vehicle as an electric vehicle as an example.
  • FIG 2a is a schematic structural diagram of an electric vehicle provided by an embodiment of the present application.
  • the electric vehicle 010 may include a power conversion circuit 011 and a battery 012.
  • the power conversion circuit 011 may include an alternating current (AC)-direct current (DC) conversion circuit and a DC-DC conversion circuit.
  • the power conversion circuit 011 may also be called an inverter. device.
  • the electric vehicle 010 when the electric vehicle is charging, the electric vehicle 010 may be connected to a three-phase power grid and receive three-phase AC power provided by the three-phase power grid.
  • the AC-DC conversion circuit can convert three-phase alternating current into direct current, and by controlling the power of the DC-DC conversion circuit in the power conversion circuit 011
  • the operation of the switching tube allows the DC-DC conversion circuit to regulate the voltage of the direct current output by the AC-DC conversion circuit, thereby providing a voltage-adapted direct current to the battery 012, so that the battery 012 can store the direct current and realize the charging function.
  • the power conversion circuit 011 may also be a DC-DC conversion circuit
  • the electric vehicle 010 may also include a load 013, which may be an on-board equipment, power system, etc. of the electric vehicle 010.
  • the power conversion circuit 011 can adjust the voltage of the DC power output by the battery and output it to the load 013, thereby providing voltage adaptation for the load 013. of direct current.
  • the semiconductor device provided by the embodiment of the present application is a MOSFET with a trench gate structure, which can increase the conduction channel density without increasing the JFET area resistance, thereby reducing the total conduction resistance, thereby improving device performance and reducing device loss.
  • the semiconductor device provided by the embodiment of the present application can be applied to the power conversion circuit 011 of the vehicle as a power switch transistor in an AC-DC converter and/or a DC-DC converter. Since the semiconductor device provided by the embodiments of the present application has better device performance, when the semiconductor device is used in an AC-DC converter and/or a DC-DC converter, the AC-DC converter and/or DC-DC converter can be improved. converter performance and reduced driving losses, thereby improving the performance of the entire circuit and reducing driving losses.
  • the semiconductor device provided by the embodiment of the present application can also be widely used in various electronic devices, for example, it can be used in electronic devices with logic devices or memory devices.
  • the electronic device may be a smartphone, a smart TV, a laptop, a personal digital assistant (PDA), a wearable device with wireless communication functions (such as a smart watch, smart glasses, a smart bracelet), etc.
  • PDA personal digital assistant
  • the semiconductor devices proposed in the embodiments of the present application are intended to include, but are not limited to, applications in these and any other suitable types of electronic equipment.
  • FIG2b is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
  • the electronic device 0100 provided in an embodiment of the present application includes a power conversion circuit 0110 and a load module 0120, and the power conversion circuit 0110 is electrically connected to the load module 0120.
  • the electronic device 0100 can be any electrical device.
  • PDA personal digital assistant
  • MCU micro control unit
  • OBC on-board battery charger
  • the power conversion circuit 0110 may be a DC-DC power conversion circuit, which is used to step up or step down the DC power and then output the DC power to power the load module 0120.
  • the power conversion circuit 0110 can convert the DC power (eg 48V) output by the power supply 0200 into DC power for all types of load modules 0120, and output it to the load module 0120 for the load module 0120 to operate. This application does not place any restrictions on the power supply 0200 and the load module 0120.
  • the power supply 0200 can be any device or component that can output direct current.
  • the power supply 0200 can be a battery (such as a battery), and the power conversion circuit 0110 can receive the battery voltage provided by the battery.
  • the load module 0120 can be any functional module that uses direct current.
  • the load module 0120 can be a processor, a chip, etc.
  • the power conversion circuit 0110 includes a DC-DC converter 0111.
  • the MOSFET in the DC-DC converter 0111 works at a certain switching frequency, so that the DC-DC converter 0111 converts the DC power of the power supply 0200 into a step-up or step-down process, and then the output is provided by the load module 0120.
  • Operating voltage DC Exemplarily, DC-DC converters are: Buck (step-down) converter, Boost (boost) converter, half-bridge converter, full-bridge converter and inductor-inductor-capacitor (inductor-inductor- capacitor, LLC) resonant converter, etc.
  • the semiconductor device provided by the embodiment of the present application is a MOSFET with a trench gate structure, which can increase the conduction channel density without increasing the JFET area resistance, thereby reducing the total conduction resistance, thereby improving device performance and reducing device loss.
  • the semiconductor device provided by the embodiment of the present application can be applied to the DC-DC converter 0111 as a MOSFET in the DC-DC converter 0111. Since the semiconductor device provided by the embodiment of the present application has better device performance, when the semiconductor device is used in the MOSFET in the DC-DC converter 0111, the performance of the DC-DC converter 0111 can be improved and the driving loss can be reduced, thereby improving performance of the entire electronic device and reduced drive losses.
  • the material of the semiconductor substrate and the first epitaxial layer is SiC.
  • the semiconductor device provided in the embodiment of this application is a SiC MOSFET.
  • the "+” marked on N or P indicates that the doping concentration is higher than the doping concentration of the layer or region not marked with +, and the more the number of "+”, the higher the doping concentration.
  • the N or P containing the same number of "+”s is expressed as a similar doping concentration and is not limited to the same doping concentration.
  • the "-" marked on N or P indicates that the doping concentration is lower than the doping concentration of the layer or region not marked with -, and the more the number of "-", the lower the doping concentration.
  • the N or P containing the same number of "-”s is expressed as a similar doping concentration and is not limited to the same doping concentration.
  • the comparison of the doping concentrations of the two regions in this application only refers to the comparison of the concentrations of the impurities doped in the two regions.
  • the lining used for doping the impurities The base is not limited, that is, the components of the impurities may be the same or different; the materials of the substrate used for doping the impurities may be the same or different.
  • Figure 3 shows a schematic top structural view of a semiconductor device provided by an embodiment of the present application.
  • Figure 4 shows a schematic cross-sectional structural view along AA' in Figure 3.
  • Figure 5 shows a schematic cross-sectional view along BB in Figure 3.
  • Figure 6a shows a schematic cross-sectional structural diagram along the tangential direction VV' in Figure 3.
  • Figure 6b shows another schematic cross-sectional structural diagram along the tangential direction VV' in Figure 3.
  • Figure 7 shows a schematic diagram of the partial three-dimensional structure in Figure 3.
  • Figure 8 shows a schematic diagram of the three-dimensional structure of the semiconductor device shown in Figure 7 when no interlayer dielectric layer and source are provided.
  • Figure 9 shows A schematic diagram of the three-dimensional structure of the gate trench in the semiconductor device shown in Figure 7 is shown.
  • the semiconductor device provided by the embodiment of the present application includes: an N-type semiconductor substrate 1 , a first epitaxial layer 100 , a plurality of gate trenches 01 spaced apart from each other, a gate electrode 11 , an interlayer Dielectric layer 12, source electrode 13 and drain electrode 14.
  • the first epitaxial layer 100 is disposed on the semiconductor substrate 1, and the first epitaxial layer 100 includes: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, a plurality of A P-type semiconductor region 8 and a source region 6, the first N-type semiconductor region 2 is provided between the second N-type semiconductor region 3 and the semiconductor substrate 1, and the second P-type semiconductor region 4 is provided in the first N-type semiconductor region 2 on the side away from the semiconductor substrate 1, and the source region 6 is disposed on the side of the second P-type semiconductor region 4 away from the semiconductor substrate 1.
  • the semiconductor substrate may be a silicon carbide single crystal substrate doped with pentavalent elements.
  • the first epitaxial layer 100 may be made of SiC material grown by epitaxial growth and doped with corresponding impurities.
  • the first N-type semiconductor region 2 is a partial region of the first epitaxial layer 100 formed by epitaxial growth.
  • the second N-type semiconductor region 3 and the source region 6 can be formed by using an ion implantation process. formed by doping.
  • the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).
  • the doping concentration of the semiconductor substrate 1 is greater than the doping concentration of the second N-type semiconductor region 3, and the doping concentration of the second N-type semiconductor region 3 is greater than the doping concentration of the first N-type semiconductor region 2.
  • Source The doping concentration of region 6 is greater than the doping concentration of second N-type semiconductor region 3 .
  • the second P-type semiconductor region 4 may be formed by doping the first epitaxial layer 100 using an ion implantation process. Moreover, the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • P-type impurities such as boron (B), aluminum (Al) or gallium (Ga).
  • a plurality of gate trenches 01 spaced apart from each other are provided in the first epitaxial layer 100 , and in the third direction z perpendicular to the plane of the semiconductor substrate 1 , the gate trenches 01 extends into the first N-type semiconductor region 2 . And the plurality of gate trenches 01 extend along a first direction x parallel to the plane where the semiconductor substrate 1 lies, and the plurality of gate trenches 01 are arranged along a second direction y parallel to the plane where the semiconductor substrate 1 lies. A closely arranged array of gate trenches 01 is fabricated in the first epitaxial layer 100 .
  • the gate 11 includes a first gate 111 and a second gate 112 that are in contact with each other.
  • the first gate 111 is filled in the gate trench 01 through the gate dielectric layer 10 so that The first gate 111 is embedded inside the first epitaxial layer 100 of SiC material.
  • the second gate 112 is also disposed on the top of the first epitaxial layer 100 of SiC material through the gate dielectric layer 10 .
  • the first gate 111 passes through the gate dielectric layer 10 and together with the second P-type semiconductor region 4 forms the trench gate structure 7 of the SiC MOSFET device. That is to say, the semiconductor device provided by the embodiment of the present application has a trench gate structure. SiC MOSFET.
  • the first gate 111 is disposed in the gate trench 01, which is equivalent to the first gate 111 extending along the first direction x.
  • the second gate 112 can be arranged to extend along the second direction y, so that a portion of the second gate 112 is disposed on the top of the first epitaxial layer 100 through the gate dielectric layer 10, and another portion is disposed on the top of the first gate 111, directly contacting the first gate 111.
  • the material of the gate electrode 11 can be polysilicon material, or other materials with good conductive properties such as metal (such as W, Al, Ti, Cu, Mo or Pt).
  • the interlayer dielectric layer 12 covers the side of the gate electrode 11 away from the semiconductor substrate 1 , that is, the interlayer dielectric layer 12 covers the entire side of the semiconductor substrate 1 having the gate electrode 11 .
  • the source electrode 13 is disposed on the side of the interlayer dielectric layer 12 away from the semiconductor substrate 1 , that is, the source electrode 13 covers the entire interlayer dielectric layer 12 .
  • the drain electrode 14 is disposed on the side of the semiconductor substrate 1 away from the first epitaxial layer 100 , that is, the drain electrode 14 covers the side of the semiconductor substrate 1 where the first epitaxial layer 100 is not disposed.
  • a contact hole 02 extending along the second direction y may be provided in the interlayer dielectric layer 12 .
  • the orthographic projection of the contact hole 02 on the semiconductor substrate 1 and the orthographic projection of the gate electrode 11 on the semiconductor substrate 1 do not overlap each other, that is, a contact is provided in the third direction. Hole 02 and gate 11 do not overlap each other.
  • the contact hole 02 exposes a part of the first epitaxial layer (for example, the contact hole 02 exposes a part of the source region 6 located on both sides of the first gate 111 in the first direction x), so that the source 13 can pass through
  • the contact hole 02 is in contact with the source region 6 to realize the connection between the source electrode 13 and the source region 6 .
  • the gate 11 controls the channel to be turned on, signals can be transmitted between the source 13 and the drain 14.
  • the material forming the interlayer dielectric layer 12 may be a dielectric material, and the dielectric material includes but is not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO). ), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.
  • the material used to form the source electrode 13 and the drain electrode 14 may be a metal material.
  • the metallic material may include W, Al, Ti, Cu, Mo, or Pt.
  • the first direction x, the second direction y, and the third direction z are arranged to cross each other.
  • the first direction x, the second direction y, and the third direction z are arranged perpendicularly to each other.
  • third P-type semiconductor regions 9 are respectively provided at the first sidewall S1 and the second sidewall S2 of the gate trench 01, and are provided on the first sidewall of the gate trench 01.
  • the second P-type semiconductor region 4 at S1 and the second sidewall S2 (that is, the second P-type semiconductor region 4 below the fourth P-type semiconductor region 5) is not controlled by the first gate 111 and has a channel. performance. Therefore, in the second direction y, the portion of the sidewall of the gate trench 01 corresponding to the first gate 111 is the channel.
  • a closely arranged gate trench array is fabricated in the first epitaxial layer, and a first gate electrode is disposed in the gate trench, and in the second direction, the first gate electrode corresponds to The two sidewalls of the gate trench are the channels.
  • the extending direction of the contact hole provided in the interlayer dielectric layer is the second direction, and the extending direction of the gate trench (or first gate) is the first direction, then the extending direction of the contact hole is consistent with the extending direction of the gate trench (or the first gate electrode).
  • the extension direction of the first gate is perpendicular to each other, that is, the contact hole is placed in a direction perpendicular to the gate trench (or the first gate).
  • the gate trench and the interface hole are parallel to each other.
  • the semiconductor device provided by the embodiment of the present application reduces the restriction of the contact hole on the trench spacing C of the adjacent gate trenches in the second direction, and can make the gate trenches more compact, that is, the third A grid will also be tighter. Therefore, the gate trench array density of the semiconductor device provided by the embodiment of the present application can be much higher than the gate trench array density of the device structure in the prior art, thereby increasing the channel density of SiC MOSFET and significantly reducing The total on-resistance of the device improves device performance and reduces device loss.
  • multiple gate trenches in the semiconductor device can be divided into one or more trench groups, and two or more contact holes are provided. Furthermore, a trench group is provided between two adjacent contact holes, and the contact hole penetrates the trench group in the second direction. This can make the signal flow more evenly.
  • a plurality of gate trenches 01 in the semiconductor device are divided into two trench groups, and the two trench groups are GK1 and GK2 respectively.
  • there are three contact holes 02 and the three contact holes 02 are respectively 021, 022, and 023.
  • a groove group GK1 is provided between contact holes 021 and 022, and a groove group GK2 is provided between contact holes 022 and 023.
  • the plurality of gate trenches 01 in the semiconductor device are divided into a trench group, such as trench group GK1.
  • two contact holes 02 are provided, for example, the two contact holes 02 are respectively 021 and 022.
  • a groove group GK1 is provided between the contact holes 021 and 022.
  • the number of gate trenches in different trench groups can be made the same. This allows the gate trenches to be evenly distributed. For example, referring to FIG. 3 , five gate trenches 01 are respectively provided in the trench groups GK1 and GK2 . It should be noted that the number of gate trenches 01 provided in the trench groups GK1 and GK2 shown in FIG. 3 is only for explanation, and is not the number of gate trenches 01 in the actually prepared semiconductor device. . In actual applications, the number of gate trenches 01 in the trench group can be determined according to the needs of the actual application, which is not limited in this application.
  • the number of gate trenches 01 in some trench groups may be the same, while the number of gate trenches 01 in the remaining trench groups may be different. Alternatively, the number of gate trenches 01 in different trench groups may also be different. In actual applications, the number of gate trenches 01 in the trench group can be determined according to the needs of the actual application, and this application does not limit this.
  • the two gate trenches at the edge in the trench group are respectively defined as the first edge trench and the second edge trench, and the contact hole is formed by the first edge trench.
  • a side of the groove facing away from the second edge groove extends along the second direction to a side of the second edge groove facing away from the first edge groove.
  • the two gate trenches 01 at the edge of the trench group GK1 are respectively defined as the first edge trench 01a and the second edge.
  • the contact hole 02 extends along the second direction y from the side of the first edge trench 01a facing away from the second edge trench 01b to the side of the second edge trench 01b facing away from the first edge trench 01a. Then the contact hole 02 penetrates the trench group, and the contact hole 02 is a continuous opening, and the gate trench 01 in different trench groups does not penetrate.
  • the semiconductor device provided by the embodiment of the present application is a SiC MOSFET device with a trench gate structure.
  • the bottom of the trench gate structure 7 and the gate dielectric layer at the corners will be exposed when the device is working. Withstanding extremely high electric field intensity, it is the weak point of electric field breakdown, which can easily cause long-term reliability failure of the device. Therefore, how to effectively shield the gate dielectric layer from high electric field stress has become the key to high robustness/reliability design of the device. .
  • a plurality of first P-type semiconductor regions 8 are provided in the first epitaxial layer 100 , and the plurality of first P-type semiconductor regions 8 and the plurality of gate trenches are 01 one-to-one corresponding settings. Moreover, the first P-type semiconductor region 8 is disposed below the corresponding gate trench 01 . And in this application, each first P-type semiconductor region 8 can be electrically connected to the source electrode 13 . When the SiC MOSFET device is operating, the source 13 will be loaded with voltage. Since the first P-type semiconductor region 8 is electrically connected to the source 13, the voltage loaded on the source 13 will be input into the first P-type semiconductor region 8. The first P-type semiconductor region 8 also has a corresponding voltage, so that the electric field of the gate dielectric layer at the bottom of the gate trench 01 can be effectively shielded, thereby improving the robustness of the device operation.
  • each first P-type semiconductor region 8 is disposed in direct contact with the bottom end of the corresponding gate trench 01 .
  • the orthographic projection of each first P-type semiconductor region 8 on the semiconductor substrate 1 covers the orthographic projection of the bottom end of the corresponding gate trench 01 on the semiconductor substrate 1 , further effectively shielding the bottom of the gate trench 01 .
  • the electric field of the gate dielectric layer improves the robustness of the device operation.
  • each first P-type semiconductor region 8 is located at the edge of the orthographic projection of the semiconductor substrate 1 and at the bottom end of the corresponding gate trench 01 in the orthographic projection of the semiconductor substrate 1 .
  • the edge periphery further effectively shields the electric field of the gate dielectric layer at the bottom of the gate trench 01, thereby improving the robustness of the device operation.
  • first P-type semiconductor regions corresponding to the same trench group there is a separation distance between adjacent first P-type semiconductor regions. That is to say, a plurality of first P-type semiconductor regions corresponding to the same trench group are spaced apart from each other.
  • a separation distance 202 between adjacent first P-type semiconductor regions 8 there is a separation distance 202 between adjacent first P-type semiconductor regions 8. It should be noted that the separation distance is greater than 0, and the specific value of the separation distance can be determined according to the needs of the actual application environment, and is not limited here.
  • the first P-type semiconductor region 8 is formed at the bottom of the gate trench 01 using a vertical ion implantation process after the gate trench 01 is formed. Therefore, in the first In three directions z, the first P-type semiconductor region 8 may cover the gate trench 01 . Moreover, due to the diffusion of ions during the ion implantation process, the first P-type semiconductor region 8 will diffuse toward the bottom periphery of the gate trench 01 , that is, the first P-type semiconductor region 8 will appear in the positive direction on the semiconductor substrate 1 . The projected edge is located at the periphery of the orthographic projected edge of the gate trench 01 on the semiconductor substrate 1 .
  • first P-type semiconductor regions corresponding to the same trench group adjacent first P-type semiconductor regions are in contact with each other. That is to say, there is no separation distance between the plurality of first P-type semiconductor regions corresponding to the same trench group or the separation distance is 0.
  • the adjacent first P-type semiconductor regions 8 are in contact with each other, then the plurality of first P-type semiconductor regions 8 corresponding to trench group GK2 A P-type semiconductor region 8 contacts each other to form a planar region.
  • the trench spacing C in the gate trench 01 is smaller than the ion implantation diffusion size, for example, when the trench spacing C is less than 0.4um, ions will diffuse and fill the spacing area between the gate trenches 01. That is, the plurality of first P-type semiconductor regions 8 are in contact with each other to form a planar region, and the shape of the planar region can be considered as a rectangle.
  • This application does not limit the thickness of the first P-type semiconductor region 8 in the third direction x.
  • the thickness of the first P-type semiconductor region 8 in the third direction may be less than 1 ⁇ m.
  • the thickness of 8 in the third direction may range from 0.3um to 0.8um.
  • the SiC MOSFET provided in the embodiment of the present application when the SiC MOSFET provided in the embodiment of the present application is applied to a power conversion circuit, its source can be connected to the ground and its drain can be connected to other components. Then the voltage of the source of the SiC MOSFET is the ground voltage (0V). Since the first P-type semiconductor region is connected to the source, the voltage of the first P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation. sex.
  • the SiC MOSFET provided in the embodiment of the present application when the SiC MOSFET provided in the embodiment of the present application is applied to a power conversion circuit, its source can also be connected to other components, and its drain can also be connected to other components. Then the voltage of the source of the SiC MOSFET is the input of other components. the voltage of the signal. Since the first P-type semiconductor region is connected to the source, the voltage of the first P-type semiconductor region is also the voltage of the input signal, which can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the device Robustness of work.
  • the first epitaxial layer 100 further includes: a third P-type semiconductor region 9 and a fourth P-type semiconductor region 5 .
  • the third P-type semiconductor region 9 is disposed at the sidewall of the gate trench 01 along the first direction, and the fourth P-type semiconductor region 5 and the source region 6 are disposed in the same layer.
  • the second P-type semiconductor region 4, the first P-type semiconductor region 8, the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 may be formed by doping the first epitaxial layer 100 using an ion implantation process. of.
  • the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga).
  • the doping concentrations of the first P-type semiconductor region 8, the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 are greater than the doping concentration of the second P-type semiconductor region 4.
  • the doping concentrations of the first P-type semiconductor region 8, the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 may be the same or similar.
  • at least two of the doping concentrations of the first P-type semiconductor region 8, the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 may be different. It should be noted that the doping concentrations of the first P-type semiconductor region 8, the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 may be determined according to the requirements of the actual application environment and are not limited here.
  • the third P-type semiconductor region 9 corresponding to the same gate trench 01 and the first P-type semiconductor region 8 are in contact with each other, and the third P-type semiconductor region 9 corresponding to the same gate trench 01 is in contact with each other.
  • the fourth P-type semiconductor region 5 is in contact with the third P-type semiconductor region 9 , and the fourth P-type semiconductor region 5 is in contact with the source electrode 13 through the contact hole 02 .
  • the source electrode 13 is connected to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 in sequence, so that the voltage loaded on the source electrode 13 passes through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 in sequence.
  • the three P-type semiconductor regions 9 are input to the first P-type semiconductor region 8, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench 01, thereby improving the robustness of the device operation.
  • the gate trench 01 has a first sidewall S1 and a second sidewall S2 that are oppositely arranged.
  • a plurality of third P-type semiconductor regions 9 are provided, and one of the plurality of third P-type semiconductor regions 9 is provided on the first side wall S1 of each gate trench 01, and each The second sidewall S2 of the gate trench 01 is also provided with a third P-type semiconductor region 9 among a plurality of third P-type semiconductor regions 9 . That is to say, the first sidewall S1 and the second sidewall S2 of each gate trench 01 are respectively provided with the third P-type semiconductor region 9 .
  • these third P-type semiconductor regions 9 are all in contact with the corresponding first P-type semiconductor regions 8, so that the third P-type semiconductor regions 9 can be connected to the corresponding first P-type semiconductor regions 8 for signal transmission. , then the third P-type semiconductor region 9 has the same voltage as the first P-type semiconductor region 8 .
  • a plurality of fourth P-type semiconductor regions 5 are also provided, and the plurality of fourth P-type semiconductor regions 5 correspond to and are provided in contact with the plurality of third P-type semiconductor regions 9.
  • each of the third P-type semiconductor regions 9 provided on the first side wall S1 corresponds to a fourth P-type semiconductor region 5 of the plurality of fourth P-type semiconductor regions 5, and the fourth P-type semiconductor region 5 is provided on the side of the first side wall S1 of the third P-type semiconductor region 9 away from the gate trench 01.
  • each of the third P-type semiconductor regions 9 provided on the second side wall S2 corresponds to a fourth P-type semiconductor region 5 of the plurality of fourth P-type semiconductor regions 5, and the fourth P-type semiconductor region 5 is provided on the side of the second side wall S2 of the third P-type semiconductor region 9 away from the gate trench 01.
  • the source 13 is connected to the first P-type semiconductor region 8 in sequence through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 that are arranged correspondingly to each other, so that the voltage loaded on the source 13 is input to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 in sequence, so that the first P-type semiconductor region 8 has a voltage, thereby being able to effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench 01, thereby improving the robustness of the device operation.
  • multiple source regions 6 are also provided, and multiple source regions and multiple source regions are located at the same end of the gate trench 01.
  • the fourth P-type semiconductor regions 5 are alternately arranged.
  • a plurality of source regions 6 and a plurality of fourth P-type semiconductor regions 5 located at the first sidewall S1 of the gate trench 01 in the same trench group are alternately arranged.
  • a plurality of source regions 6 and a plurality of fourth P-type semiconductor regions 5 located at the second sidewall S2 of the gate trench 01 in the same trench group are alternately arranged.
  • This application does not limit the width of the fourth P-type semiconductor region 5 along the second direction y.
  • the width of the fourth P-type semiconductor region 5 along the second direction y can be the same as or similar to the trench width.
  • the width of the fourth P-type semiconductor region 5 along the second direction can also be different from the trench width, which is not limited here.
  • the orthographic projection of the first P-type semiconductor region 8 on the semiconductor substrate also covers the third P-type semiconductor region at at least one of the first sidewall and the second sidewall of the corresponding gate trench.
  • 9 Orthographic projection on the semiconductor substrate For example, referring to FIGS. 3 to 9 , in the third direction z, the first P-type semiconductor region 8 also covers the correspondingly arranged third P-type semiconductor region 9 . That is to say, the orthographic projection of the first P-type semiconductor region 8 on the semiconductor substrate 1 not only covers the orthographic projection of the corresponding gate trench 01 on the semiconductor substrate 1 , but also covers the corresponding third P-type semiconductor region 9 Orthographic projection on semiconductor substrate 1 .
  • the trench spacing C is less than 1 ⁇ m.
  • the trench pitch C ranges from 50nm to 0.5um. It should be noted that when the trench spacing C is less than 100nm, the semiconductor device provided by this application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly increase the carrier channel mobility, further Reduce the total on-resistance of the device.
  • Fin FET Fin Field-Effect Transistor
  • the spacing distance 202 is smaller than the trench pitch C.
  • the gate trench 01 has a trench length D.
  • This application does not limit the trench length D.
  • the trench length D is greater than 5um.
  • the gate trench 01 has a trench width E.
  • This application does not limit the trench width E.
  • the trench width is less than 1 ⁇ m.
  • the contact hole 02 has a contact width F, so that the trench pitch C is no larger than the contact width F.
  • the trench pitch C can also be made larger than the contact width F.
  • the groove spacing C and the contact width F can be determined according to the environmental requirements of the actual application, and are not limited here.
  • This application does not limit the width of the source region 6 along the second direction.
  • the width of the source region 6 along the second direction y can be made the same as or similar to the trench pitch C, which is not limited here.
  • the trench gate structure 7 forms a SiC MOSFET in the second P-type semiconductor region 4 at the two sidewalls of the gate trench 01 in the second direction y.
  • Channel area therefore, by increasing the trench width or reducing the trench spacing C, the conductive channel density of SiC MOSFET devices can be increased and the total on-resistance of SiC MOSFET devices can be reduced.
  • Figure 10 shows some schematic diagrams when the semiconductor device provided by the embodiment of the present application generates a conduction current
  • Figure 11 shows a schematic cross-sectional structural diagram along the GG' tangent direction in Figure 10.
  • the black straight line with an arrow represents the flow direction of the on-current when the SiC MOSFET is turned on.
  • the MOSFET with the trench gate structure provided in this application can be controlled to be turned on.
  • FIG12 shows some flow charts of the method for preparing a semiconductor device provided in an embodiment of the present application.
  • the preparation method may include the following steps:
  • step S10 includes: using an epitaxial process to epitaxially grow a SiC material doped with N-type impurities on an N-type SiC semiconductor substrate 1 to form a first epitaxial layer reaching a set thickness DS0. Layer 100.
  • This application does not limit the specific value of the set thickness DS0.
  • the specific value of the set thickness DS0 can be determined according to the needs of the actual application environment.
  • S20 Use an ion implantation process to perform ion implantation in part of the first epitaxial layer to form a second N-type semiconductor region and a source region.
  • the first N-type semiconductor region is formed in a region of the first epitaxial layer that has not been ion implanted.
  • an ion implantation process is used to dope the surface of the first epitaxial layer with N-type impurities to form a second N-type semiconductor region 3. Then, an ion implantation process is used to dope the surface of the first epitaxial layer with P-type impurities to form a second P-type semiconductor region 4.
  • an ion implantation process is used to dope the surface of the first epitaxial layer 100 with N-type impurities to form a source region 6, and an ion implantation process is used to dope the surface of the first epitaxial layer 100 at the first side wall S1 and the second side wall S2 of the gate trench 01 with P-type impurities to form a fourth P-type semiconductor region 5 disposed in the same layer as the source region 6.
  • part of the first epitaxial layer 100 forms the second N-type semiconductor region 3, the second P-type semiconductor region 4, the source region 6 and the fourth P-type semiconductor.
  • Region 5 and the region of the first epitaxial layer 100 that is not ion implanted using this ion implantation process forms the first N-type semiconductor region 2.
  • a trench mask is formed on the first epitaxial layer (the trench mask can be a mask formed using photoresist or a hard mask), and the gate will be formed through the trench mask.
  • the area in the first epitaxial layer of the gate trench 01 is covered, and the area of the first epitaxial layer where the gate trench 01 needs to be formed is exposed. Afterwards, referring to FIG.
  • a suitable etching process is selected from the etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the areas of the first epitaxial layer that are not covered by the trench mask are The region is etched until the first N-type semiconductor region 2 is etched, and a plurality of gate trenches 01 extending along the first direction x and arranged along the second direction y are formed in the first epitaxial layer.
  • a vertical ion implantation process can be used to dope P-type impurities into the bottom of the gate trench 01 to form a first P-type semiconductor region consistent with the bottom pattern of the gate trench 01 or a planar region.
  • This application does not limit the thickness of the first P-type semiconductor region 8 (that is, the thickness in the third direction).
  • the specific value of the thickness of the first P-type semiconductor region 8 can be determined according to the requirements of the actual application environment.
  • an inclined ion implantation process is used to dope P-type impurities on the surfaces of the first side wall S1 and the second side wall S2 of each gate trench 01 to form third P-type semiconductor regions 9 in contact with the first P-type semiconductor region 8 .
  • an oxidation process is used to oxidize the entire first epitaxial layer, so that the gate dielectric layer 10 is formed on the surface of the first epitaxial layer. That is, the gate dielectric layer 10 is formed on the surface of each gate trench 01 , and the gate dielectric layer 10 is also formed on the side of the first epitaxial layer facing away from the semiconductor substrate 1 .
  • a deposition process is used to deposit polysilicon material on the entire first epitaxial layer where the gate trench is formed, and the polysilicon material fills the gate trench, and then the polysilicon material is used to fill the gate trench.
  • the entirety of the last first epitaxial layer covers the polysilicon material film layer.
  • a gate mask is formed on the first epitaxial layer (the gate mask can be a mask formed using photoresist or a hard mask), and the second gate will be formed through the gate mask. Areas are covered, leaving the rest exposed.
  • a suitable etching process is selected from the etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process to etch the polysilicon material area not covered by the trench mask.
  • the etching is stopped until the source region 6 and the fourth P-type semiconductor region 5 are exposed to form the first gate electrode 111 and the second gate electrode 112 .
  • S80 Form an interlayer dielectric layer covering the entire first epitaxial layer on the gate electrode.
  • a deposition process is used to deposit the interlayer dielectric layer 12 on the entire first epitaxial layer, and the interlayer dielectric layer 12 covers the entire first epitaxial layer.
  • a contact hole mask is formed on the first epitaxial layer (the contact hole mask may be a mask formed using photoresist or a hard mask), through which the contact hole mask will not require
  • the area where the contact hole 02 is formed is covered, while the area where the contact hole 02 needs to be formed is exposed.
  • a suitable etching process is selected from the etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the interlayer dielectric layer 12 is not covered by the contact hole 02 mask.
  • the region is etched to expose the portion of the source region 6 located on both sides of the first gate electrode 111 in the first direction x and the portion of the fourth P-type semiconductor region 5 located on both sides of the first gate electrode 111 .
  • the material forming the source electrode and the drain electrode may be a metal material.
  • the metallic material may include W, Al, Ti, Cu, Mo, or Pt.
  • a deposition process is used to deposit metal material on the side of the interlayer dielectric layer 12 away from the semiconductor substrate 1 to form the source electrode 13.
  • the interface hole is filled with metal material, so that the source electrode 13 contacts the source region 6 through the metal material filled in the contact hole 02 .
  • a deposition process may be used to deposit a metal material on the side of the semiconductor substrate 1 away from the first epitaxial layer to form the drain electrode 14.
  • a deposition process may be used to deposit a metal material on the side of the semiconductor substrate 1 away from the first epitaxial layer to form the drain electrode 14 .
  • FIG. 14 shows a schematic three-dimensional structural diagram of a semiconductor device provided by another embodiment of the present application.
  • FIG. 15 shows a schematic three-dimensional structural view of the semiconductor device shown in FIG. 14 when the interlayer dielectric layer and the source electrode are not provided.
  • FIG. 16 shows a schematic three-dimensional structural view of the gate trench in the semiconductor device shown in FIG. 14 .
  • the semiconductor device provided by the embodiment of the present application includes: an N-type semiconductor substrate 1 , a first epitaxial layer, and a plurality of gates spaced apart from each other. Trench 01, gate electrode 11, interlayer dielectric layer 12, source electrode 13 and drain electrode 14.
  • the first epitaxial layer includes: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, a source region 6, a first P-type semiconductor region 8, and a third P-type semiconductor region. 9 and the fourth P-type semiconductor region 5.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • a plurality of third P-type semiconductor regions 9 are provided, and the first sidewall S1 of each gate trench 01 is provided with a plurality of third P-type semiconductor regions 9
  • a third P-type semiconductor region 9 is provided, and the second sidewall S2 of each gate trench 01 is not provided with the third P-type semiconductor region 9 . That is to say, the third P-type semiconductor region 9 is provided only at the first sidewall S1 of each gate trench 01 .
  • these third P-type semiconductor regions 9 are all in contact with the corresponding first P-type semiconductor regions 8, so that the third P-type semiconductor regions 9 can be connected to the corresponding first P-type semiconductor regions 8 for signal transmission. , then the third P-type semiconductor region 9 has the same voltage as the first P-type semiconductor region 8 .
  • a plurality of fourth P-type semiconductor regions 5 are also provided, and the plurality of fourth P-type semiconductor regions 5 correspond to and are in contact with the plurality of third P-type semiconductor regions 9 mentioned above. set up.
  • each of the third P-type semiconductor regions 9 provided on the first sidewall S1 corresponds to one of the plurality of fourth P-type semiconductor regions 5
  • the fourth P-type semiconductor region 5 is disposed on a side of the third P-type semiconductor region 9 away from the first sidewall S1 of the gate trench 01 .
  • the source 13 is connected to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 which are arranged corresponding to each other in sequence, so that the voltage loaded on the source 13 passes through the fourth P-type semiconductor in sequence.
  • Region 5 and the third P-type semiconductor region 9 are input to the first P-type semiconductor region 8, so that the first P-type semiconductor region 8 has a voltage, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench 01, and thus Improve the robustness of device operation.
  • the first epitaxial layer further includes: a fifth P-type semiconductor region 15 , the fifth P-type semiconductor region 15 and the source region 6 are arranged in the same layer, and the fifth P-type semiconductor region 15 is arranged in The second sidewall S2 of the gate trench 01 is on one side away from the first sidewall S1 , and the fifth P-type semiconductor region 15 is in contact with the source electrode 13 through the contact hole 02 .
  • a plurality of fifth P-type semiconductor regions 15 there are a plurality of fifth P-type semiconductor regions 15 , and the plurality of fifth P-type semiconductor regions 15 are arranged in one-to-one correspondence with the second sidewalls of the plurality of gate trenches 01 , that is, one gate trench 01
  • the second sidewall S2 is arranged in one-to-one correspondence with a fifth P-type semiconductor region 15 .
  • a plurality of source regions 6 and a plurality of fifth P-type semiconductor regions 15 located on the second sidewall S2 of the gate trench 01 are alternately arranged. That is, the plurality of source regions 6 and the plurality of fifth P-type semiconductor regions 15 located at the same sidewall of the gate trench 01 are alternately arranged along the second direction y.
  • a plurality of source regions are provided, and the gate trenches 01 are alternately provided with a plurality of source regions 6 . That is, the gate trenches 01 and the source regions 6 are alternately arranged along the second direction y. That is, a plurality of source regions and a plurality of fifth P-type semiconductor regions 15 located on the second sidewall S2 of the gate trench 01 are alternately arranged.
  • the fifth P-type semiconductor region 15 may be formed by doping the first epitaxial layer using an ion implantation process. Furthermore, the fifth P-type semiconductor region 15 is doped mainly with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga). Exemplarily, the doping concentration of the fifth P-type semiconductor region 15 is the same as or similar to the doping concentration of the fourth P-type semiconductor region 5.
  • P-type impurities such as boron (B), aluminum (Al) or gallium (Ga).
  • the doping concentration of the fifth P-type semiconductor region 15 is the same as or similar to the doping concentration of the fourth P-type semiconductor region 5.
  • a third P-type semiconductor region 9 is provided at the first sidewall S1 of the gate trench 01, and no channel is formed.
  • steps S10 to S40 and S60 to S100 may refer to the description of the above preparation method.
  • step S50 is: using an oblique ion implantation process to form third P-type semiconductor regions in contact with the first P-type semiconductor region on the first sidewall of each gate trench along the first direction. Semiconductor area.
  • an oblique ion implantation process is used to perform P-type impurity doping on the surface of the first sidewall S1 of each gate trench 01 to form a first P-type semiconductor region in contact with the first P-type semiconductor region 8 .
  • FIG. 17 shows a schematic three-dimensional structural diagram of a semiconductor device provided by yet another embodiment of the present application.
  • FIG. 18 shows a schematic three-dimensional structural view of the semiconductor device shown in FIG. 17 when no interlayer dielectric layer and source are provided.
  • FIG. 19 shows a schematic three-dimensional structural view of the gate trench in the semiconductor device shown in FIG. 17 .
  • the semiconductor device includes: an N-type semiconductor substrate 1, a first epitaxial layer, a plurality of gate trenches 01 spaced apart from each other, a gate 11, an interlayer dielectric layer 12, a source 13 and a drain 14.
  • the first epitaxial layer includes: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, a source region 6, a first P-type semiconductor region 8, a third P-type semiconductor region 9 and a fourth P-type semiconductor region 5.
  • This embodiment is a modification of the implementation method in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • a plurality of third P-type semiconductor regions 9 are provided, and one third P-type semiconductor region 9 among the plurality of third P-type semiconductor regions 9 is provided on the first side wall S1 of each gate trench 01, and the third P-type semiconductor region 9 is not provided on the second side wall of each gate trench.
  • the third P-type semiconductor region 9 is provided only on the first side wall S1 of each gate trench 01.
  • these third P-type semiconductor regions 9 are in contact with the corresponding first P-type semiconductor regions 8, so that the third P-type semiconductor regions 9 can be connected to the corresponding first P-type semiconductor regions 8 for signal transmission, and the voltage of the third P-type semiconductor regions 9 is the same as that of the first P-type semiconductor regions 8.
  • a plurality of fourth P-type semiconductor regions 5 are also provided, and the plurality of fourth P-type semiconductor regions 5 correspond to and are in contact with the plurality of third P-type semiconductor regions 9 mentioned above. set up.
  • the third P-type semiconductor region 9 provided on the first sidewall S1 corresponds to one of the plurality of fourth P-type semiconductor regions 5
  • the fourth P-type semiconductor region 5 is provided on The third P-type semiconductor region 9 is away from the side of the first sidewall S1 of the gate trench 01 .
  • the source 13 is connected to the first P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 which are arranged corresponding to each other in sequence, so that the voltage loaded on the source 13 passes through the fourth P-type semiconductor in sequence.
  • Region 5 and the third P-type semiconductor region 9 are input to the first P-type semiconductor region 8, so that the first P-type semiconductor region 8 has a voltage, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench 01, and thus Improve the robustness of device operation.
  • the fourth P-type semiconductor region 5 is provided only at the first sidewall S1 of the gate trench 01 , and is provided at the second sidewall S2 of the gate trench 01 are all source area 6.
  • the second P-type semiconductor region 4 at the second sidewall S2 of the gate trench 01 can be controlled by the first gate 111 to form a channel, and at the same time, it is provided at the second sidewall S2 of the gate trench 01 source region 6 , the conduction current can be transmitted from the second P-type semiconductor region 4 at the second sidewall S2 of the gate trench 01 to the drain electrode 14 , further improving the flow path of the conduction current.
  • steps S10, S30-S40, S60-S100 may refer to the description of the above preparation method.
  • step S20 is: using an ion implantation process to perform ion implantation in part of the first epitaxial layer to form a second N-type semiconductor region, a second P-type semiconductor region and a source region.
  • the first epitaxial layer A first N-type semiconductor region is formed in a region where ions are not implanted.
  • an ion implantation process is used to perform N-type impurity doping on the surface of the first epitaxial layer to form the second N-type semiconductor region 3 .
  • an ion implantation process is used to dope P-type impurities on the surface of the first epitaxial layer to form the second P-type semiconductor region 4 .
  • an ion implantation process is used to perform N-type impurity doping on the surface of the first epitaxial layer to form the source region 6 , and P-type impurity doping is performed on the surface of the first epitaxial layer at the first sidewall S1 of the gate trench 01 Impurities are doped to form a fourth P-type semiconductor region 5 arranged in the same layer as the source region 6 . Therefore, in the embodiment of the present application, after the ion implantation process, part of the first epitaxial layer forms the second N-type semiconductor region 3, the second P-type semiconductor region 4, the source region 6 and the fourth P-type semiconductor region. 5.
  • the first N-type semiconductor region 2 is formed in the area of the first epitaxial layer that is not ion implanted using the ion implantation process.
  • step S50 is: using an oblique ion implantation process, forming a first sidewall S1 in contact with the first P-type semiconductor region 8 on the first sidewall S1 of each gate trench 01 along the first direction.
  • an oblique ion implantation process is used to perform P-type impurity doping on the surface of the first sidewall S1 of each gate trench 01 to form a first P-type semiconductor region in contact with the first P-type semiconductor region 8 .
  • FIG. 20 shows a schematic top structural view of a semiconductor device provided by another embodiment of the present application.
  • the semiconductor device includes: an N-type semiconductor substrate 1, a first epitaxial layer, a plurality of gate trenches 01 spaced apart from each other, a gate electrode 11, an interlayer Dielectric layer 12, source electrode 13 and drain electrode 14.
  • the first epitaxial layer includes: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, a source region 6, a first P-type semiconductor region 8, and a third P-type semiconductor region. 9 and the fourth P-type semiconductor region 5.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • some of the gate trenches 01 in two adjacent trench groups are penetrated by the gate trenches 01 arranged along the first direction x.
  • the gate trench 01c1 in the trench group GK1 and the gate trench 01c2 in the trench group GK2 are arranged along the first direction x, and the gate trench 01c1 and the gate trench 01c2 penetrate each other.
  • the gate trench 01d1 in the trench group GK1 and the gate trench 01d2 in the trench group GK2 are arranged along the first direction x, and the gate trench 01d1 and the gate trench 01d2 penetrate each other.
  • the gate trenches 01e1 in the trench group GK1 and the gate trenches 01e2 in the trench group GK2 are arranged along the first direction, and the gate trenches 01e1 and the gate trenches 01e2 penetrate each other.
  • the plurality of gate trenches include first gate trenches and second gate trenches penetrating along the first direction x, wherein the first gate trench and the second gate trench
  • the grooves are located in two adjacent groove groups. That is, the first gate trench is located in one of the two adjacent trench groups, and the second gate trench is located in the other of the two adjacent trench groups, And the first gate trench and the second gate trench penetrate each other.
  • first gate trench is located in one of the two adjacent trench groups
  • the second gate trench is located in the other of the two adjacent trench groups
  • the first gate trench and the second gate trench penetrate each other.
  • the gate trench 01c1 in the trench group GK1 may serve as the first gate trench
  • the gate trench 01c2 in the trench group GK2 may serve as the second gate trench
  • the trench group The gate trench 01c1 in GK1 and the gate trench 01c2 in the trench group GK2 penetrate each other.
  • the gate trench 01d1 in the trench group GK1 can be used as the first gate trench
  • the gate trench 01d2 in the trench group GK2 can be used as the second gate trench
  • the gate trench in the trench group GK1 Groove 01d1 and gate trench 01d2 in trench group GK2 penetrate each other.
  • the gate trench 01e1 in the trench group GK1 can be used as the first gate trench
  • the gate trench 01e2 in the trench group GK2 can be used as the second gate trench
  • the contact hole 02 includes a plurality of sub-contact holes spaced apart from each other, and at least one through gate trench 01 is provided between two adjacent sub-contact holes in the same contact hole 02 .
  • This application does not limit the number of sub-contact holes into which the contact hole 02 is divided. For example, it may be two, three, four or more.
  • this application does not limit the number of through gate trenches 01 provided between two adjacent sub-contact holes in the same contact hole 02.
  • it may be one, two, three, four or more. indivual. This can improve the design freedom of contact hole 02 and improve the flow uniformity of SiC MOSFET devices.
  • the contact hole includes sub-contact holes arranged spaced apart from each other: 02a and 02b.
  • a gate trench formed by gate trenches 01d1 and 01d2 is provided between the sub-contact holes 02a and 02b.
  • Figure 21 shows a schematic three-dimensional structural diagram of a semiconductor device provided by yet another embodiment of the present application.
  • the semiconductor device includes: an N-type semiconductor substrate 1, a first epitaxial layer, a second epitaxial layer 201, a plurality of gate trenches 01 spaced apart from each other, Gate electrode 11, interlayer dielectric layer 12, source electrode 13 and drain electrode 14.
  • the first epitaxial layer includes: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a second P-type semiconductor region 4, a source region 6, a first P-type semiconductor region 8, and a third P-type semiconductor region. 9 and the fourth P-type semiconductor region 5.
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the second epitaxial layer 201 is disposed between the first epitaxial layer (eg, the first N-type semiconductor region 2 ) and the semiconductor substrate 1 . Due to the provision of the second epitaxial layer 201, the thickness of the first P-type semiconductor region 8 in the first epitaxial layer 100 in the third direction z can be set thicker. For example, the first P-type semiconductor region 8 can be made thicker in the third direction z. 8The thickness in the third direction z is set to be greater than 1um.
  • the second epitaxial layer 201 is an N-type semiconductor region.
  • the second epitaxial layer 201 is SiC doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).
  • N nitrogen
  • P phosphorus
  • As arsenic
  • the doping concentration of the second epitaxial layer 201 is smaller than the doping concentration of the first N-type semiconductor region 2 .
  • steps S10 to S100 may refer to the description of the above preparation method.
  • step S00 is also included: epitaxially growing a second epitaxial layer on the N-type semiconductor substrate 1 .
  • an epitaxial process is used to epitaxially grow SiC material doped with N-type impurities on the N-type SiC semiconductor substrate 1 to form a second epitaxial layer.
  • Layer 201 an epitaxial process is used to epitaxially grow SiC material doped with N-type impurities on the N-type SiC semiconductor substrate 1 to form a second epitaxial layer.
  • Embodiments of the present application also provide a power conversion circuit, which may be an AC-DC conversion circuit and/or a DC-DC conversion circuit.
  • the power conversion circuit may include a circuit board and one or more semiconductor devices, and the semiconductor device is connected to the circuit board. Since the performance of the above-mentioned semiconductor device is better, the performance of the power conversion circuit including the above-mentioned semiconductor device is also better.
  • the principle of the power conversion circuit to solve the problem is similar to the principle of the aforementioned semiconductor device to solve the problem. Therefore, the technical effect of the power conversion circuit can be referred to the technical effect of the aforementioned semiconductor device, and the repeated parts will not be repeated.
  • An embodiment of the present application also provides a vehicle, which includes the power conversion circuit provided by the embodiment of the present application. Since the performance of the above-mentioned power conversion circuit is better, the circuit performance of the vehicle including the above-mentioned power conversion circuit is also better. Moreover, the principle of solving problems of this vehicle is similar to the principle of solving problems of the aforementioned power conversion circuit. Therefore, the technical effect of this vehicle can be referred to the technical effect of the aforementioned power conversion circuit, and the repeated parts will not be repeated.

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Abstract

本申请公开了半导体器件、制备方法、功率转换电路及车辆，包括：N型的半导体衬底、第一外延层、相互间隔设置的多个栅极沟槽、栅极、层间介质层、源极以及漏极。第一外延层包括多个第一P型半导体区，第一P型半导体区设置于栅极沟槽的下方；栅极沟槽设置于第一外延层中；栅极包括相互接触的第一栅极和第二栅极，第一栅极隔着栅介质层填充设置于栅极沟槽中，第二栅极设置于第一外延层顶部；层间介质层覆盖于栅极远离半导体衬底一侧，且具有沿第二方向延伸的接触孔；源极设置于层间介质层远离半导体衬底一侧，且通过接触孔与第一外延层接触；漏极设置于半导体衬底远离第一外延层的一侧，降低了器件的导通总电阻，提升了器件的鲁棒性。

Description

半导体器件、制备方法、功率转换电路及车辆 技术领域
本申请涉及半导体技术领域，尤其涉及到半导体器件、制备方法、功率转换电路及车辆。
背景技术
碳化硅(SiC)材料相对硅(Si)材料具有宽禁带、高临界击穿电场、高热导率及高电子饱和漂移速度等优势，利用SiC材料制作的金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)相比Si材料制作的绝缘栅双极型晶体管(insulated gate bipolar transistor，IGBT)具有高击穿电压、低导通压降等特性。且单极导电特性使得SiC MOSFET相比Si IGBT具有更快的开关速度、更低的导通损耗和更低的开关损耗。因此，SiC MOSFET已经在部分应用场景，诸如车载微控制单元(micro controller unit，MCU)、车载电池充电器(on-board battery charger，OBC)等领域取代Si IGBT。
相比于普通平面栅结构的器件，采用沟槽栅结构的SiC MOSFET器件通过将栅极嵌入到SiC体内，使器件的导电沟道由平面方向转向垂直方向，因而明显减小了器件的元胞尺寸、极大提高了器件的导电沟道密度，进而可以显著降低芯片的导通电阻、提升通流能力，沟槽栅结构已经成为未来器件的主流技术方向。但沟槽栅结构的SiC MOSFET器件中，沟道区电阻和结型场效应晶体管(junction field effect transistor，JFET)区电阻之间存在明显的矛盾关系。参照图1，横坐标代表元胞尺寸，纵坐标代表电阻，由图1可知，通过减小SiC MOSFET器件中的沟槽栅结构的间距，可以缩小SiC MOSFET器件的元胞尺寸，增大导电沟道密度，减小沟道区电阻，但同时JFET区通流宽度也会随之减小，导致JFET区电阻增大，从而使得SiC MOSFET器件整体的导通总电阻反而会增加，降低器件性能、增加芯片损耗。并且，在沟槽栅结构的SiC MOSFET器件中，在沟槽栅结构的底部及拐角处的栅介质层在器件工作时会承受极高的电场强度，是电场击穿的薄弱点，易造成器件长期工作可靠性失效，因而如何有效屏蔽栅介质层免受高电场应力作用成为器件高鲁棒性/可靠性设计的关键。
发明内容
本申请提供一种半导体器件、制备方法、功率转换电路及车辆，用于降低器件的导通总电阻，提升器件性能，降低器件损耗以及提升器件工作的鲁棒性。
第一方面，本申请实施例提供了一种半导体器件，包括：N型的半导体衬底、第一外延层、相互间隔设置的多个栅极沟槽、栅极、层间介质层、源极以及漏极。其中，第一外延层设置于半导体衬底上，且第一外延层包括：多个第一P型半导体区。多个栅极沟槽沿垂直于半导体衬底所在平面的第三方向上延伸至第一外延层中(如第一外延层还包括：第一N型半导体区、第二N型半导体区、第二P型半导体区以及源区，第一N型半导体区设置于第二N型半导体区与半导体衬底之间，第二P型半导体区设置于第一N型半导体区远离半导体衬底一侧，源区设置于第二P型半导体区远离半导体衬底一侧，在垂直于半导体衬底所在平面的第三方向上，栅极沟槽延伸至第一N型半导体区中)。以及多个栅极沟槽沿平行于半导体衬底所在平面的第一方向延伸，多个栅极沟槽沿平行于半导体衬底所 在平面的第二方向排列，在第一外延层中制作紧密排列的栅极沟槽阵列。栅极包括相互接触的第一栅极和第二栅极，第一栅极隔着栅介质层填充设置于栅极沟槽中，以使第一栅极嵌入在SiC材料的第一外延层内部。第二栅极隔着栅介质层设置于SiC材料的第一外延层顶部。第一栅极通过栅介质层，与第二P型半导体区一起形成SiC MOSFET器件的沟槽栅结构，也就是说，本申请实施例提供的半导体器件即为沟槽栅结构的SiC MOSFET。层间介质层覆盖于栅极远离半导体衬底一侧，即层间介质层覆盖于整个半导体衬底具有栅极的一侧上。源极设置于层间介质层远离半导体衬底一侧，即源极覆盖于整个层间介质层上。漏极设置于半导体衬底远离第一外延层的一侧，即漏极覆盖于半导体衬底未设置有第一外延层的一侧上。在实际应用中，源极与漏极之间需要传输信号，则可在层间介质层中设置沿第二方向延伸的接触孔。为了避免源极与栅极接触，可使接触孔在半导体衬底的正投影与栅极在半导体衬底的正投影互不交叠，即在第三方向上，设置接触孔与栅极互不交叠。并使接触孔暴露出第一外延层的部分区域(如接触孔暴露出源区的部分区域)，从而使源极通过接触孔与第一外延层(如源区)接触。在栅极控制沟道导通时，源极与漏极之间即可传输信号。
在本申请中，第一外延层中设置有多个第一P型半导体区，该多个第一P型半导体区与该多个栅极沟槽一一对应设置。并且，该第一P型半导体区设置于对应的栅极沟槽下方。并且本申请中，可将每一个第一P型半导体区与源极连接。在SiC MOSFET器件工作时，源极会加载电压，由于第一P型半导体区与源极连接，则源极上加载的电压会输入到第一P型半导体区中，使第一P型半导体区也具有相应的电压，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，每一个第一P型半导体区与对应的栅极沟槽的底端直接接触设置。并且，每一个第一P型半导体区在半导体衬底的正投影覆盖对应的栅极沟槽的底端在半导体衬底的正投影，进一步有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，每一个第一P型半导体区在半导体衬底的正投影的边缘位于对应的栅极沟槽的底端在半导体衬底的正投影的边缘外围，进一步有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
在一些示例中，对应同一所述沟槽组的第一P型半导体区中，相邻的所述第一P型半导体区之间具有间隔距离。也就是说，对应于同一沟槽组的多个第一P型半导体区相互间隔设置。
需要说明的是，第一P型半导体区是在栅极沟槽形成后，在栅极沟槽的底部采用垂直离子注入工艺形成的，因此，在第三方向上，第一P型半导体区可以覆盖栅极沟槽。并且，由于离子注入工艺过程中离子的扩散性，第一P型半导体区会向栅极沟槽的底部外围扩散，即呈现出第一P型半导体区在半导体衬底上的正投影边缘位于栅极沟槽在半导体衬底上的正投影边缘的外围。
在另一些示例中，对应同一所述沟槽组的第一P型半导体区中，相邻的所述第一P型半导体区相互接触。也就是说，对应于同一沟槽组的多个第一P型半导体区之间无间隔距离或间隔距离为0。
需要说明的是，栅极沟槽中的沟槽间距小于离子注入扩散尺寸时，例如在沟槽间距小于0.4um时，离子会扩散并充满栅极沟槽之间的间距区域，即多个第一P型半导体区相互 接触形成了面状区域，该面状区域的形状可认为是矩形。
本申请实施例提供的半导体器件，在第一外延层中制作紧密排列的栅极沟槽阵列，并在栅极沟槽中设置第一栅极，且在第二方向上，第一栅极对应的栅极沟槽两个侧壁的部分即为沟道。并且，层间介质层中设置的接触孔的延伸方向为第二方向，栅极沟槽(或第一栅极)的延伸方向为第一方向，则接触孔的延伸方向与栅极沟槽(或第一栅极)的延伸方向相互垂直，即将接触孔放置在垂直于栅极沟槽(或第一栅极)的方向上，进而相比现有技术中栅极沟槽与接口孔相互平行的设置方式，本申请实施例提供的半导体器件，降低了接触孔对相邻栅极沟槽在第二方向上的沟槽间距的限制，能够使栅极沟槽制备的更加紧密，即第一栅极也会更加紧密。因此，本申请实施例提供的半导体器件的栅极沟槽阵列密度，可远高于现有技术中的器件结构的栅极沟槽阵列密度，因而提高了SiC MOSFET的沟道密度，明显降低了器件的导通总电阻，提升器件性能，降低器件损耗。
在本申请中，半导体衬底可以为掺杂有五价元素的碳化硅单晶衬底。第一外延层可以采用外延生长生成的掺杂有相应杂质的SiC材料。例如，第一N型半导体区是采用外延生长形成的第一外延层的部分区域，第二N型半导体区和源区可以是采用离子注入工艺，通过对第一外延层进行掺杂形成的。并且，N型半导体区中掺杂的主要是N型杂质，例如氮(N)、磷(P)或砷(As)等。示例性地，半导体衬底的掺杂浓度大于第二N型半导体区的掺杂浓度，第二N型半导体区的掺杂浓度大于第一N型半导体区的掺杂浓度，源区的掺杂浓度大于第二N型半导体区的掺杂浓度。
在本申请中，第二P型半导体区可以是采用离子注入工艺，通过对第一外延层进行掺杂形成的。并且，P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。
示例性地，第一栅极设置于栅极沟槽中，相当于第一栅极沿第一方向延伸。第二栅极可以设置为沿第二方向延伸，则使第二栅极的一部分隔着栅介质层设置于第一外延层上，另一部分设置于第一栅极上，直接与第一栅极接触。
本申请对栅极的材料不作限定，例如，栅极的材料可以是多晶硅材料，也可以是金属(例如W、Al、Ti、Cu、Mo或Pt)等其它具有良好导电特性的材料。
本申请对形成层间介质层的材料不作限定，例如，形成层间介质层的材料可以是介电材料，该介电材料包括但不限于二氧化硅(SiO2)、氮氧化硅(SiNO)、碳氧化硅(SiCO)、氮化硅(SiNx)等。
本申请对形成源极和漏极的材料不作限定，例如，形成源极和漏极的材料可以为金属材料。示例性地，该金属材料可以包括W、Al、Ti、Cu、Mo或Pt。
本申请中，第一方向、第二方向以及第三方向相互交叉设置。例如，第一方向、第二方向以及第三方向相互垂直设置。
本申请实施例提供的半导体器件，栅极沟槽的第一侧壁和第二侧壁处分别设置了第三P型半导体区，这样使得设置于栅极沟槽的第一侧壁和第二侧壁处的第二P型半导体区(即第四P型半导体区下方的第二P型半导体区)并不会受第一栅极的控制而具备沟道的性能。因此，在第二方向上，第一栅极对应的栅极沟槽侧壁的部分即为沟道。
在本申请一些可能的实施方式中，可将半导体器件中的多个栅极沟槽划分为一个或多个沟槽组，接触孔设置为两个或多个。并且，相邻的两个接触孔之间设置一个沟槽组，且接触孔在第二方向上贯穿沟槽组，使信号流通较均匀。
在本申请一些可能的实施方式中，可以使不同沟槽组中的栅极沟槽的数量相同。这样可以将栅极沟槽进行均匀分布。示例性地，沟槽组分别设置了5个栅极沟槽。需要说明的是，在实际应用中，沟槽组中的栅极沟槽的数量，可以根据实际应用的需求进行确定，本申请对此不作限定。
在本申请一些可能的实施方式中，也可以使部分沟槽组中的栅极沟槽的数量相同，其余部分沟槽组中的栅极沟槽的数量不同。或者，也可以使不同沟槽组中的栅极沟槽的数量不同。在实际应用中，沟槽组中的栅极沟槽的数量，可以根据实际应用的需求进行确定，本申请对此不作限定。
在本申请一些可能的实施方式中，在第二方向上，将沟槽组中处于边缘的两个栅极沟槽分别定义为第一边缘沟槽和第二边缘沟槽，接触孔由第一边缘沟槽背离第二边缘沟槽的一侧沿第二方向延伸至第二边缘沟槽背离第一边缘沟槽的一侧。也就是说，接触孔是连续的开口，并且不同沟槽组中的栅极沟槽并未贯通。
本申请实施例提供的半导体器件为沟槽栅结构的SiC MOSFET器件，在沟槽栅结构的SiC MOSFET器件中，其沟槽栅结构的底部及拐角处的栅极介质层在器件工作时会承受极高的电场强度，是电场击穿的薄弱点，易造成器件长期工作可靠性失效，因而如何有效屏蔽栅极介质层免受高电场应力作用成为器件高鲁棒性/可靠性设计的关键。在本申请一些可能的实施方式中，第一外延层中设置有多个第一P型半导体区。该第一P型半导体区设置于栅极沟槽下方，且第一P型半导体区与栅极沟槽的底端直接接触设置。并且本申请中，可将第一P型半导体区与源极连接。在SiC MOSFET器件工作时，源极会加载电压，由于第一P型半导体区与源极连接，则源极上加载的电压会输入到第一P型半导体区中，使第一P型半导体区也具有相应的电压，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
本申请对第一P型半导体区在第三方向x上的厚度不作限定，例如，第一P型半导体区在第三方向上的厚度的范围可小于1um，例如，第一P型半导体区在第三方向上的厚度的范围可为0.3um～0.8um。
示例性地，本申请实施例提供的SiC MOSFET在应用到功率转换电路中时，其源极可接地，其漏极可连接其他元件，则SiC MOSFET的源极的电压为接地电压(0V)。由于第一P型半导体区与源极连接，则第一P型半导体区的电压也为接地电压，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，本申请实施例提供的SiC MOSFET在应用到功率转换电路中时，其源极也可连接其他元件，其漏极也连接其他元件，则SiC MOSFET的源极的电压为其他元件输入的信号的电压。由于第一P型半导体区与源极连接，则第一P型半导体区的电压也为该输入的信号的电压，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
在本申请一些可能的实施方式中，第一外延层还包括：第三P型半导体区和第四P型半导体区。第三P型半导体区设置于栅极沟槽沿第一方向的侧壁处，第四P型半导体区和源区同层设置。第二P型半导体区、第一P型半导体区、第三P型半导体区以及第四P型半导体区，可以是采用离子注入工艺，通过对第一外延层进行掺杂形成的。并且，P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。
示例性地，第一P型半导体区、第三P型半导体区以及第四P型半导体区的掺杂浓度 大于第二P型半导体区的掺杂浓度。可选地，第一P型半导体区、第三P型半导体区以及第四P型半导体区的掺杂浓度可相同或相似。当然，也可以使第一P型半导体区、第三P型半导体区以及第四P型半导体区的掺杂浓度至少两个不相同。需要说明的是，第一P型半导体区、第三P型半导体区以及第四P型半导体区的掺杂浓度，可以根据实际应用环境的需求进行确定，在此不作限定。
在本申请一些可能的实施方式中，对应于同一栅极沟槽的第三P型半导体区与第一P型半导体区相互接触，对应于同一栅极沟槽的第四P型半导体区与第三P型半导体区接触，第四P型半导体区通过接触孔与源极接触。源极依次通过第四P型半导体区和第三P型半导体区与第一P型半导体区连接，以使源极加载的电压依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
在本申请一些可能的实施方式中，在所述第一方向上，所述栅极沟槽具有相对设置的第一侧壁和第二侧壁；所述第三P型半导体区设置于至少一个所述栅极沟槽的第一侧壁和/或第二侧壁，以及所述第三P型半导体区与所述第一P型半导体区相互接触。所述第四P型半导体区和所述源区同层设置，且所述第四P型半导体区设置于所述第三P型半导体区远离栅极沟槽的一侧，以及所述第四P型半导体区与所述第三P型半导体区接触，所述第四P型半导体区通过所述接触孔与所述源极接触。
示例性地，在第一方向上，栅极沟槽具有相对设置的第一侧壁和第二侧壁。第三P型半导体区设置了多个，每一个栅极沟槽的第一侧壁设置了多个第三P型半导体区中的一个第三P型半导体区，并且每一个栅极沟槽的第二侧壁也设置了多个第三P型半导体区中的一个第三P型半导体区。也就是说，每一个栅极沟槽的第一侧壁和第二侧壁分别设置了第三P型半导体区。并且，这些第三P型半导体区均与对应的第一P型半导体区相互接触，从而可以使第三P型半导体区均与对应的第一P型半导体区连接，进行信号传输，则第三P型半导体区均与第一P型半导体区的电压相同。
示例性地，第四P型半导体区也设置了多个，该多个第四P型半导体区与上述多个第三P型半导体区一一对应且接触设置。其中，设置于第一侧壁的第三P型半导体区中的每一个第三P型半导体区对应设置多个第四P型半导体区中的一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离栅极沟槽的第一侧壁的一侧。以及，设置于第二侧壁的第三P型半导体区中的每一个第三P型半导体区对应设置多个第四P型半导体区中的一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离栅极沟槽的第二侧壁的一侧。源极依次通过相互对应设置的第四P型半导体区和第三P型半导体区与第一P型半导体区连接，以使源极加载的电压依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，使第一P型半导体区具有电压，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，本申请实施例提供的半导体器件中，源区也设置了多个，位于栅极沟槽同一端的多个源区和多个第四P型半导体区交替设置。例如，位于同一沟槽组中的栅极沟槽的第一侧壁处的多个源区和多个第四P型半导体区交替设置。以及，位于同一沟槽组中的栅极沟槽的第二侧壁处的多个源区和多个第四P型半导体区交替设置。
本申请对第四P型半导体区沿第二方向的宽度不作限定，例如，可以使第四P型半导体区沿第二方向的宽度与沟槽宽度相同或相似。当然，也可以使第四P型半导体区沿第二 方向的宽度与沟槽宽度不同，在此不作限定。
在本申请一些可能的实施方式中，第一P型半导体区在半导体衬底的正投影还覆盖对应的栅极沟槽的第一侧壁和第二侧壁中的至少一个侧壁处的第三P型半导体区在半导体衬底的正投影。例如，在第三方向上，第一P型半导体区还覆盖对应设置的第三P型半导体区。也就是说，第一P型半导体区在半导体衬底上的正投影不仅覆盖对应的栅极沟槽在半导体衬底上的正投影，还覆盖对应的第三P型半导体区在半导体衬底上的正投影。
在第二方向上，相邻两个栅极沟槽之间具有沟槽间距。本申请对沟槽间距的具体数值不作限定，例如，沟槽间距小于1um。可选地，沟槽间距的范围为50nm～0.5um。需要说明的是，沟槽间距小于100nm时，本申请提供的半导体器件将形成鳍式场效应晶体管(Fin Field-Effect Transistor，Fin FET)效应，可显著提高载流子沟道迁移率，进一步降低器件导通总电阻。
在本申请中，间隔距离小于沟槽间距。
在第一方向上，栅极沟槽具有沟槽长度。本申请对沟槽长度不作限定，例如，沟槽长度大于5um。
在第二方向上，栅极沟槽具有沟槽宽度。本申请对沟槽宽度不作限定，例如，沟槽宽度小于1um。
在第一方向上，接触孔具有接触宽度，可以使沟槽间距不大于接触宽度。当然，也可以使沟槽间距大于接触宽度。在实际应用中，沟槽间距与接触宽度可以根据实际应用的环境需求进行确定，在此不作限定。
本申请对源区沿第二方向的宽度不作限定，例如，可以使源区沿第二方向的宽度与沟槽间距相同或相似，在此不作限定。
本申请实施例提供的半导体器件中，沟槽栅结构在第二方向上的栅极沟槽的两个侧壁处的第二P型半导体区形成了SiC MOSFET的沟道区，因而，通过增大沟槽宽度或减小沟槽间距，可提高SiC MOSFET器件的导电沟道密度，降低SiC MOSFET器件的导通总电阻。
需要说明的是，本申请实施例中，通过在栅极沟槽的第一侧壁和第二侧壁处，设置第四P型半导体区，在源极上具有电压时，能够提升SiC MOSFET器件的稳定性。
在本申请一些可能的实施方式中，半导体器件包括：N型的半导体衬底、第一外延层、相互间隔设置的多个栅极沟槽、栅极、层间介质层、源极以及漏极。并且，第一外延层包括：第一N型半导体区、第二N型半导体区、第二P型半导体区、源区、第一P型半导体区、第三P型半导体区以及第四P型半导体区。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本实施例中，第三P型半导体区设置了多个，每一个栅极沟槽的第一侧壁设置了多个第三P型半导体区中的一个第三P型半导体区，并且每一个栅极沟槽的第二侧壁未设置第三P型半导体区。也就是说，仅在每一个栅极沟槽的第一侧壁处分别设置了第三P型半导体区。并且，这些第三P型半导体区均与对应的第一P型半导体区相互接触，从而可以使第三P型半导体区均与对应的第一P型半导体区连接，进行信号传输，则第三P型半导体区均与第一P型半导体区的电压相同。
示例性地，第四P型半导体区也设置了多个，该多个第四P型半导体区与上述多个第三P型半导体区一一对应且接触设置。其中，设置于第一侧壁的第三P型半导体区中的每一个第三P型半导体区对应设置多个第四P型半导体区中的一个第四P型半导体区，且该 第四P型半导体区设置于第三P型半导体区远离栅极沟槽的第一侧壁的一侧。源极依次通过相互对应设置的第四P型半导体区和第三P型半导体区与第一P型半导体区连接，以使源极加载的电压依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，使第一P型半导体区具有电压，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，第一外延层还包括：第五P型半导体区，第五P型半导体区和源区同层设置，第五P型半导体区设置于栅极沟槽的第二侧壁背离第一侧壁的一侧，且第五P型半导体区通过接触孔与源极接触。
示例性地，第五P型半导体区为多个，该多个第五P型半导体区与多个栅极沟槽的第二侧壁一一对应设置，即一个栅极沟槽的第二侧壁与一个第五P型半导体区一一对应设置。可选地，位于栅极沟槽的第二侧壁的多个源区和多个第五P型半导体区交替设置。即，位于栅极沟槽的同一侧壁处的多个源区和多个第五P型半导体区沿第二方向交替设置。
示例性地，第五P型半导体区为多个，该多个第五P型半导体区与多个栅极沟槽的第二侧壁一一对应设置，即一个栅极沟槽的第二侧壁与一个第五P型半导体区一一对应设置。可选地，源区为多个，且栅极沟槽与多个源区交替设置。即栅极沟槽与源区沿第二方向交替设置。
可选地，第五P型半导体区可以是采用离子注入工艺，通过对第一外延层进行掺杂形成的。并且，第五P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。示例性地，第五P型半导体区的掺杂浓度与第四P型半导体区的掺杂浓度相同或相似。
本申请实施例中，栅极沟槽的第一侧壁处设置了第三P型半导体区，不形成沟道。
在本申请一些可能的实施方式中，半导体器件包括：N型的半导体衬底、第一外延层、相互间隔设置的多个栅极沟槽、栅极、层间介质层、源极以及漏极。并且，第一外延层包括：第一N型半导体区、第二N型半导体区、第二P型半导体区、源区、第一P型半导体区、第三P型半导体区以及第四P型半导体区。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本实施例中，第三P型半导体区设置了多个，每一个栅极沟槽的第一侧壁设置了多个第三P型半导体区中的一个第三P型半导体区，并且每一个栅极沟槽的第二侧壁未设置第三P型半导体区。也就是说，仅在每一个栅极沟槽的第一侧壁处分别设置了第三P型半导体区。并且，这些第三P型半导体区均与对应的第一P型半导体区相互接触，从而可以使第三P型半导体区均与对应的第一P型半导体区连接，进行信号传输，则第三P型半导体区均与第一P型半导体区的电压相同。
示例性地，第四P型半导体区也设置了多个，该多个第四P型半导体区与上述多个第三P型半导体区一一对应且接触设置。其中，设置于第一侧壁的第三P型半导体区中的每一个第三P型半导体区对应设置多个第四P型半导体区中的一个第四P型半导体区，且该第四P型半导体区设置于第三P型半导体区远离栅极沟槽的第一侧壁的一侧。这样可以使源极依次通过相互对应设置的第四P型半导体区和第三P型半导体区与第一P型半导体区连接，以使源极加载的电压依次通过第四P型半导体区和第三P型半导体区输入到第一P型半导体区，使第一P型半导体区具有电压，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，仅在栅极沟槽的第一侧壁处设置了第四P型半导体区，而在栅极沟槽的第 二侧壁处设置的均为源区。而栅极沟槽的第二侧壁处的第二P型半导体区可以受第一栅极的控制以形成沟道，同时在栅极沟槽的第二侧壁处设置源区，这样可以使导通电流能够从栅极沟槽的第二侧壁处的第二P型半导体区传输到漏极上，进一步提高导通电流的流动路径。
在本申请一些可能的实施方式中，半导体器件包括：N型的半导体衬底、第一外延层、相互间隔设置的多个栅极沟槽、栅极、层间介质层、源极以及漏极。并且，第一外延层包括：第一N型半导体区、第二N型半导体区、第二P型半导体区、源区、第一P型半导体区、第三P型半导体区以及第四P型半导体区。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
示例性地，该多个栅极沟槽包括沿第一方向贯通的第一栅极沟槽和第二栅极沟槽，其中，第一栅极沟槽和第二栅极沟槽分别位于相邻的两个沟槽组。即第一栅极沟槽位于该相邻的两个沟槽组中的一个沟槽组中，第二栅极沟槽位于该相邻的两个沟槽组中的另一个沟槽组中，并且该第一栅极沟槽和第二栅极沟槽相互贯通。
示例性地，相邻两个沟槽组中的至少部分栅极沟槽中，沿第一方向排列的栅极沟槽贯通。
示例性地，接触孔包括多个相互间隔设置的子接触孔，同一接触孔中相邻的两个子接触孔之间设置有至少一个贯通的栅极沟槽。本申请对接触孔划分为的子接触孔的数量不作限定，例如，可以为两个、三个、四个或更多个。并且，本申请对同一接触孔中相邻的两个子接触孔之间设置的贯通的栅极沟槽的数量不作限定，例如，可以为一个、两个、三个、四个或更多个。这样可以提高接触孔的设计自由度，可提升SiC MOSFET器件的通流均匀性。
在本申请一些可能的实施方式中，半导体器件包括：N型的半导体衬底、第一外延层、第二外延层、相互间隔设置的多个栅极沟槽、栅极、层间介质层、源极以及漏极。并且，第一外延层包括：第一N型半导体区、第二N型半导体区、第二P型半导体区、源区、第一P型半导体区、第三P型半导体区以及第四P型半导体区。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本实施例中，第二外延层设置于第一外延层(例如第一N型半导体区)与半导体衬底之间。由于设置了第二外延层，则可以使第一外延层中的第一P型半导体区在第三方向上的厚度设置的较厚一些，例如，可使第一P型半导体区在第三方向上的厚度设置大于1um。
在本实施例中，第二外延层为N型半导体区。示例性地，第二外延层为掺杂有N型杂质的SiC，该N型杂质例如为氮(N)、磷(P)或砷(As)等。示例性地，第二外延层的掺杂浓度小于第一N型半导体区的掺杂浓度。
第二方面，本申请实施例还提供了半导体器件的制备方法，在该制备方法中，可以包括以下步骤：
在N型的半导体衬底上外延生长第一外延层。
刻蚀第一外延层，形成沿垂直于半导体衬底所在平面的第三方向上延伸至第一外延层中的相互间隔设置的多个栅极沟槽。其中，该多个栅极沟槽沿平行于半导体衬底所在平面的第一方向延伸，该多个栅极沟槽沿平行于半导体衬底所在平面的第二方向排列，并且，第一方向、第二方向以及第三方向相互交叉设置。
采用离子注入工艺，在每一个栅极沟槽的下方形成对应的第一P型半导体区。
在栅极沟槽中形成栅介质层。
在形成有栅介质层的栅极沟槽中形成栅极中的第一栅极，以及在第一外延层顶部形成栅极中的第二栅极，并使第一栅极和第二栅极相互接触。
在栅极上形成覆盖整个第一外延层的层间介质层。
刻蚀层间介质层，形成沿第二方向延伸的接触孔。其中，该接触孔暴露出第一外延层的部分区域，且接触孔在半导体衬底的正投影与栅极在半导体衬底的正投影互不交叠。
在层间介质层远离半导体衬底一侧形成源极，并使源极通过接触孔与该接触孔暴露出的第一外延层接触。以及在半导体衬底远离第一外延层的一侧形成漏极。
在一些可能的实施方式中，为了形成第一外延层，在N型的半导体衬底上外延生长第一外延层，可以包括如下步骤：
采用外延工艺，在N型的SiC半导体衬底上，外延生长掺杂有N型杂质的SiC材料，形成达到设定厚度的第一外延层。本申请对设定厚度的具体数值不作限定。在实际应用中，可以根据实际应用环境的需求，确定设定厚度的具体数值。
在一些可能的实施方式中，在N型的半导体衬底上外延生长第一外延层之后，还可以包括如下步骤：采用离子注入工艺，在第一外延层的部分区域中进行离子注入，形成第二N型半导体区、第二P型半导体区以及源区，第一外延层中未进行离子注入的区域形成第一N型半导体区。示例性地，为了形成第二N型半导体区、第二P型半导体区以及源区，第一外延层中未进行离子注入的区域形成第一N型半导体区。采用离子注入工艺，在第一外延层的部分区域中进行离子注入，形成第二N型半导体区、第二P型半导体区以及源区，第一外延层中未进行离子注入的区域形成第一N型半导体区，可以包括如下步骤：采用离子注入工艺，在第一外延层的表面进行N型杂质掺杂，形成第二N型半导体区。之后，采用离子注入工艺，在第一外延层的表面进行P型杂质掺杂，形成第二P型半导体区。之后，采用离子注入工艺，在第一外延层的表面进行N型杂质掺杂，形成源区，以及在栅极沟槽的第一侧壁和第二侧壁处的第一外延层的表面进行P型杂质掺杂，形成与源区同层设置的第四P型半导体区。因此，本申请实施例中，经过该离子注入工艺后，第一外延层的部分区域形成了第二N型半导体区、第二P型半导体区、源区以及第四P型半导体区，而第一外延层中未采用该离子注入工艺进行离子注入的区域，则形成了第一N型半导体区。
在一些可能的实施方式中，为了形成栅极沟槽，刻蚀第一外延层至第一N型半导体区，在第一外延层中形成相互间隔设置的多个栅极沟槽，可以包括如下步骤：首先，在第一外延层上形成沟槽掩膜(该沟槽掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该沟槽掩膜将形成栅极沟槽的第一外延层中的区域遮盖上，而将需要形成栅极沟槽的第一外延层中的区域暴露出来。之后，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对第一外延层中未被沟槽掩膜遮盖的区域进行刻蚀，直至刻蚀至第一N型半导体区中，在第一外延层中形成沿第一方向延伸且沿第二方向排列的多个栅极沟槽。
在一些可能的实施方式中，为了形成第一P型半导体区，采用离子注入工艺，在每一个栅极沟槽的下方形成对应的第一P型半导体区，可以包括如下步骤：采用垂直离子注入工艺，向栅极沟槽的底部掺杂P型杂质，形成与栅极沟槽底部图形一致或面状区域的第一P型半导体区。本申请对第一P型半导体区的厚度(即在第三方向上的厚度)不作限定。 在实际应用中，可以根据实际应用环境的需求，确定第一P型半导体区的厚度的具体数值。
在一些可能的实施方式中，在采用离子注入工艺，在每一个栅极沟槽的下方形成对应的第一P型半导体区之后，在栅极沟槽中形成栅介质层之前，还包括如下步骤：采用倾斜离子注入工艺，在每一个栅极沟槽沿第一方向上的第一侧壁和第二侧壁上，分别形成与第一P型半导体区接触的第三P型半导体区。示例性地，为了形成第三P型半导体区，采用倾斜离子注入工艺，在每一个栅极沟槽沿第一方向上的第一侧壁和第二侧壁上，分别形成与第一P型半导体区接触的第三P型半导体区，可以包括如下步骤：采用倾斜离子注入工艺，在每一个栅极沟槽的第一侧壁和第二侧壁的表面进行P型杂质掺杂，分别形成与第一P型半导体区接触的第三P型半导体区。
在一些可能的实施方式中，为了形成栅介质层，在栅极沟槽中形成栅介质层，可以包括如下步骤：采用氧化工艺，对整个第一外延层进行氧化处理，使第一外延层的表面形成栅介质层。即，每一个栅极沟槽的表面形成了栅介质层，第一外延层的背离半导体衬底的一侧也形成了栅介质层。
在一些可能的实施方式中，为了形成栅极，在形成有栅介质层的栅极沟槽中形成栅极中的第一栅极，以及在第一外延层顶部形成栅极中的第二栅极，并使第一栅极和第二栅极相互接触，可以包括如下步骤：首先，采用沉积工艺，在形成有栅极沟槽的第一外延层的整体上沉积多晶硅材料，并使该多晶硅材料填充栅极沟槽，且在采用多晶硅材料填充栅极沟槽后第一外延层的整体上覆盖多晶硅材料膜层。之后，在第一外延层上形成栅极掩膜(该栅极掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该栅极掩膜将形成第二栅极的区域遮盖上，而将其余区域暴露出来。之后，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对未被沟槽掩膜遮盖的多晶硅材料区域进行刻蚀，直至刻蚀至暴露出源区和第四P型半导体区时停止刻蚀，以形成第一栅极以及第二栅极。
在一些可能的实施方式中，为了形成层间介质层，在栅极上形成覆盖整个第一外延层的层间介质层，可以包括如下步骤：采用沉积工艺，在整个第一外延层上沉积层间介质层，并使层间介质层覆盖整个第一外延层。
在一些可能的实施方式中，为了形成接触孔，刻蚀层间介质层，形成沿第二方向延伸的接触孔，可以包括如下步骤：首先，在第一外延层上形成接触孔掩膜(该接触孔掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该接触孔掩膜将不需要形成接触孔的区域遮盖上，而将需要形成接触孔的区域暴露出来。之后，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对层间介质层未被接触孔掩膜遮盖的区域进行刻蚀，暴露出源区的部分区域(如源区在第一方向上位于第一栅极两侧的部分区域)以及暴露出第四P型半导体区位于第一栅极两侧的部分。
在一些可能的实施方式中，为了形成源极和漏极，在层间介质层远离半导体衬底一侧形成源极，并使源极通过接触孔与源区接触。以及在半导体衬底远离第一外延层的一侧形成漏极，可以包括如下步骤：采用沉积工艺，在层间介质层远离半导体衬底一侧沉积金属材料，形成源极。并通过金属材料填充接口孔，使源极通过接触孔中填充的金属材料与源区接触。示例性地，可以在形成源极时，采用沉积工艺，在半导体衬底远离第一外延层的一侧沉积金属材料，形成漏极。或者，也可以在源极之后，采用沉积工艺，在半导体衬底远离第一外延层的一侧沉积金属材料，形成漏极。
本申请对源极和漏极的材料不作限定，例如，形成源极和漏极的材料可以为金属材料。示例性地，该金属材料可以包括W、Al、Ti、Cu、Mo或Pt。
第三方面，本申请实施例还提供了一种功率转换电路，该功率转换电路可以为交流-直流转换电路和/或直流-直流转换电路。该功率转换电路可以包括：电路板和一个或多个半导体器件，并且该半导体器件与电路板连接。其中，该半导体器件可以为如第一方面或第一方面的各种可能设计中的半导体器件，或者如采用第二方面或第二方面的各种可能设计中制备的半导体器件。由于上述半导体器件的性能较好，因而，包括上述半导体器件的功率转换电路的性能也较好。以及，该功率转换电路解决问题的原理与前述半导体器件可以解决问题的原理相似，因此该功率转换电路的技术效果可以参照前述半导体器件的技术效果，重复之处不再赘述。
第四方面，本申请实施例还提供了一种车辆，该车辆可以包括功率转换电路。其中，该功率转换电路可以为如第三方面或第三方面的各种可能设计中的功率转换电路。由于上述功率转换电路的性能较好，因而，包括上述功率转换电路的车辆的电路性能也较好。以及，该车辆解决问题的原理与前述功率转换电路可以解决问题的原理相似，因此该车辆的技术效果可以参照前述功率转换电路的技术效果，重复之处不再赘述。
附图说明
图1为SiC MOSFET器件中沟道区电阻和JFET区电阻之间的关系图；
图2a为本申请一种实施例提供的电动汽车的结构示意图；
图2b为本申请一种实施例提供的电子设备的结构示意图；
图3为本申请一种实施例提供的半导体器件的俯视结构示意图；
图4为图3中沿AA’切线方向上的剖视结构示意图；
图5为图3中沿BB’切线方向上的剖视结构示意图；
图6a为图3中沿VV’切线方向上的一种剖视结构示意图；
图6b为图3中沿VV’切线方向上的另一种剖视结构示意图；
图7为图3中的局部立体结构示意图；
图8为图7所示的半导体器件中未设置层间介质层和源极时的立体结构示意图；
图9为图7所示的半导体器件中的栅极沟槽的立体结构示意图；
图10为本申请实施例提供的半导体器件产生导通电流时的一种示意图；
图11为图10中沿GG’切线方向上的剖视结构示意图；
图12为本申请实施例提供的半导体器件的制备方法的一种流程图；
图13a至图13i为本申请实施例提供的一种制备半导体器件的过程的结构示意图；
图14为本申请另一种实施例提供的半导体器件的立体结构示意图；
图15为图14所示的半导体器件中未设置层间介质层和源极时的立体结构示意图；
图16为图14所示的半导体器件中的栅极沟槽的立体结构示意图；
图17为本申请又一种实施例提供的半导体器件的立体结构示意图；
图18为图17所示的半导体器件中未设置层间介质层和源极时的立体结构示意图；
图19为图17所示的半导体器件中的栅极沟槽的立体结构示意图；
图20为本申请另一种实施例提供的半导体器件的俯视结构示意图；
图21为本申请又一种实施例提供的半导体器件的立体结构示意图；
图22为本申请实施例提供的半导体器件的制备方法的另一种流程图。
附图标记：
010-电动汽车；012-蓄电池；013-负载；0100-电子设备；0120-负载模块；0200-电源；011/0110-功率转换电路；0111-DC-DC转换器；01/01c1/01c2/01d1/01d2/01e1/01e2-栅极沟槽；02/021/022/023-接触孔；02a/02b-子接触孔；1-半导体衬底；100-第一外延层；2-第一N型半导体区；3-第二N型半导体区；4-第二P型半导体区；5-第四P型半导体区；6-源区；7-沟槽栅结构；8-第一P型半导体区；9-第三P型半导体区；10-栅介质层；11-栅极；111-第一栅极；112-第二栅极；12-层间介质层；13-源极；14-漏极；15-第五P型半导体区；201-第二外延层；202-间隔距离；01a-第一边缘沟槽；01b-第二边缘沟槽；x-第一方向；y-第二方向；z-第三方向；C-沟槽间距；D-沟槽长度；E-沟槽宽度；F-接触宽度；GK1/GK2-沟槽组；S1-第一侧壁；S2-第二侧壁；DS0-设定厚度。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。方法实施例中的具体操作方法也可以应用于装置实施例或系统实施例中。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本申请实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
需要指出的是，本申请实施例中“连接”指的是电连接，两个电学元件连接可以是两个电学元件之间的直接或间接连接。例如，A与B连接，既可以是A与B直接连接，也可以是A与B之间通过一个或多个其它电学元件间接连接，例如A与B连接，也可以是A与C直接连接，C与B直接连接，A与B之间通过C实现了连接。
并且，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本申请更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
需要说明的是，在以下描述中阐述了具体细节以便于充分理解本申请。但是本申请能够以多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广。因此本申请不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式，然而描述是以说明本申请的一般原则为目的，并非用以限定本申请的范围。
为了方便理解本申请实施例提供的半导体器件、制备方法、功率转换电路及车辆，下面首先介绍一下其应用场景。
本申请实施例提供的半导体器件可以应用在车辆(例如电动汽车)中，例如可以应用 于车载微控制单元(micro controller unit，MCU)、车载电池充电器(on-board battery charger，OBC)等。应注意的是，本申请实施例提出的半导体器件，旨在包括但不限于应用在这些和任意其它适合类型的器件中。下面以车辆为电动汽车为例进行说明。
图2a为本申请实施例提供的电动汽车的结构示意图。参照图2a，电动汽车010中可以包括功率转换电路011和蓄电池012。
在一种可能的实现方式中，该功率转换电路011可以包括交流(Alternating Current，AC)-直流(Direct Current，DC)转换电路和DC-DC转换电路，功率转换电路011也可以称为逆变器。示例性地，在电动汽车充电时，电动汽车010可以与三相电网连接，接收三相电网提供的三相交流电。通过控制功率转换电路011中的AC-DC转换电路的功率开关管工作，可使AC-DC转换电路将三相交流电转换为直流电，并且通过控制功率转换电路011中的DC-DC转换电路的功率开关管工作，可使DC-DC转换电路对AC-DC转换电路输出的直流电进行调压，从而为蓄电池012提供电压适配的直流电，进而使蓄电池012可以存储该直流电，实现充电的功能。
在另一种可能的实现方式中，功率转换电路011还可以是DC-DC转换电路，电动汽车010还可以包括负载013，该负载013可以是电动汽车010的车载设备、动力系统等等。示例性地，通过控制功率转换电路011的DC-DC转换电路的功率开关管工作，可使功率转换电路011将蓄电池输出的直流电进行调压后输出给负载013，从而为负载013提供电压适配的直流电。
本申请实施例提供的半导体器件，为沟槽栅结构的MOSFET，可以提高导通沟道密度，同时也不会提高JFET区电阻，从而使导通总电阻降低，进而提升器件性能，降低器件损耗。示例性地，本申请实施例提供的半导体器件可以应用到车辆的功率转换电路011中，作为AC-DC转换器和/或DC-DC转换器中的功率开关管。由于本申请实施例提供的半导体器件的器件性能较好，在该半导体器件应用于AC-DC转换器和/或DC-DC转换器中时，可以提高AC-DC转换器和/或DC-DC转换器的性能以及降低驱动损耗，从而提高整个电路的性能以及降低驱动损耗。
本申请实施例提供的半导体器件也可以被广泛应用在各种电子设备中，例如可以应用于具有逻辑器件或存储器件等的电子设备中。示例性地，该电子设备可以为智能手机、智能电视、笔记本电脑、掌上电脑(personal digital assistant，PDA)、具备无线通讯功能的可穿戴设备(如智能手表、智能眼镜、智能手环)等。应注意的是，本申请实施例提出的半导体器件，旨在包括但不限于应用在这些和任意其它适合类型的电子设备中。
图2b为本申请实施例提供的电子设备的结构示意图。参照图2b，本申请实施例提供的电子设备0100包括功率转换电路0110及负载模块0120，功率转换电路0110与负载模块0120电性连接。示例性地，电子设备0100可以是任何用电设备。例如，智能手机、智能电视、笔记本电脑、掌上电脑(personal digital assistant，PDA)、具备无线通讯功能的可穿戴设备(如智能手表、智能眼镜、智能手环)、车载微控制单元(micro controller unit，MCU)、车载电池充电器(on-board battery charger，OBC)等。应注意的是，本申请对电子设备的具体类型不作任何限定。
在一些实施例中，功率转换电路0110可以为DC-DC功率转换电路，用于将直流电进行升压或降压变化处理后输出直流电，以为负载模块0120供电。例如，功率转换电路0110可将电源0200输出的直流电(例如48V)变换为用于所有类型负载模块0120的直流电， 并输出至负载模块0120，以供负载模块0120工作。本申请对电源0200及负载模块0120不作任何限制，电源0200可以是任何能输出直流电的设备或元件，例如，电源0200可以是电池(例如蓄电池)，则功率转换电路0110可以接收电池提供的电池电压，并将电池电压转换为负载模块0120的工作电压后，输出给负载模块0120。负载模块0120可以是任何使用直流电的功能模块，例如负载模块0120可以是处理器、芯片等。
参照图2a，功率转换电路0110包括DC-DC转换器0111。具体工作时，DC-DC转换器0111中的MOSFET工作在一定的开关频率下，使DC-DC转换器0111将电源0200的直流电，进行升压或降压变化处理后，输出为负载模块0120提供工作电压的直流电。示例性地，DC-DC转换器例如为：Buck(降压式)转换器、Boost(升压式)转换器、半桥转换器、全桥转换器和电感-电感-电容(inductor-inductor-capacitor，LLC)谐振转换器等。
本申请实施例提供的半导体器件，为沟槽栅结构的MOSFET，可以提高导通沟道密度，同时也不会提高JFET区电阻，从而使导通总电阻降低，进而提升器件性能，降低器件损耗。示例性地，本申请实施例提供的半导体器件可以应用到DC-DC转换器0111中，作为DC-DC转换器0111中的MOSFET。由于本申请实施例提供的半导体器件的器件性能较好，在该半导体器件应用于DC-DC转换器0111中的MOSFET中时，可以提高DC-DC转换器0111的性能以及降低驱动损耗，从而提高整个电子设备的性能以及降低驱动损耗。
需要说明的是，上述场景描述仅是举例说明本申请的半导体器件的一些可实现的应用方式。本申请对本申请实施例提供的半导体器件的具体应用的场景不作限定，可以根据实际应用的需求进行确定。
在本申请提供的一些实施例中，半导体衬底和第一外延层的材料为SiC。则本申请实施例提供的半导体器件为SiC MOSFET。
需要明说的是，在本申请中，在前缀有N或P的层和区域中，分别表示电子或者空穴为多数载流子。此外，标记于N或P的“+”表示掺杂浓度比未标记+的层或区域的掺杂浓度高，且“+”的数量越多，表示掺杂浓度越高。且包含有相同数量“+”的N或P表示为相近的掺杂浓度并不限于掺杂浓度相同。以及，标记于N或P的“-”表示掺杂浓度比未标记-的层或区域的掺杂浓度低，且“-”的数量越多，表示掺杂浓度越低。包含有相同数量“-”的N或P表示为相近的掺杂浓度并不限于掺杂浓度相同。
另外还需要说明的是，本申请中两个区的掺杂浓度的比较仅是指该两个区所掺杂的杂质的浓度大小的比较，对杂质的成分，用于掺杂该杂质的衬底不作限定，即杂质的成分可以相同，也可以不相同；用于掺杂该杂质的衬底的材料可以相同，也可以不相同。
图3示出了本申请一种实施例提供的半导体器件的俯视结构示意图，图4示出了图3中沿AA’切线方向上的剖视结构示意图，图5示出了图3中沿BB’切线方向上的剖视结构示意图，图6a示出了图3中沿VV’切线方向上的一种剖视结构示意图，图6b示出了图3中沿VV’切线方向上的另一种剖视结构示意图，图7示出了图3中的局部立体结构示意图，图8示出了图7所示的半导体器件中未设置层间介质层和源极时的立体结构示意图，图9示出了图7所示的半导体器件中的栅极沟槽的立体结构示意图。
参照图3至图9，本申请实施例提供的半导体器件，包括：N型的半导体衬底1、第一外延层100、相互间隔设置的多个栅极沟槽01、栅极11、层间介质层12、源极13以及漏极14。其中，第一外延层100设置于半导体衬底1上，且第一外延层100包括：第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、多个第一P型半导体区8以 及源区6，第一N型半导体区2设置于第二N型半导体区3与半导体衬底1之间，第二P型半导体区4设置于第一N型半导体区2远离半导体衬底1一侧，源区6设置于第二P型半导体区4远离半导体衬底1一侧。
在本申请中，半导体衬底可以为掺杂有五价元素的碳化硅单晶衬底。第一外延层100可以采用外延生长生成的掺杂有相应杂质的SiC材料。例如，第一N型半导体区2是采用外延生长形成的第一外延层100的部分区域，第二N型半导体区3和源区6可以是采用离子注入工艺，通过对第一外延层100进行掺杂形成的。并且，N型半导体区中掺杂的主要是N型杂质，例如氮(N)、磷(P)或砷(As)等。示例性地，半导体衬底1的掺杂浓度大于第二N型半导体区3的掺杂浓度，第二N型半导体区3的掺杂浓度大于第一N型半导体区2的掺杂浓度，源区6的掺杂浓度大于第二N型半导体区3的掺杂浓度。
在本申请中，第二P型半导体区4可以是采用离子注入工艺，通过对第一外延层100进行掺杂形成的。并且，P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。
继续参照图3至图9，相互间隔设置的多个栅极沟槽01设置于第一外延层100中，且在垂直于半导体衬底1所在平面的第三方向z上，栅极沟槽01延伸至第一N型半导体区2中。以及多个栅极沟槽01沿平行于半导体衬底1所在平面的第一方向x延伸，多个栅极沟槽01沿平行于半导体衬底1所在平面的第二方向y排列。在第一外延层100中制作紧密排列的栅极沟槽01阵列。
继续参照图3至图9，栅极11包括相互接触的第一栅极111和第二栅极112，第一栅极111隔着栅介质层10填充设置于栅极沟槽01中，以使第一栅极111嵌入在SiC材料的第一外延层100内部。第二栅极112也隔着栅介质层10设置于SiC材料的第一外延层100顶部。第一栅极111通过栅介质层10，与第二P型半导体区4一起形成SiC MOSFET器件的沟槽栅结构7，也就是说，本申请实施例提供的半导体器件即为沟槽栅结构的SiC MOSFET。
示例性地，第一栅极111设置于栅极沟槽01中，相当于第一栅极111沿第一方向x延伸。第二栅极112可以设置为沿第二方向y延伸，则使第二栅极112的一部分隔着栅介质层10设置于第一外延层100顶部，另一部分设置于第一栅极111顶部，直接与第一栅极111接触。
本申请对栅极11的材料不作限定，例如，栅极11的材料可以是多晶硅材料，也可以是金属(例如W、Al、Ti、Cu、Mo或Pt)等其它具有良好导电特性的材料。
继续参照图3至图9，层间介质层12覆盖于栅极11远离半导体衬底1一侧，即层间介质层12覆盖于整个半导体衬底1具有栅极11的一侧上。源极13设置于层间介质层12远离半导体衬底1一侧，即源极13覆盖于整个层间介质层12上。漏极14设置于半导体衬底1远离第一外延层100的一侧，即漏极14覆盖于半导体衬底1未设置有第一外延层100的一侧上。在实际应用中，源极13与漏极14之间需要传输信号，则可在层间介质层12中设置沿第二方向y延伸的接触孔02。为了避免源极13与栅极11接触，可使在接触孔02在半导体衬底1的正投影与栅极11在半导体衬底1的正投影互不交叠，即在第三方向上，设置接触孔02与栅极11互不交叠。并使接触孔02暴露出第一外延层的部分区域(如接触孔02暴露出源区6在第一方向x上位于第一栅极111两侧的部分区域)，从而使源极13能够通过接触孔02与源区6接触，实现源极13与源区6连接的效果。在栅极11控制 沟道导通时，源极13与漏极14之间即可传输信号。
本申请对形成层间介质层12的材料不作限定，例如，形成层间介质层12的材料可以是介电材料，该介电材料包括但不限于二氧化硅(SiO2)、氮氧化硅(SiNO)、碳氧化硅(SiCO)、氮化硅(SiNx)等。
本申请对形成源极13和漏极14的材料不作限定，例如，形成源极13和漏极14的材料可以为金属材料。示例性地，该金属材料可以包括W、Al、Ti、Cu、Mo或Pt。
继续参照图3至图9，第一方向x、第二方向y以及第三方向z相互交叉设置。例如，第一方向x、第二方向y以及第三方向z相互垂直设置。
本申请实施例提供的半导体器件，栅极沟槽01的第一侧壁S1和第二侧壁S2处分别设置了第三P型半导体区9，设置于栅极沟槽01的第一侧壁S1和第二侧壁S2处的第二P型半导体区4(即第四P型半导体区5下方的第二P型半导体区4)并不会受第一栅极111的控制而具备沟道的性能。因此，在第二方向y上，第一栅极111对应的栅极沟槽01侧壁的部分即为沟道。
本申请实施例提供的半导体器件，在第一外延层中制作紧密排列的栅极沟槽阵列，并在栅极沟槽中设置第一栅极，且在第二方向上，第一栅极对应的栅极沟槽两个侧壁的部分即为沟道。并且，层间介质层中设置的接触孔的延伸方向为第二方向，栅极沟槽(或第一栅极)的延伸方向为第一方向，则接触孔的延伸方向与栅极沟槽(或第一栅极)的延伸方向相互垂直，即将接触孔放置在垂直于栅极沟槽(或第一栅极)的方向上，进而相比现有技术中栅极沟槽与接口孔相互平行的设置方式，本申请实施例提供的半导体器件，降低了接触孔对相邻栅极沟槽在第二方向上的沟槽间距C的限制，能够使栅极沟槽制备的更加紧密，即第一栅极也会更加紧密。因此，本申请实施例提供的半导体器件的栅极沟槽阵列密度，可远高于现有技术中的器件结构的栅极沟槽阵列密度，因而提高了SiC MOSFET的沟道密度，明显降低了器件的导通总电阻，提升器件性能，降低器件损耗。
在本申请一些实施例中，可将半导体器件中的多个栅极沟槽划分为一个或多个沟槽组，接触孔设置为两个或多个。并且，相邻的两个接触孔之间设置一个沟槽组，且接触孔在第二方向上贯穿沟槽组。这样可以使信号流通较均匀。示例性地，参照图3至图5，半导体器件中的多个栅极沟槽01划分为两个沟槽组，这两个沟槽组分别为GK1和GK2。并且，接触孔02设置为三个，这三个接触孔02分别为021、022、023。接触孔021和022之间设置有沟槽组GK1，接触孔022和023之间设置有沟槽组GK2。或者，半导体器件中的多个栅极沟槽01划分为一个沟槽组，例如沟槽组GK1。并且，接触孔02设置为两个，例如这两个接触孔02分别为021、022。接触孔021和022之间设置有沟槽组GK1。
在本申请一些实施例中，可以使不同沟槽组中的栅极沟槽的数量相同。这样可以将栅极沟槽进行均匀分布。示例性地，参照图3，沟槽组GK1和GK2中分别设置了5个栅极沟槽01。需要说明的是，图3示出的沟槽组GK1和GK2中设置的栅极沟槽01的数量仅是为了进行解释说明，并不是实际制备出的半导体器件中的栅极沟槽01的数量。在实际应用中，沟槽组中的栅极沟槽01的数量，可以根据实际应用的需求进行确定，本申请对此不作限定。
在本申请一些实施例中，也可以使部分沟槽组中的栅极沟槽01的数量相同，其余部分沟槽组中的栅极沟槽01的数量不同。或者，也可以使不同沟槽组中的栅极沟槽01的数量不同。在实际应用中，沟槽组中的栅极沟槽01的数量，可以根据实际应用的需求进行 确定，本申请对此不作限定。
在本申请一些实施例中，在第二方向上，将沟槽组中处于边缘的两个栅极沟槽分别定义为第一边缘沟槽和第二边缘沟槽，接触孔由第一边缘沟槽背离第二边缘沟槽的一侧沿第二方向延伸至第二边缘沟槽背离第一边缘沟槽的一侧。示例性地，参照图5，以沟槽组GK1为例，在第二方向上，将沟槽组GK1处于边缘的两个栅极沟槽01分别定义为第一边缘沟槽01a和第二边缘沟槽01b，则接触孔02由第一边缘沟槽01a背离第二边缘沟槽01b的一侧沿第二方向y延伸至第二边缘沟槽01b背离第一边缘沟槽01a的一侧。则接触孔02贯穿沟槽组，并且，接触孔02是连续的开口，并且不同沟槽组中的栅极沟槽01并未贯通。
本申请实施例提供的半导体器件为沟槽栅结构的SiC MOSFET器件，在沟槽栅结构的SiC MOSFET器件中，其沟槽栅结构7的底部及拐角处的栅极介质层在器件工作时会承受极高的电场强度，是电场击穿的薄弱点，易造成器件长期工作可靠性失效，因而如何有效屏蔽栅极介质层免受高电场应力作用成为器件高鲁棒性/可靠性设计的关键。在本申请实施例中，参照图3至图9，第一外延层100中设置有多个第一P型半导体区8，该多个第一P型半导体区8与该多个栅极沟槽01一一对应设置。并且，该第一P型半导体区8设置于对应的栅极沟槽01下方。并且本申请中，可将每一个第一P型半导体区8与源极13导通。在SiC MOSFET器件工作时，源极13会加载电压，由于第一P型半导体区8与源极13导通连接，则源极13上加载的电压会输入到第一P型半导体区8中，使第一P型半导体区8也具有相应的电压，从而能够有效屏蔽栅极沟槽01的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，参见图3至图9，每一个第一P型半导体区8与对应的栅极沟槽01的底端直接接触设置。并且，每一个第一P型半导体区8在半导体衬底1的正投影覆盖对应的栅极沟槽01的底端在半导体衬底1的正投影，进一步有效屏蔽栅极沟槽01的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，参见图3至图9，每一个第一P型半导体区8在半导体衬底1的正投影的边缘位于对应的栅极沟槽01的底端在半导体衬底1的正投影的边缘外围，进一步有效屏蔽栅极沟槽01的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
在一些示例中，对应同一所述沟槽组的第一P型半导体区中，相邻的所述第一P型半导体区之间具有间隔距离。也就是说，对应于同一沟槽组的多个第一P型半导体区相互间隔设置。示例性地，参见图6a，以沟槽组GK2为例，在沟槽组GK2中，相邻的所述第一P型半导体区8之间具有间隔距离202。需要说明的是，该间隔距离大于0，并且，该间隔距离的具体数值，可以根据实际应用环境的需求确定，在此不作限定。
需要说明的是，在本申请一些实施例中，第一P型半导体区8是在栅极沟槽01形成后，在栅极沟槽01的底部采用垂直离子注入工艺形成的，因此，在第三方向z上，第一P型半导体区8可以覆盖栅极沟槽01。并且，由于离子注入工艺过程中离子的扩散性，第一P型半导体区8会向栅极沟槽01的底部外围扩散，即呈现出第一P型半导体区8在半导体衬底1上的正投影边缘位于栅极沟槽01在半导体衬底1上的正投影边缘的外围。
在另一些示例中，对应同一所述沟槽组的第一P型半导体区中，相邻的所述第一P型半导体区相互接触。也就是说，对应于同一沟槽组的多个第一P型半导体区之间无间隔距离或间隔距离为0。示例性地，参见图6b，以沟槽组GK2为例，在沟槽组GK2中，相邻的所述第一P型半导体区8之间相互接触，则沟槽组GK2对应的多个第一P型半导体区8 相互接触成了面状区域。
需要说明的是，栅极沟槽01中的沟槽间距C小于离子注入扩散尺寸时，例如在沟槽间距C小于0.4um时，离子会扩散并充满栅极沟槽01之间的间距区域，即多个第一P型半导体区8相互接触形成了面状区域，该面状区域的形状可认为是矩形。
本申请对第一P型半导体区8在第三方向x上的厚度不作限定，例如，第一P型半导体区8在第三方向上的厚度的范围可小于1um，例如，第一P型半导体区8在第三方向上的厚度的范围可为0.3um～0.8um。
示例性地，本申请实施例提供的SiC MOSFET在应用到功率转换电路中时，其源极可接地，其漏极可连接其他元件，则SiC MOSFET的源极的电压为接地电压(0V)。由于第一P型半导体区与源极连接，则第一P型半导体区的电压也为接地电压，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，本申请实施例提供的SiC MOSFET在应用到功率转换电路中时，其源极也可连接其他元件，其漏极也连接其他元件，则SiC MOSFET的源极的电压为其他元件输入的信号的电压。由于第一P型半导体区与源极连接，则第一P型半导体区的电压也为该输入的信号的电压，从而能够有效屏蔽栅极沟槽的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
在本申请一些实施例中，参照图3、图4以及图7至图9，第一外延层100还包括：第三P型半导体区9和第四P型半导体区5。第三P型半导体区9设置于栅极沟槽01沿第一方向的侧壁处，第四P型半导体区5和源区6同层设置。第二P型半导体区4、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5，可以是采用离子注入工艺，通过对第一外延层100进行掺杂形成的。并且，P型半导体区中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。
示例性地，第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5的掺杂浓度大于第二P型半导体区4的掺杂浓度。可选地，第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5的掺杂浓度可相同或相似。当然，也可以使第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5的掺杂浓度至少两个不相同。需要说明的是，第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5的掺杂浓度，可以根据实际应用环境的需求进行确定，在此不作限定。
参照图3、图4以及图7至图9，对应于同一栅极沟槽01的第三P型半导体区9与第一P型半导体区8相互接触，对应于同一栅极沟槽01的第四P型半导体区5与第三P型半导体区9接触，第四P型半导体区5通过接触孔02与源极13接触。则源极13依次通过第四P型半导体区5和第三P型半导体区9与第一P型半导体区8连接，以使源极13加载的电压依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，从而能够有效屏蔽栅极沟槽01的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，参照图3、图4以及图7至图9，在第一方向x上，栅极沟槽01具有相对设置的第一侧壁S1和第二侧壁S2。第三P型半导体区9设置了多个，每一个栅极沟槽01的第一侧壁S1设置了多个第三P型半导体区9中的一个第三P型半导体区9，并且每一个栅极沟槽01的第二侧壁S2也设置了多个第三P型半导体区9中的一个第三P型半导体区9。也就是说，每一个栅极沟槽01的第一侧壁S1和第二侧壁S2分别设置了第三P型半导体区9。并且，这些第三P型半导体区9均与对应的第一P型半导体区8相互接触，从而 可以使第三P型半导体区9均与对应的第一P型半导体区8连接，进行信号传输，则第三P型半导体区9均与第一P型半导体区8的电压相同。
示例性地，参照图3、图4以及图7至图9，第四P型半导体区5也设置了多个，该多个第四P型半导体区5与上述多个第三P型半导体区9一一对应且接触设置。其中，设置于第一侧壁S1的第三P型半导体区9中的每一个第三P型半导体区9对应设置多个第四P型半导体区5中的一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离栅极沟槽01的第一侧壁S1的一侧。以及，设置于第二侧壁S2的第三P型半导体区9中的每一个第三P型半导体区9对应设置多个第四P型半导体区5中的一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离栅极沟槽01的第二侧壁S2的一侧。则源极13依次通过相互对应设置的第四P型半导体区5和第三P型半导体区9与第一P型半导体区8连接，以使源极13加载的电压依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，使第一P型半导体区8具有电压，从而能够有效屏蔽栅极沟槽01的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，参照图3、图4以及图7至图9，本申请实施例提供的半导体器件中，源区6也设置了多个，位于栅极沟槽01同一端的多个源区和多个第四P型半导体区5交替设置。例如，位于同一沟槽组中的栅极沟槽01的第一侧壁S1处的多个源区6和多个第四P型半导体区5交替设置。以及，位于同一沟槽组中的栅极沟槽01的第二侧壁S2处的多个源区6和多个第四P型半导体区5交替设置。
本申请对第四P型半导体区5沿第二方向y的宽度不作限定，例如，可以使第四P型半导体区5沿第二方向y的宽度与沟槽宽度相同或相似。当然，也可以使第四P型半导体区5沿第二方向的宽度与沟槽宽度不同，在此不作限定。
示例性地，第一P型半导体区8在半导体衬底的正投影还覆盖对应的栅极沟槽的第一侧壁和第二侧壁中的至少一个侧壁处的第三P型半导体区9在半导体衬底的正投影。例如，参照图3至图9，在第三方向z上，第一P型半导体区8还覆盖对应设置的第三P型半导体区9。也就是说，第一P型半导体区8在半导体衬底1上的正投影不仅覆盖对应的栅极沟槽01在半导体衬底1上的正投影，还覆盖对应的第三P型半导体区9在半导体衬底1上的正投影。
参照图3与图8，在第二方向y上，相邻两个栅极沟槽01之间具有沟槽间距C。本申请对沟槽间距C的具体数值不作限定，例如，沟槽间距C小于1um。可选地，沟槽间距C的范围为50nm～0.5um。需要说明的是，沟槽间距C小于100nm时，本申请提供的半导体器件将形成鳍式场效应晶体管(Fin Field-Effect Transistor，Fin FET)效应，可显著提高载流子沟道迁移率，进一步降低器件导通总电阻。
参照图3与图8，间隔距离202小于沟槽间距C。
继续参照图3、图4以及图8，在第一方向上，栅极沟槽01具有沟槽长度D。本申请对沟槽长度D不作限定，例如，沟槽长度D大于5um。
继续参照图3，在第二方向y上，栅极沟槽01具有沟槽宽度E。本申请对沟槽宽度E不作限定，例如，沟槽宽度小于1um。
继续参照图3，在第一方向上，接触孔02具有接触宽度F，可以使沟槽间距C不大于接触宽度F。当然，也可以使沟槽间距C大于接触宽度F。在实际应用中，沟槽间距C与 接触宽度F可以根据实际应用的环境需求进行确定，在此不作限定。
本申请对源区6沿第二方向的宽度不作限定，例如，可以使源区6沿第二方向y的宽度与沟槽间距C相同或相似，在此不作限定。
参见图5，本申请实施例提供的半导体器件中，沟槽栅结构7在第二方向y上的栅极沟槽01的两个侧壁处的第二P型半导体区4形成了SiC MOSFET的沟道区，因而，通过增大沟槽宽度或减小沟槽间距C，可提高SiC MOSFET器件的导电沟道密度，降低SiC MOSFET器件的导通总电阻。
图10示出了本申请实施例提供的半导体器件产生导通电流时的一些示意图，图11示出了图10中沿GG’切线方向上的剖视结构示意图。参照图10与图11，黑色带箭头的直线代表SiC MOSFET导通时的导通电流的流动方向。示例性地，在SiC MOSFET的栅极11上加载正电平的电压时，可以控制本申请提供的沟槽栅结构的MOSFET导通，此时若在源极13和漏极14上加载不同的电压(例如，源极13上加载的电压大于漏极14上加载的电压)，则源极13和漏极14之间会产生，如图10与图11所示的由源极13流向漏极14的导通电流。
图12示出了本申请实施例提供的半导体器件的制备方法的一些流程图。参照图12，以制备图7所示的结构为例，在该制备方法中，可以包括以下步骤：
S10、在N型的半导体衬底上外延生长第一外延层。
示例性地，参照图13a，步骤S10，包括：采用外延工艺，在N型的SiC半导体衬底1上，外延生长掺杂有N型杂质的SiC材料，形成达到设定厚度DS0的第一外延层100。
本申请对设定厚度DS0的具体数值不作限定。在实际应用中，可以根据实际应用环境的需求，确定设定厚度DS0的具体数值。
S20、采用离子注入工艺，在第一外延层的部分区域中进行离子注入，形成第二N型半导体区以及源区，第一外延层中未进行离子注入的区域形成第一N型半导体区。
示例性地，参照图13b，采用离子注入工艺，在第一外延层的表面进行N型杂质掺杂，形成第二N型半导体区3。之后，采用离子注入工艺，在第一外延层的表面进行P型杂质掺杂，形成第二P型半导体区4。之后，采用离子注入工艺，在第一外延层100的表面进行N型杂质掺杂，形成源区6，以及在栅极沟槽01的第一侧壁S1和第二侧壁S2处的第一外延层100的表面进行P型杂质掺杂，形成与源区6同层设置的第四P型半导体区5。
因此，本申请实施例中，经过该离子注入工艺后，第一外延层100的部分区域形成了第二N型半导体区3、第二P型半导体区4、源区6以及第四P型半导体区5，而第一外延层100中未采用该离子注入工艺进行离子注入的区域，则形成了第一N型半导体区2。
S30、刻蚀第一外延层至第一N型半导体区，在第一外延层中形成相互间隔设置的多个栅极沟槽。
示例性地，首先，在第一外延层上形成沟槽掩膜(该沟槽掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该沟槽掩膜将形成栅极沟槽01的第一外延层中的区域遮盖上，而将需要形成栅极沟槽01的第一外延层中的区域暴露出来。之后，参照图13c，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对第一外延层中未被沟槽掩膜遮盖的区域进行刻蚀，直至刻蚀至第一N型半导体区2中，在第一外延层中形成沿第一方向x延伸且沿第二方向y排列的多个栅极沟槽01。
S40、采用离子注入工艺，在每一个栅极沟槽的下方形成对应的第一P型半导体区。
示例性地，参照图13d，可以采用垂直离子注入工艺，向栅极沟槽01的底部掺杂P型杂质，形成与栅极沟槽01底部图形一致或面状区域的第一P型半导体区8。
本申请对第一P型半导体区8的厚度(即在第三方向上的厚度)不作限定。在实际应用中，可以根据实际应用环境的需求，确定第一P型半导体区8的厚度的具体数值。
S50、采用倾斜离子注入工艺，在每一个栅极沟槽沿第一方向上的第一侧壁和第二侧壁上，分别形成与第一P型半导体区接触的第三P型半导体区。
示例性地，参照图13e，采用倾斜离子注入工艺，在每一个栅极沟槽01的第一侧壁S1和第二侧壁S2的表面进行P型杂质掺杂，分别形成与第一P型半导体区8接触的第三P型半导体区9。
S60、在栅极沟槽中形成栅介质层。
示例性地，参照图13e，采用氧化工艺，对整个第一外延层进行氧化处理，使第一外延层的表面形成栅介质层10。即，每一个栅极沟槽01的表面形成了栅介质层10，第一外延层的背离半导体衬底1的一侧也形成了栅介质层10。
S70、在形成有栅介质层的栅极沟槽中形成栅极中的第一栅极，以及在第一外延层上形成栅极中的第二栅极，并使第一栅极和第二栅极相互接触。
示例性地，首先，采用沉积工艺，在形成有栅极沟槽的第一外延层的整体上沉积多晶硅材料，并使该多晶硅材料填充栅极沟槽，且在采用多晶硅材料填充栅极沟槽后第一外延层的整体上覆盖多晶硅材料膜层。之后，在第一外延层上形成栅极掩膜(该栅极掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该栅极掩膜将形成第二栅极的区域遮盖上，而将其余区域暴露出来。之后，参照图13f，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对未被沟槽掩膜遮盖的多晶硅材料区域进行刻蚀，直至刻蚀至暴露出源区6和第四P型半导体区5时停止刻蚀，以形成第一栅极111以及第二栅极112。
S80、在栅极上形成覆盖整个第一外延层的层间介质层。
示例性地，参照图13g，采用沉积工艺，在整个第一外延层上沉积层间介质层12，并使层间介质层12覆盖整个第一外延层。
S90、刻蚀层间介质层，形成沿第二方向延伸的接触孔。
示例性地，首先，在第一外延层上形成接触孔掩膜(该接触孔掩膜可以是采用光刻胶形成的掩膜或者是硬掩膜板)，通过该接触孔掩膜将不需要形成接触孔02的区域遮盖上，而将需要形成接触孔02的区域暴露出来。之后，参照图13h，从等离子刻蚀工艺、离子溅射刻蚀工艺和反应离子刻蚀工艺等刻蚀工艺中选取合适的刻蚀工艺，对层间介质层12未被接触孔02掩膜遮盖的区域进行刻蚀，暴露出源区6在第一方向x上位于第一栅极111两侧的部分以及暴露出第四P型半导体区5位于第一栅极111两侧的部分。
S100、在层间介质层远离半导体衬底一侧形成源极，并使源极通过接触孔与源区接触。以及在半导体衬底远离第一外延层的一侧形成漏极。
本申请对源极和漏极的材料不作限定，例如，形成源极和漏极的材料可以为金属材料。示例性地，该金属材料可以包括W、Al、Ti、Cu、Mo或Pt。
示例性地，参照图13i，采用沉积工艺，在层间介质层12远离半导体衬底1一侧沉积金属材料，形成源极13。并通过金属材料填充接口孔，使源极13通过接触孔02中填充的金属材料与源区6接触。
示例性地，参照图13i，可以在形成源极13时，采用沉积工艺，在半导体衬底1远离第一外延层的一侧沉积金属材料，形成漏极14。或者，也可以在源极13之后，采用沉积工艺，在半导体衬底1远离第一外延层的一侧沉积金属材料，形成漏极14。
图14示出了本申请另一种实施例提供的半导体器件的立体结构示意图。图15示出了图14所示的半导体器件中未设置层间介质层和源极时的立体结构示意图，图16示出了图14所示的半导体器件中的栅极沟槽的立体结构示意图。
参照图14至图16，在本申请提供的又一些实施例中，本申请实施例提供的半导体器件，包括：N型的半导体衬底1、第一外延层、相互间隔设置的多个栅极沟槽01、栅极11、层间介质层12、源极13以及漏极14。并且，第一外延层包括：第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、源区6、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图14至图16，在本实施例中，第三P型半导体区9设置了多个，每一个栅极沟槽01的第一侧壁S1设置了多个第三P型半导体区9中的一个第三P型半导体区9，并且每一个栅极沟槽01的第二侧壁S2未设置第三P型半导体区9。也就是说，仅在每一个栅极沟槽01的第一侧壁S1处分别设置了第三P型半导体区9。并且，这些第三P型半导体区9均与对应的第一P型半导体区8相互接触，从而可以使第三P型半导体区9均与对应的第一P型半导体区8连接，进行信号传输，则第三P型半导体区9均与第一P型半导体区8的电压相同。
示例性地，参照图14至图16，第四P型半导体区5也设置了多个，该多个第四P型半导体区5与上述多个第三P型半导体区9一一对应且接触设置。其中，设置于第一侧壁S1的第三P型半导体区9中的每一个第三P型半导体区9对应设置多个第四P型半导体区5中的一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离栅极沟槽01的第一侧壁S1的一侧。则源极13依次通过相互对应设置的第四P型半导体区5和第三P型半导体区9与第一P型半导体区8连接，以使源极13加载的电压依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，使第一P型半导体区8具有电压，从而能够有效屏蔽栅极沟槽01的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，参照图14至图16，第一外延层还包括：第五P型半导体区15，第五P型半导体区15和源区6同层设置，第五P型半导体区15设置于栅极沟槽01的第二侧壁S2背离第一侧壁S1的一侧，且第五P型半导体区15通过接触孔02与源极13接触。
示例性地，第五P型半导体区15为多个，该多个第五P型半导体区15与多个栅极沟槽01的第二侧壁一一对应设置，即一个栅极沟槽01的第二侧壁S2与一个第五P型半导体区15一一对应设置。可选地，位于栅极沟槽01的第二侧壁S2的多个源区6和多个第五P型半导体区15交替设置。即，位于栅极沟槽01的同一侧壁处的多个源区6和多个第五P型半导体区15沿第二方向y交替设置。
示例性地，源区设置为多个，且栅极沟槽01与多个源区6交替设置。即栅极沟槽01与源区6沿第二方向y交替设置。即位于栅极沟槽01的第二侧壁S2的多个源区和多个第五P型半导体区15交替设置。
可选地，第五P型半导体区15可以是采用离子注入工艺，通过对第一外延层进行掺 杂形成的。并且，第五P型半导体区15中掺杂的主要是P型杂质，例如硼(B)、铝(Al)或镓(Ga)等。示例性地，第五P型半导体区15的掺杂浓度与第四P型半导体区5的掺杂浓度相同或相似。
本申请实施例中，栅极沟槽01的第一侧壁S1处设置了第三P型半导体区9，不形成沟道。
以制备图14所示的结构为例，对应的制备方法的流程图可以参照图12。其中，步骤S10～S40、S60～S100可以参照上述的制备方法的描述。
在本实施例中，步骤S50为：采用倾斜离子注入工艺，在每一个栅极沟槽沿第一方向上的第一侧壁上，分别形成与第一P型半导体区接触的第三P型半导体区。
示例性地，参照图16，采用倾斜离子注入工艺，在每一个栅极沟槽01的第一侧壁S1的表面进行P型杂质掺杂，分别形成与第一P型半导体区8接触的第三P型半导体区9。
图17示出了本申请又一种实施例提供的半导体器件的立体结构示意图。图18示出了图17所示的半导体器件中未设置层间介质层和源极时的立体结构示意图，图19示出了图17所示的半导体器件中的栅极沟槽的立体结构示意图。
参照图17至图19，在本申请提供的又一些实施例中，半导体器件包括：N型的半导体衬底1、第一外延层、相互间隔设置的多个栅极沟槽01、栅极11、层间介质层12、源极13以及漏极14。并且，第一外延层包括：第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、源区6、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图17至图19，在本实施例中，第三P型半导体区9设置了多个，每一个栅极沟槽01的第一侧壁S1设置了多个第三P型半导体区9中的一个第三P型半导体区9，并且每一个栅极沟槽的第二侧壁未设置第三P型半导体区9。也就是说，仅在每一个栅极沟槽01的第一侧壁S1处分别设置了第三P型半导体区9。并且，这些第三P型半导体区9均与对应的第一P型半导体区8相互接触，从而可以使第三P型半导体区9均与对应的第一P型半导体区8连接，进行信号传输，则第三P型半导体区9均与第一P型半导体区8的电压相同。
示例性地，参照图17至图19，第四P型半导体区5也设置了多个，该多个第四P型半导体区5与上述多个第三P型半导体区9一一对应且接触设置。其中，设置于第一侧壁S1的第三P型半导体区9对应设置多个第四P型半导体区5中的一个第四P型半导体区5，且该第四P型半导体区5设置于第三P型半导体区9远离栅极沟槽01的第一侧壁S1的一侧。则源极13依次通过相互对应设置的第四P型半导体区5和第三P型半导体区9与第一P型半导体区8连接，以使源极13加载的电压依次通过第四P型半导体区5和第三P型半导体区9输入到第一P型半导体区8，使第一P型半导体区8具有电压，从而能够有效屏蔽栅极沟槽01的底部的栅极介质层电场，进而提升器件工作的鲁棒性。
示例性地，参照图17至图19，仅在栅极沟槽01的第一侧壁S1处设置了第四P型半导体区5，而在栅极沟槽01的第二侧壁S2处设置的均为源区6。而栅极沟槽01的第二侧壁S2处的第二P型半导体区4可以受第一栅极111的控制以形成沟道，同时在栅极沟槽01的第二侧壁S2处设置源区6，则导通电流能够从栅极沟槽01的第二侧壁S2处的第二P型半导体区4传输到漏极14上，进一步提高导通电流的流动路径。
以制备图17所示的结构为例，对应的制备方法的流程图可以参照图12。其中，步骤S10、S30～S40、S60～S100可以参照上述的制备方法的描述。
在本实施例中，步骤S20为：采用离子注入工艺，在第一外延层的部分区域中进行离子注入，形成第二N型半导体区、第二P型半导体区以及源区，第一外延层中未进行离子注入的区域形成第一N型半导体区。
示例性地，参照图19，采用离子注入工艺，在第一外延层的表面进行N型杂质掺杂，形成第二N型半导体区3。之后，采用离子注入工艺，在第一外延层的表面进行P型杂质掺杂，形成第二P型半导体区4。之后，采用离子注入工艺，在第一外延层的表面进行N型杂质掺杂，形成源区6，以及在栅极沟槽01的第一侧壁S1处的第一外延层的表面进行P型杂质掺杂，形成与源区6同层设置的第四P型半导体区5。因此，本申请实施例中，经过该离子注入工艺后，第一外延层的部分区域形成了第二N型半导体区3、第二P型半导体区4、源区6以及第四P型半导体区5，而第一外延层中未采用该离子注入工艺进行离子注入的区域，则形成了第一N型半导体区2。
在本实施例中，步骤S50为：采用倾斜离子注入工艺，在每一个栅极沟槽01沿第一方向上的第一侧壁S1上，分别形成与第一P型半导体区8接触的第三P型半导体区9。
示例性地，参照图19，采用倾斜离子注入工艺，在每一个栅极沟槽01的第一侧壁S1的表面进行P型杂质掺杂，分别形成与第一P型半导体区8接触的第三P型半导体区9。
图20示出了本申请另一种实施例提供的半导体器件的俯视结构示意图。
参照图20，在本申请提供的又一些实施例中，半导体器件包括：N型的半导体衬底1、第一外延层、相互间隔设置的多个栅极沟槽01、栅极11、层间介质层12、源极13以及漏极14。并且，第一外延层包括：第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、源区6、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图20，相邻两个沟槽组中的部分栅极沟槽01中，沿第一方向x排列的栅极沟槽01贯通。例如，沟槽组GK1中的栅极沟槽01c1和沟槽组GK2中的栅极沟槽01c2沿第一方向x排列，且栅极沟槽01c1和栅极沟槽01c2相互贯通。沟槽组GK1中的栅极沟槽01d1和沟槽组GK2中的栅极沟槽01d2沿第一方向x排列，且栅极沟槽01d1和栅极沟槽01d2相互贯通。沟槽组GK1中的栅极沟槽01e1和沟槽组GK2中的栅极沟槽01e2沿第一方向排列，且栅极沟槽01e1和栅极沟槽01e2相互贯通。
示例性地，本申请中，该多个栅极沟槽包括沿第一方向x贯通的第一栅极沟槽和第二栅极沟槽，其中，第一栅极沟槽和第二栅极沟槽分别位于相邻的两个沟槽组。即第一栅极沟槽位于该相邻的两个沟槽组中的一个沟槽组中，第二栅极沟槽位于该相邻的两个沟槽组中的另一个沟槽组中，并且该第一栅极沟槽和第二栅极沟槽相互贯通。例如，参照图20，沟槽组GK1中的栅极沟槽01c1可以作为第一栅极沟槽，沟槽组GK2中的栅极沟槽01c2可以作为第二栅极沟槽，且沟槽组GK1中的栅极沟槽01c1和沟槽组GK2中的栅极沟槽01c2相互贯通。沟槽组GK1中的栅极沟槽01d1可以作为第一栅极沟槽，沟槽组GK2中的栅极沟槽01d2可以作为第二栅极沟槽，且沟槽组GK1中的栅极沟槽01d1和沟槽组GK2中的栅极沟槽01d2相互贯通。沟槽组GK1中的栅极沟槽01e1可以作为第一栅极沟槽，沟槽组GK2中的栅极沟槽01e2可以作为第二栅极沟槽，且沟槽组GK1中的栅极沟槽01e1 和沟槽组GK2中的栅极沟槽01e2相互贯通。
参照图20，接触孔02包括多个相互间隔设置的子接触孔，同一接触孔02中相邻的两个子接触孔之间设置有至少一个贯通的栅极沟槽01。本申请对接触孔02划分为的子接触孔的数量不作限定，例如，可以为两个、三个、四个或更多个。并且，本申请对同一接触孔02中相邻的两个子接触孔之间设置的贯通的栅极沟槽01的数量不作限定，例如，可以为一个、两个、三个、四个或更多个。这样可以提高接触孔02的设计自由度，可提升SiC MOSFET器件的通流均匀性。
示例性地，参照图20，接触孔包括相互间隔设置的子接触孔：02a和02b。子接触孔02a和02b之间设置有由栅极沟槽01d1和01d2相互贯通的栅极沟槽。
图21示出了本申请又一种实施例提供的半导体器件的立体结构示意图。
参照图21，在本申请提供的又一些实施例中，半导体器件包括：N型的半导体衬底1、第一外延层、第二外延层201、相互间隔设置的多个栅极沟槽01、栅极11、层间介质层12、源极13以及漏极14。并且，第一外延层包括：第一N型半导体区2、第二N型半导体区3、第二P型半导体区4、源区6、第一P型半导体区8、第三P型半导体区9以及第四P型半导体区5。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图21，第二外延层201设置于第一外延层(例如第一N型半导体区2)与半导体衬底1之间。由于设置了第二外延层201，则可以使第一外延层100中的第一P型半导体区8在第三方向z上的厚度设置的较厚一些，例如，可使第一P型半导体区8在第三方向z上的厚度设置大于1um。
参照图21，在本实施例中，第二外延层201为N型半导体区。示例性地，第二外延层201为掺杂有N型杂质的SiC，该N型杂质例如为氮(N)、磷(P)或砷(As)等。示例性地，第二外延层201的掺杂浓度小于第一N型半导体区2的掺杂浓度。
以制备图21所示的结构为例，对应的制备方法的流程图可以参照图22。其中，步骤S10～S100可以参照上述的制备方法的描述。
在步骤S10之前，还包括步骤S00：在N型的半导体衬底1上外延生长第二外延层。
示例性地，参照图21，在N型的SiC半导体衬底1上，采用外延工艺，在N型的SiC半导体衬底1上，外延生长掺杂有N型杂质的SiC材料，形成第二外延层201。
本申请实施例还提供了功率转换电路，该功率转换电路可以为交流-直流转换电路和/或直流-直流转换电路。该功率转换电路可以包括：电路板和一个或多个半导体器件，并且该半导体器件与电路板连接。由于上述半导体器件的性能较好，因而，包括上述半导体器件的功率转换电路的性能也较好。以及，该功率转换电路解决问题的原理与前述半导体器件可以解决问题的原理相似，因此该功率转换电路的技术效果可以参照前述半导体器件的技术效果，重复之处不再赘述。
本申请实施例还提供了车辆，该车辆包括本申请实施例提供的功率转换电路。由于上述功率转换电路的性能较好，因而，包括上述功率转换电路的车辆的电路性能也较好。以及，该车辆解决问题的原理与前述功率转换电路可以解决问题的原理相似，因此该车辆的技术效果可以参照前述功率转换电路的技术效果，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内， 则本申请也意图包含这些改动和变型在内。

Claims (19)

  1. 一种半导体器件，其特征在于，包括：
    N型的半导体衬底；
    第一外延层，所述第一外延层设置于所述半导体衬底上；
    相互间隔设置的多个栅极沟槽，所述多个栅极沟槽沿垂直于所述半导体衬底所在平面的第三方向上延伸至所述第一外延层中；其中，所述多个栅极沟槽沿平行于所述半导体衬底所在平面的第一方向延伸，所述多个栅极沟槽沿平行于所述半导体衬底所在平面的第二方向排列；所述第一方向、所述第二方向以及所述第三方向相互交叉设置；
    栅极，所述栅极包括相互接触的第一栅极和第二栅极，所述第一栅极隔着栅介质层填充设置于所述栅极沟槽中，所述第二栅极隔着所述栅介质层设置于所述第一外延层顶部；
    层间介质层，所述层间介质层覆盖于所述栅极远离所述半导体衬底一侧，且所述层间介质层具有接触孔；其中，所述接触孔沿所述第二方向延伸，所述接触孔在所述半导体衬底的正投影与所述栅极在所述半导体衬底的正投影互不交叠，且所述接触孔暴露出所述第一外延层的部分区域；
    源极，所述源极设置于所述层间介质层远离所述半导体衬底一侧，且所述源极通过所述接触孔与所述接触孔暴露出的所述第一外延层接触；
    漏极，所述漏极设置于所述半导体衬底远离所述第一外延层的一侧；
    其中，所述第一外延层包括：多个第一P型半导体区，所述多个第一P型半导体区与所述多个栅极沟槽一一对应且设置于对应的栅极沟槽的下方，所述多个第一P型半导体区中的每一个第一P型半导体区与所述源极导通。
  2. 如权利要求1所述的半导体器件，其特征在于，所述多个第一P型半导体区中的每一个第一P型半导体区与对应的所述栅极沟槽的底端接触设置；
    所述多个第一P型半导体区中的每一个第一P型半导体区在所述半导体衬底的正投影覆盖对应的所述栅极沟槽的底端在所述半导体衬底的正投影。
  3. 如权利要求2所述的半导体器件，其特征在于，所述第一P型半导体区在所述半导体衬底的正投影的边缘位于对应的所述栅极沟槽的底端在所述半导体衬底的正投影的边缘外围。
  4. 如权利要求1-3任一项所述的半导体器件，其特征在于，所述多个栅极沟槽划分为至少一个沟槽组；所述接触孔为至少两个；
    相邻的两个所述接触孔之间设置一个所述沟槽组，所述接触孔在所述第二方向上贯穿所述沟槽组。
  5. 如权利要求4所述的半导体器件，其特征在于，所述多个栅极沟槽包括沿所述第一方向贯通的第一栅极沟槽和第二栅极沟槽，其中，所述第一栅极沟槽和所述第二栅极沟槽分别位于相邻的两个所述沟槽组；
    所述接触孔包括多个相互间隔设置的子接触孔，同一接触孔中相邻的两个子接触孔之间设置有至少一个贯通的栅极沟槽。
  6. 如权利要求4或5所述的半导体器件，其特征在于，对应同一所述沟槽组的第一P型半导体区中，相邻的所述第一P型半导体区之间具有间隔距离；
    或者，对应同一所述沟槽组的第一P型半导体区中，相邻的所述第一P型半导体区相 互接触。
  7. 如权利要求1-6任一项所述的半导体器件，其特征在于，所述第一外延层包括：第一N型半导体区、第二N型半导体区、第二P型半导体区以及源区，所述第一N型半导体区设置于所述第二N型半导体区与所述半导体衬底之间，所述第二P型半导体区设置于所述第二N型半导体区远离所述半导体衬底一侧，所述源区设置于所述第二P型半导体区远离所述半导体衬底一侧，所述第一P型半导体区设置于所述第一N型半导体区内；
    在垂直于所述半导体衬底所在平面的第三方向上，所述栅极沟槽延伸至所述第一N型半导体区中；
    所述接触孔暴露出所述源区的部分区域。
  8. 如权利要求7所述的半导体器件，其特征在于，在所述第一方向上，所述栅极沟槽具有相对设置的第一侧壁和第二侧壁；
    所述第一外延层还包括：
    第三P型半导体区，所述第三P型半导体区设置于至少一个所述栅极沟槽的第一侧壁和/或第二侧壁，以及所述第三P型半导体区与所述第二P型半导体区相互接触；
    第四P型半导体区，所述第四P型半导体区和所述源区同层设置，且所述第四P型半导体区设置于所述第三P型半导体区远离栅极沟槽的一侧，以及所述第四P型半导体区与所述第三P型半导体区接触，所述第四P型半导体区通过所述接触孔与所述源极接触。
  9. 如权利要求8所述的半导体器件，其特征在于，所述第一外延层还包括：
    第五P型半导体区，所述第五P型半导体区和所述源区同层设置，所述第五P型半导体区设置于所述栅极沟槽的第二侧壁背离第一侧壁的一侧，且所述第五P型半导体区通过所述接触孔与所述源极接触。
  10. 如权利要求9所述的半导体器件，其特征在于，第五P型半导体区为多个，所述多个第五P型半导体区与多个所述栅极沟槽的第二侧壁一一对应设置；
    所述源区为多个，所述栅极沟槽与所述多个源区交替设置。
  11. 如权利要求8-10任一项所述的半导体器件，其特征在于，所述第一P型半导体区在所述半导体衬底的正投影还覆盖对应的所述栅极沟槽的第一侧壁和第二侧壁中的至少一个侧壁处的所述第三P型半导体区在所述半导体衬底的正投影。
  12. 如权利要求7-11任一项所述的半导体器件，其特征在于，所述半导体器件还包括：
    N型的第二外延层，所述第二外延层设置于所述第一外延层与所述半导体衬底之间，且所述第二外延层的掺杂浓度小于所述第一N型半导体区的掺杂浓度；
    所述第二外延层在所述第三方向上的厚度大于1um。
  13. 如权利要求1-12任一项所述的半导体器件，其特征在于，所述半导体衬底、所述第一外延层以及第二外延层的材料为SiC。
  14. 一种半导体器件的制备方法，其特征在于，包括：
    在N型的半导体衬底上外延生长第一外延层；
    刻蚀所述第一外延层，形成沿垂直于所述半导体衬底所在平面的第三方向上延伸至所述第一外延层中的相互间隔设置的多个栅极沟槽，所述多个栅极沟槽沿平行于所述半导体衬底所在平面的第一方向延伸，所述多个栅极沟槽沿平行于所述半导体衬底所在平面的第二方向排列；所述第一方向、所述第二方向以及所述第三方向相互交叉设置；
    采用离子注入工艺，在每一个所述栅极沟槽的下方形成对应的所述第一P型半导体区；
    在所述栅极沟槽中形成栅介质层；
    在形成有栅介质层的栅极沟槽中形成栅极中的第一栅极，以及在所述第一外延层顶部形成栅极中的第二栅极，并使第一栅极和第二栅极相互接触；
    在所述栅极上形成覆盖整个第一外延层的层间介质层；
    刻蚀所述层间介质层，形成沿所述第二方向延伸的接触孔，所述接触孔暴露出所述第一外延层的部分区域，且所述接触孔在所述半导体衬底的正投影与所述栅极在所述半导体衬底的正投影互不交叠；
    在所述层间介质层远离所述半导体衬底一侧形成源极，使所述源极通过所述接触孔与所述接触孔暴露出的所述第一外延层接触，并使所述源极与每一个所述第一P型半导体区连接，以及在所述半导体衬底远离所述第一外延层的一侧形成漏极。
  15. 如权利要求14所述的制备方法，其特征在于，在N型的半导体衬底上外延生长第一外延层之后，所述制备方法还包括：
    采用离子注入工艺，在所述第一外延层的部分区域中进行离子注入，形成第二N型半导体区、第二P型半导体区以及源区，所述第一外延层中未进行离子注入的区域形成第一N型半导体区；其中，所述第一N型半导体区设置于所述第二N型半导体区与所述半导体衬底之间，所述第二P型半导体区设置于所述第二N型半导体区远离所述半导体衬底一侧，所述源区设置于所述第二P型半导体区远离所述半导体衬底一侧；
    所述接触孔暴露出所述源区的部分区域。
  16. 如权利要求14或15所述的制备方法，其特征在于，所述采用离子注入工艺，在每一个所述栅极沟槽的下方形成对应的所述第一P型半导体区，包括：
    采用垂直离子注入工艺，在每一个所述栅极沟槽的下方形成对应的所述第一P型半导体区。
  17. 如权利要求16所述的制备方法，其特征在于，所述制备方法还包括：
    在形成所述源区时，采用离子注入工艺，在所述第一外延层中形成与所述源区同层设置的第四P型半导体区；
    所述制备方法还包括：
    在所述栅极沟槽中形成栅介质层之前，采用倾斜离子注入工艺，在所述栅极沟槽沿所述第一方向上的至少一个侧壁形成与所述第一P型半导体区接触的第三P型半导体区。
  18. 一种功率转换电路，其特征在于，包括电路板以及一个或多个如权利要求1-13任一项所述的半导体器件，所述半导体器件与所述电路板连接。
  19. 一种车辆，其特征在于，包括如权利要求18所述的功率转换电路，所述功率转换电路用于对交流电和/或直流电进行转换后输出直流电。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000054342A1 (en) * 1999-03-10 2000-09-14 Nova Crystals, Inc. HIGH BRIGHTNESS NITRIDE-BASED LEDs
CN111370487A (zh) * 2018-12-26 2020-07-03 深圳尚阳通科技有限公司 沟槽栅mosfet器件及其制造方法
CN111370463A (zh) * 2018-12-26 2020-07-03 深圳尚阳通科技有限公司 沟槽栅功率器件及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000054342A1 (en) * 1999-03-10 2000-09-14 Nova Crystals, Inc. HIGH BRIGHTNESS NITRIDE-BASED LEDs
CN111370487A (zh) * 2018-12-26 2020-07-03 深圳尚阳通科技有限公司 沟槽栅mosfet器件及其制造方法
CN111370463A (zh) * 2018-12-26 2020-07-03 深圳尚阳通科技有限公司 沟槽栅功率器件及其制造方法

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