CN111192915A - 半导体功率器件及其制造方法 - Google Patents

半导体功率器件及其制造方法 Download PDF

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CN111192915A
CN111192915A CN201811360699.7A CN201811360699A CN111192915A CN 111192915 A CN111192915 A CN 111192915A CN 201811360699 A CN201811360699 A CN 201811360699A CN 111192915 A CN111192915 A CN 111192915A
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power device
epitaxial layer
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毛振东
刘伟
刘磊
袁愿林
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Suzhou Oriental Semiconductor Co Ltd
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Abstract

本发明属于半导体功率器件技术领域，具体公开了一种半导体功率器件，包括第一导电类型的漏区；位于所述漏区之上的第二导电类型的外延层；位于所述外延层内的交替排列的栅沟槽和第二导电类型的体区；位于所述体区中的第一导电类型的源区；位于所述栅沟槽的上部的第一栅极；至少位于所述栅沟槽的下部的第二栅极；所述第一栅极、所述第二栅极与所述外延层之间由绝缘介质层隔离；位于所述外延层内的第一导电类型的掺杂区，所述掺杂区围绕所述栅沟槽的下部且与所述漏区连接。本发明在半导体功率器件中引入了电荷平衡结构，能够降低半导体功率器件的特征导通电阻。

Description

半导体功率器件及其制造方法
技术领域
本发明属于半导体功率器件技术领域，特别是涉及一种半导体功率器件及其制造方法。
背景技术
图1是现有技术的一种半导体功率器件的剖面结构示意图，如图1所示，现有技术的一种半导体功率器件包括：n型半导体基底100，位于n型半导体基底100底部的n型漏区10，位于n型半导体基底100中交替排列的栅沟槽和p型体区16，位于p型体区16中的n型源区17，位于所述栅沟槽中的栅介质层12、第一栅极13、绝缘介质层14和第二栅极15，第一栅极13位于栅沟槽的上部并通过栅极电压来控制n型源区17与n型漂移区11之间的电流沟道的开启和关断。第二栅极15位于栅沟槽的下部且向上延伸至栅沟槽的上部，第二栅极15通过源极金属层19与n型源区17连接，第二栅极15通过源极电压在n型漂移区11内形成横向电场，起到提高耐压的作用。层间绝缘层18用于将源极金属层19与栅极金属层隔离，基于剖面的位置关系，栅极金属层在图1中未示出。
特征导通电阻(Rsp)是评价半导体功率器件电流导通能力的重要指标，现有技术的半导体功率器件可以通过提高n型漂移区的掺杂浓度来降低特征导通电阻，但是n型漂移区的掺杂浓度的提高会影响半导体功率器件的耐压。
发明内容
有鉴于此，本发明的目的是提供一种半导体功率器件及其制造方法，以解决现有技术中的如何进一步降低半导体功率器件的特征导通电阻的问题。
为达到本发明的上述目的，本发明提供了一种半导体功率器件，包括：
第一导电类型的漏区；
位于所述漏区之上的第二导电类型的外延层；
位于所述外延层内的交替排列的栅沟槽和第二导电类型的体区；
位于所述体区中的第一导电类型的源区；
位于所述栅沟槽的上部的第一栅极；
至少位于所述栅沟槽的下部的第二栅极；
所述第一栅极、所述第二栅极与所述外延层之间由绝缘介质层隔离；
位于所述外延层内的第一导电类型的掺杂区，所述掺杂区围绕所述栅沟槽的下部且与所述漏区连接。
可选的，本发明的半导体功率器件，所述第二栅极从所述栅沟槽的下部向上延伸至所述栅沟槽的上部。
可选的，本发明的半导体功率器件，所述栅沟槽的上部的宽度大于所述栅沟槽的下部的宽度。
可选的，本发明的半导体功率器件，所述第一栅极接栅极电压，所述体区、所述源区与所述第二栅极均接源极电压。
可选的，本发明的半导体功率器件，所述第一导电类型为n型，所述第二导电类型为p型。
本发明的半导体功率器件的制造方法，包括：
在第一导电类型的半导体衬底上形成第二导电类型的外延层；
在所述外延层内形成第一沟槽；
在所述第一沟槽内形成第一栅极；
在所述外延层内形成位于所述第一沟槽下方的第二沟槽；
进行离子注入，在所述外延层内形成围绕所述第二沟槽的第一导电类型的掺杂区；
至少在所述第二沟槽内形成第二栅极，其中，所述第一栅极、所述第二栅极和所述外延层相绝缘。
可选的，本发明的半导体功率器件的制造方法，所述第二栅极从所述第二沟槽内向上延伸至所述第一沟槽内。
本发明的半导体功率器件是在n型漏区之上设置p型外延层，在p型外延层内形成围绕栅沟槽的下部的n型掺杂区，n型掺杂区的掺杂杂质与p型外延层的掺杂杂质形成电荷平衡，用以提高半导体功率器件的耐压，从而在不影响半导体功率器件耐压的条件下，可以提高n型掺杂区的掺杂浓度，降低半导体功率器件的特征导通电阻。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。显然，所介绍的附图只是本发明所要描述的一部分实施例的附图，而不是全部的附图，对于本领域普通技术人员，在不付出创造性劳动的前提下，还可以根据这些附图得到其他的附图。
图1是现有技术的一种半导体功率器件的剖面结构示意图；
图2是本发明的一种半导体功率器件的剖面结构示意图；
图3至图7是本发明的半导体功率器件的制造方法的一个实施例的工艺流程中的主要结构的剖面结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下将结合本发明实施例中的附图，通过具体方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例，基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动的前提下获得的所有其他实施例，均落入本发明的保护范围之内。
应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸；说明书附图是示意性的，不应限定本发明的范围。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图2是本发明的一种半导体功率器件的一个实施例的剖面结构示意图。如图2所示，本发明实施例的一种半导体功率器件包括第一导电类型的漏区21，以及位于漏区21之上的第二导电类型的外延层22。第一导电类型与第二导电类型为相反的导电类型，可以是第一导电类型为n型，第二导电类型为p型；也可以是第一导电类型为p型，第二导电类型为n型。
位于第二导电类型的外延层22中的交替排列的栅沟槽和第二导电类型的体区27，位于体区27中的第一导电类型的源区28。在本发明实施例中示例性的示出了2个栅沟槽和3个体区27，栅沟槽和体区27的具体数量依据产品的具体设计要求确定
位于栅沟槽的上部的第一栅极24，至少位于栅沟槽的下部的第二栅极26，第一栅极24、第二栅极26和外延层22之间由绝缘介质层23隔离。绝缘介质层23的材质通常为氧化硅。
优选的，栅沟槽的上部的宽度大于栅沟槽的下部的宽度，第二栅极26从栅沟槽的下部向上延伸至栅沟槽的上部，如图2所示。
第二栅极26、体区27和源区28均通过源极金属层30接源极电压，第一栅极24通过栅极金属层接栅极电压，基于剖面的位置关系，栅极金属层在图2中未示出，栅极金属层与源极金属层30通过层间绝缘层29隔离，层间绝缘层29的材质通常为硅玻璃、硼磷硅玻璃或磷硅玻璃。
图2中，源极金属层30嵌入至体区27内，可选的，源极金属层30可以不嵌入至体区27中，而是在体区27内形成高掺杂浓度的接触区，源极金属层通过该高掺杂浓度的接触区与体区接触连接，该结构为现有技术中经常使用的结构，本发明实施例中不再具体展示。
位于外延层22内的第一导电类型的掺杂区25，掺杂区25围绕栅沟槽的下部且与漏区21连接，由此第一导电类型的掺杂区25的掺杂杂质与第二导电类型的外延层22的掺杂杂质形成电荷平衡，这可以提高半导体功率器件的耐压，从而在不影响半导体功率器件耐压的条件下，可以通过提高第一导电类型的掺杂区25的掺杂浓度来降低半导体功率器件的特征导通电阻。
图3至图7是本发明提供的一种半导体功率器件的制造方法的一个实施例的工艺流程中的主要结构的剖面结构示意图，为了方便展示，图3至图7中，没有展示制造过程中的光刻胶层结构。
首先，如图3所示，提供一个第一导电类型的半导体衬底20，在半导体衬底20之上形成第二导电类型的外延层22，在外延层22之上形成掩膜层300，然后进行光刻和刻蚀，在外延层22内形成第一沟槽301，第一沟槽301即本发明的半导体功率器件的栅沟槽的上部。在本发明实施例中，在刻蚀外延层22时，通过增加横向的刻蚀使得第一沟槽301的宽度大于掩膜层300中的开口宽度。
接下来，如图4所示，在第一沟槽的表面形成栅氧化层33，然后淀积第一层导电薄膜并回刻，在第一沟槽内形成第一栅极24，第一栅极24位于第一沟槽的侧壁位置处。
接下来，如图5所示，以掩膜层300为掩膜刻蚀掉暴露出的栅氧化层33，并继续对外延层22进行刻蚀，在外延层22内形成位于第一沟槽301之下的第二沟槽302，此时第二沟槽302的宽度小于第一沟槽301的宽度，第二沟槽302即为本发明的半导体功率器件的栅沟槽的下部。
接下来，如图6所示，进行倾斜的离子注入，在外延层22内形成第一导电类型的掺杂区25，第一导电类型的掺杂区25围绕第二沟槽302。优选的，第一导类型的掺杂区25与半导体衬底20连接。
接下来，如图7所示，在第二沟槽内形成场氧化层35和第二栅极26，第二栅极26可以向上延伸至第一沟槽内，第二栅极26通过场氧化层35与第一栅极24和外延层22隔离。
最后通过现有技术的制造工艺制备体区、源区和漏区即可，其中，漏区与第一导电类型的掺杂区25连接。
以上具体实施方式及实施例是对本发明提出的一种IGBT功率器件的技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。
尽管本发明的实施方案已公开如上，但其并不仅仅限于说明书和实施方式中所列运用，它完全可以被适用于各种适合本发明的领域，对于熟悉本领域的人员而言，可容易地实现另外的修改，因此在不背离权利要求及等同范围所限定的一般概念下，本发明并不限于特定的细节和这里示出与描述的图例。

Claims (7)

1.一种半导体功率器件，其特征在于，包括：
第一导电类型的漏区；
位于所述漏区之上的第二导电类型的外延层；
位于所述外延层内的交替排列的栅沟槽和第二导电类型的体区；
位于所述体区中的第一导电类型的源区；
位于所述栅沟槽的上部的第一栅极；
至少位于所述栅沟槽的下部的第二栅极；
所述第一栅极、所述第二栅极与所述外延层之间由绝缘介质层隔离；
位于所述外延层内的第一导电类型的掺杂区，所述掺杂区围绕所述栅沟槽的下部且与所述漏区连接。
2.如权利要求1所述的半导体功率器件，其特征在于，所述第二栅极从所述栅沟槽的下部向上延伸至所述栅沟槽的上部。
3.如权利要求1所述的半导体功率器件，其特征在于，所述栅沟槽的上部的宽度大于所述栅沟槽的下部的宽度。
4.如权利要求1所述的半导体功率器件，其特征在于，所述第一栅极接栅极电压，所述体区、所述源区与所述第二栅极均接源极电压。
5.如权利要求1所述的半导体功率器件，其特征在于，所述第一导电类型为n型，所述第二导电类型为p型。
6.一种半导体功率器件的制造方法，其特征在于，包括：
在第一导电类型的半导体衬底上形成第二导电类型的外延层；
在所述外延层内形成第一沟槽；
在所述第一沟槽内形成第一栅极；
在所述外延层内形成位于所述第一沟槽下方的第二沟槽；
进行离子注入，在所述外延层内形成围绕所述第二沟槽的第一导电类型的掺杂区；
至少在所述第二沟槽内形成第二栅极，其中，所述第一栅极、所述第二栅极和所述外延层相绝缘。
7.如权利要求6所述的半导体功率器件的制造方法，其特征在于，所述第二栅极从所述第二沟槽内向上延伸至所述第一沟槽内。
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