CN103094348A - 场效应晶体管 - Google Patents
场效应晶体管 Download PDFInfo
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Abstract
本发明涉及场效应晶体管。一种场效应晶体管包括:多个沟槽,延伸进第一导电类型的半导体区,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽;多个第二类型的体区域,每个所述多个第二类型的体区域设置在所述多个沟槽中各对相邻沟槽之间的所述半导体区中;绝缘材料,填充所述多个栅化沟槽和所述多个未栅化沟槽中的每个的底部;多个栅电极,每个所述栅电极设置在所述多个沟槽中的一个相应栅化沟槽中;以及所述第二导电类型的导电材料,设置在所述多个未栅化沟槽中的每个中,以便所述导电材料沿所述未栅化沟槽的侧壁接触与每个未栅化沟槽邻接的相应的体区域。
Description
本申请是申请号为200680020630.9,申请日为2006年6月8日,发明名称为“电荷平衡场效应晶体管”的分案申请。
相关申请的交叉引用
本申请要求于2005年6月10日提交的美国临时专利申请No.60/689,229的优先权,其全部内容结合于此作为参考。
本申请涉及于2004年12月29日提交的美国专利申请No.11/026,276,以及于2006年5月24日提交的美国专利申请No.11/441,386,这两个申请均结合于此作为参考。
背景技术
本发明涉及半导体功率器件技术,尤其涉及电荷平衡场效应晶体管及其制造方法。
用于高电流开关的器件结构已经由平面栅垂直DMOS发展到包括具有屏蔽电极的沟槽栅结构。早期的开发项目关注于减少特定导通状态电阻RSP。后来,诸如栅电荷(需要用来使器件导通或截止的电荷)的其它性能属性也被增加到开发目标中。最近,这些品质特征已经演变为取决于特定开关应用的特定唯一目标。
由于对MOSFET的开关速度的影响,特定的导通电阻和栅-漏电荷的乘积(RSP x QGD)被称作品质因素(figure-of-merit,FOM),用于在很多电子系统中普遍存在的同步降压变换器中的顶部开关。以类似的方式,根据取决于全部栅极电荷的FOM(RSP x QGD)来判定下侧MOSFET,其功率消耗取决于导电损耗。屏蔽栅结构可显著地提高这些品质因素。另外,通过增加屏蔽电极的深度,可以改善电荷平衡,这样允许高于给定漂移区域浓度平行平面击穿,从而减低RSP。
诸如用于低电压MOSFET的电荷平衡期间结构的应用已经证明是困难的,原因在于工艺和材料改变导致载流子类型的不平衡,反过来又造成降低的击穿电压。假设电荷平衡导致漂移区域内的平电场,可以显示出掺杂浓度N和漂移区域柱的宽度W的乘积必须小于半导体电容率和临界电场的乘积被电荷q除:
结果,较低的BVDSS目标需要较大的掺杂浓度,从而使得漂移区域柱的宽度必须降低以维持电荷平衡。例如,具有约2x1016cm-3漂移区域浓度的30V器件需要小于约1.4μm的平台宽度,用于理想的电荷平衡。然而,这一状况不能改善RSP,原因在于,2x1016cm-3能够支持30V,而没有电荷平衡。如果浓度加倍以降低漂移区域电阻,则所需要的平台宽度被减半至约0.7μm。考虑到所有必须满足单元结构的特征,例如,雪崩耐久性所需要的重体结,这样良好的尺寸难以实现。
在大多数电荷平衡结构中,漂移区域是重掺杂n型衬底上的n型区域。在一些变形中,沟槽侧壁用硼注入,以提供相反极性的电荷。对于低压器件,这些方法中的每种方法均经过处理改变,造成电荷不平衡和包括RSP、QGD、以及BVDSS的性能特征中的相对宽的分布。这些处理改变源于多个来源,包括外延层浓度、栅电极相对于p阱深度的深度、平台宽度、和屏蔽绝缘物厚度。
因此,存在着对改进的电荷平衡MOSFET单元结构和制造方法的需求。
发明内容
根据本发明的实施例,场效应晶体管通过如下形成。提供第一导电类型的半导体区,第二导电类型的外延层在半导体区之上延伸。形成延伸穿过外延层并在半导体区停止的沟槽。执行第一导电类型的掺杂物的双通道倾斜注入,从而沿沟道侧壁形成第一导电类型的区域。执行第二导电类型的掺杂物的阈值电压调节注入,从而将第一导电类型的区域沿沟槽的上侧壁延伸的部分的导电类型转变为第二导电类型。形成在沟槽的每侧的侧面的第一导电类型的源区。
根据本发明的另一实施例,MOSFET包括延伸进半导体区的沟槽和位于所述沟槽的下部的屏蔽电极。所述屏蔽电极通过屏蔽绝缘物与所述半导体区绝缘。栅电极位于所述沟槽的上部中,所述栅电极位于所述屏蔽电极之上,但与所述屏蔽电极绝缘。所述半导体区包括第一导电类型的衬底和在所述衬底之上的第二导电类型的第一硅区域。所述第一硅区域具有延伸至所述栅电极的顶面和底面的中间深度的第一部分。所述第一硅区域具有延伸至所述屏蔽电极的顶面和底面的中间深度的第二部分。所述半导体区还包括在所述沟槽和所述第一硅区域的所述第二部分之间的所述第一导电类型的第二硅区域。所述第二硅区域具有在远离所述沟槽的侧壁的方向上减少的横向阶梯掺杂浓度。所述半导体区还包括在所述第一硅区域中的所述第一导电类型的源区,所述源区与所述沟槽相邻。
根据本发明的另一实施例,通过如下形成FET。提供第一导电类型的衬底,第二导电类型的外延层在所述衬底之上延伸。执行第一硅蚀刻,以形成延伸进所述外延层并在所述外延层内停止的上沟槽部。形成沿所述上沟槽部的侧壁并在与所述上沟槽部相邻的平台之上延伸,但不沿所述上沟槽部的底面延伸的保护材料;执行第二硅蚀刻以形成从所述上沟槽部的所述底面延伸穿过所述外延层并在所述半导体区内停止的下沟槽部。所述下沟槽部比所述上沟槽部窄。执行所述第一导电类型的掺杂物的双通道倾斜注入,从而沿所述下沟槽部的侧壁形成第一导电类型的硅区域。所述保护材料阻止所述注入掺杂物进入所述上沟槽部的侧壁和与所述上沟槽部相邻的所述平台区域。
根据本发明的再一实施例,MOSFET包括延伸进半导体区的沟槽。沟槽具有下部和上部,所述下部比所述上部窄。所述MOSFET进一步包括屏蔽电极,位于所述沟槽的所述下部,所述屏蔽电极通过屏蔽绝缘物与所述半导体区绝缘。栅电极位于所述沟槽的所述上部,所述栅电极位于所述屏蔽电极之上并与所述屏蔽电极绝缘。所述半导体区包括第一导电类型的衬底和在所述衬底之上的第二导电类型的第一硅区域。所述第一硅区域具有延伸至所述栅电极的顶面和底面的中间深度的第一部分。所述第一硅区域具有延伸至所述屏蔽电极的顶面和底面的中间深度的第二部分。所述半导体区进一步包括在所述下沟槽部和所述第一硅区域的所述第二部分之间的所述第一导电类型的第二硅区域。所述第二硅区域具有在远离所述下沟槽部的侧壁的方向上减少的横向阶梯掺杂浓度。所述第一导电类型的源区位于所述第一硅区域中,所述源区与所述上沟槽部相邻。
根据本发明的再一实施例,如下形成MOSFET。提供第一导电类型的衬底,第一导电类型的外延层在所述衬底上延伸。执行第一硅蚀刻,以形成延伸进所述外延层并在所述外延层停止的上沟槽部。形成沿所述上沟槽部的侧壁并在与所述上沟槽部相邻的平台之上延伸,但不沿所述上沟槽部的底面延伸的保护材料。执行第二硅蚀刻,以形成从所述上沟槽部的所述底面延伸穿过所述外延层并在所述衬底内停止的下沟槽部,所述下沟槽部比所述上沟槽部窄。执行所述第一导电类型的掺杂物的双通道倾斜注入,从而沿所述下沟槽部的侧壁形成第一导电类型的硅区域,所述保护材料阻止所述注入掺杂物进入所述上沟槽部的侧壁和与所述上沟槽部相邻的所述平台区域。在所述下沟槽部的侧壁和底面形成屏蔽绝缘物。在所述下沟槽部中形成屏蔽电极。沿所述上沟槽部的侧壁形成栅绝缘层。在所述上沟槽中形成栅电极,位于所述屏蔽电极之上,但与所述屏蔽电极绝缘。
根据本发明的另一实施例,MOSFET包括延伸进半导体区的沟槽。沟槽,具有下部和上部,所述下部比所述上部窄。该MOSFET进一步包括屏蔽电极,位于所述沟槽的所述下部,所述屏蔽电极通过屏蔽绝缘物与所述半导体区绝缘。栅电极位于所述沟槽的所述上部,所述栅电极位于所述屏蔽电极之上但与所述屏蔽电极绝缘。所述半导体区包括:第一导电类型的衬底;在所述衬底之上的所述第一导电类型的外延层;以及在所述外延层中的第二导电类型的体区域。所述第一导电类型的源区在所述体区域中,所述源区和所述体区域和所述衬底之间的界面限定了沟槽区域。所述第一导电类型的硅区域,沿所述沟槽的所述底部的侧壁延伸,并延伸进所述沟槽区域的下部。所述硅区域具有在远离所述沟槽的侧壁的方向上减少的横向阶梯掺杂浓度。
根据本发明的另一实施例,MOSFET如下形成。提供第一导电类型的衬底,在所述衬底之上形成第一导电类型的外延层。形成延伸穿过所述外延层并在所述衬底中停止的栅沟槽。衬着每个栅沟槽的侧壁和底面形成屏蔽绝缘物;在栅沟槽中形成屏蔽电极。沿每个栅沟槽的上侧壁形成栅绝缘层。在栅沟槽中形成栅电极,所述栅电极在所述屏蔽电极之上但与所述屏蔽电极绝缘。形成延伸穿过所述外延层并在所述衬底内停止的深坑,所述深坑与所述栅沟槽横向隔离。用所述第二导电类型的硅材料填充所述深坑。
根据本发明的另一实施例,MOSFET包括第一导电类型的衬底和在所述衬底之上的所述第一导电类型的外延层。栅沟槽延伸穿过所述外延层并在所述衬底内停止。屏蔽绝缘物衬着所述栅沟槽的侧壁和底面(作为所述栅沟槽的侧壁和底面的衬层)。屏蔽电极位于所述栅沟槽的下部。栅绝缘层沿所述栅沟槽的上侧壁延伸。栅电极在所述栅沟槽中,所述栅电极在所述屏蔽电极之上但与所述屏蔽电极绝缘。深坑延伸穿过所述外延层并在所述衬底中停止,所述深坑与所述栅沟槽横向隔离。所述深坑以所述第二导电类型的硅材料填充。
根据本发明的另一实施例,MOSFET如下形成。提供第一导电类型的衬底。在所述衬底之上形成所述第一导电类型的外延层。形成延伸穿过所述外延层并在所述衬底中停止的多个栅沟槽。衬着每个栅沟槽的侧壁和底面形成屏蔽绝缘物。在每个栅沟槽中形成屏蔽电极。沿每个栅沟槽的上侧壁形成栅绝缘层。在每个栅沟槽中形成栅电极,所述栅电极在所述屏蔽电极之上但与所述屏蔽电极绝缘。执行到相邻的栅沟槽之间的平台区域中的所述第二导电类型的掺杂物的多次离子注入,从而形成延伸穿过所述外延层并在所述衬底内停止的多个第二导电类型的柱状物,每个第二导电类型的柱状物均位于每两个栅沟槽之间。
根据本发明的再一实施例,FET如下形成。在第一导电类型的半导体区中形成多个沟槽,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽。在相邻的沟槽之间的所述半导体中形成第二导电类型的体区域。用绝缘材料填充所述栅化沟槽和所述未栅化沟槽中的每个的底部。在所述绝缘材料之上的每个栅化沟槽中形成栅电极。在所述绝缘材料之上的每个未栅化沟槽中形成所述第二导电类型的导电材料,从而使得所述导电材料沿每个未栅化沟槽的侧壁接触所述体区域。
根据本发明的再一实施例,FET如下形成。在第一导电类型的半导体区中形成多个沟槽,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽。在每个栅化沟槽和未栅化沟槽的底部形成屏蔽电极。在相邻的沟槽之间的所述半导体区中形成第二导电类型的体区域。在每个未栅化沟槽中的屏蔽电极之上形成绝缘层。在所述绝缘层之上的每个未栅化沟槽中形成所述第二导电类型的导电材料,使得所述导电材料沿所述未栅化沟槽接触体区域。
根据本发明的再一实施例,FET如下形成。在第一导电类型的半导体区中形成多个沟槽,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽。在相邻的沟槽之间的所述半导体区中形成第二导电类型的体区域。在每个栅化沟槽的底部中形成屏蔽电极。在每个未栅化沟槽中形成屏蔽电极,每个未栅化沟槽中所述屏蔽电极具有在所述体区域的底面之上的顶面。在每个未栅化沟槽中形成所述第二导电类型的导电材料,使得所述导电材料沿所述未栅化沟槽的侧壁接触体区域,所述导电材料同样接触每个未栅化沟槽中的屏蔽电极。
根据本发明的另一实施例,FET如下形成。在第一导电类型的半导体区中形成多个沟槽,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽。在每个栅化沟槽和未栅化沟槽的底部中形成屏蔽电极。在相邻的沟槽之间的所述半导体区中形成第二导电类型的体区域。在每个未栅化沟槽中的所述屏蔽电极之上形成绝缘层。将所述第二导电类型的掺杂物双通道倾斜注入每个未栅化沟槽的上侧壁,从而在每个体区域中形成重体区。
根据本发明的另一实施例,FET如下形成。在第一导电类型的半导体区中形成多个沟槽,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽。在相邻的沟槽之间的所述半导体区中形成第二导电类型的体区域。用绝缘材料填充所述栅化沟槽和所述未栅化沟槽中的每个的底部。在每个栅化沟槽中的所述绝缘材料之上形成栅电极。将所述第二导电类型的掺杂物双通道倾斜注入每个未栅化沟槽的露出的上侧壁,从而在每个体区域中形成重体区。
以下的详细描述和附图提供对本发明的本质和优点的更好理解。
附图说明
图1A-1D是示出根据本发明的一个实施例的用于形成使用p型外延层的n沟道电荷平衡MOSFET的示范处理流程的简化横截面图;
图2A-2E是示出根据本发明的另一实施例的用于形成使用p型外延层的n沟道电荷平衡MOSFET的示范处理流程的简化横截面图;
图3A-3E是示出根据本发明的另一实施例的用于形成使用n型外延层的n沟道电荷平衡MOSFET的示范处理流程的简化横截面图;
图4是示出根据本发明的实施例的用于形成具有硅填充沟槽的电荷平衡MOSFET的简化示范横截面图;
图5A-5B是示出根据本发明的实施例的使用多重离子注入步骤形成电荷平衡MOSFET的示范处理流程的简化横截面图;
图6A-6G是示出根据本发明的实施例的用于形成具有在栅化沟槽之间集成由自调整未栅化沟槽的沟槽栅极FET的示范处理流程的简化横截面图;
图7A-7H是示出根据本发明的另一实施例的用于形成具有在栅化沟槽之间集成由自调整未栅化沟槽的屏蔽栅极FET的示范处理流程的简化横截面图;
图8A-8H是示出根据本发明的另一实施例的用于形成具有在栅化沟槽之间集成由自调整未栅化沟槽的屏蔽栅极FET的再一示范处理流程的简化横截面图;
图9是具有未栅化沟槽的屏蔽栅极FET的简化横截面图,其中,重体区形成在体区内,而非形成在未栅化沟槽内部;以及
图10是具有未栅化沟槽的沟槽栅极FET的简化横截面图,其中,重体区形成在体区内,而非形成在未栅化沟槽内部。
具体实施方式
根据本发明的实施例,在p型外延层而不是在传统的n型外延层中形成n沟道屏蔽栅极MOSFET,其特别用于低压应用,但非局限于此。这样提供了简化工艺的机会,例如,省略和形成p型体区域相关的处理步骤。
图1A-1D是示出根据本发明的一个实施例的用于形成电荷平衡MOSFET的处理顺序的简化横截面图。在图1A中,在硅衬底42之上形成p型外延层44(例如,通过硅的选择性外延生长)。在一个实施例中,起始晶圆材料包括衬底42及其覆盖p型外延层44。执行常规沟槽蚀刻,以形成延伸穿过外延层44并在衬底42中停止的沟槽46。接着可以执行可选的退火步骤,以修复损坏的硅并对沟槽的角进行倒圆。
在图1B中,使用已知技术执行双通道倾斜注入50,以沿沟槽侧壁和底部形成n型区域48。未示出的,防止平台区域接收注入的掺杂物。可以使用可选的扩散和驱动步骤,以驱使注入的离子更远地进入硅。在图1C中,使用常规技术,在沟槽46的下部形成屏蔽绝缘物53和屏蔽电极54。接着,在屏蔽电极54之上形成inter-poly绝缘(IPD)层56。使用已知方法,衬着上侧壁(作为上侧壁的衬层)形成栅绝缘层53,接着在IPD层56之上形成凹入栅电极58。
在图1D中,使用已知技术执行p型掺杂物的阈值电压(Vt)调节注入,以形成p型区域62。选择Vt注入的掺杂浓度,使得注入反向掺杂沿沟槽区域延伸的n型区域48的部分,在晶体管的沟槽区域获得想要的掺杂浓度。接着执行常规的源注入,以形成n+源区64。用于源扩散的热预算同样满足在Vt调节注入中的使用。接着,使用常规技术形成重体区域66。如图1D所示,p型外延层44的大部分仍然保持p掺杂。为了完成器件,诸如硼磷硅玻璃(BPSG)的绝缘层68被沉积并被图样化以覆盖沟槽46和源区64的一部分。源互连层70(例如包括金属)接着被形成在衬底上,以电接触源区64和重体区66。
在和上述步骤相关的热循环中,在n型区域48和衬底42中的n型掺杂物扩散。结果,在外扩散n型区域48的掺杂浓度在靠近沟槽处最大,在远离沟槽侧壁的方向上逐渐减小。类似地,掺杂物从衬底42到外延层44的扩散使得形成具有在从衬底42和外延层44之间的原始界面(如图1C和1D中的虚线示出)向顶面的方向上逐渐减少的掺杂浓度的阶梯n型区域。这样高效地向上移动了衬底42和外延层44之间的边界。
在图1D中,在晶体管之下延伸的n型区域48的部分连同直接和n型区域48相邻的p型外延层44的部分形成电荷平衡结构柱。正如从图1A-1D所示出的工艺,这些p型和n型电荷平衡结构柱被有利地以自调整方式形成。电荷平衡结构连同屏蔽栅极结构减少了栅漏电荷Qgd和导通电阻,并提高了击穿电压。使用简单的工艺(其中用于形成阱区(也被成为体区)的处理步骤被省略)实现了这些改进。在一个实施例中,多个区域的导电类型被反转,从而获得p沟道MOSFET。在一个实施例中,衬底42包括具有不同的掺杂浓度的相同导电类型的硅的多个层。
在图1A-1D实施例的一个变形例中,使用了非常轻微掺杂的p型外延层,接着,执行p型掺杂物的双通道倾斜注入,以沿沟槽侧壁形成p型区域。接着,执行n型掺杂物的双通道倾斜注入,以沿沟槽侧壁形成n型区域。可适当地选择掺杂浓度、注入能量和其它注入参数,以保证p型区域比n型区域横向延伸的更远,从而使得p型区域和n型区域形成电荷平衡结构的两个柱(column)。因此,由于使用注入步骤对电荷平衡结构中的p型和n型柱进行掺杂,所以可以消除任何由于外延层中的掺杂变化而导致的电荷不平衡。
因此,和常规技术相比,通过仔细地优化p型体和n型侧壁注入以及驱进条件,p体的电荷平衡和栅极覆盖被极大地增强。结果,实现了较低的特定导通状态电阻和更小的栅漏电荷。示范结构的模拟显示出,和常规的屏蔽栅结构相比,RSP至少降低10-20%,栅漏电荷降低一半。
在可选方法中,蚀刻中空沟槽,形成氧化层接着形成氮化层,以保护平台和沟槽侧壁免于后续的深沟槽蚀刻。将氮化物保留在中空沟槽的侧壁上,较深的沟槽侧壁被暴露以进行倾斜注入。这样限制了到外延区域的下部的注入和来自沟道区域的注入,允许p型外延层起到沟道的作用,起到深结的作用,以用于电荷平衡目的。在图2A-2D中示出用于获得这种结构的示范性处理流程。
在图2A中,在重掺杂n型衬底80之上形成p型外延层82(例如,通过硅的选择性外延生长)。接着蚀刻沟槽84至外延层82内的中间深度。第一绝缘层86(例如包括氧化物)接着被衬着沟槽84的侧壁和底部形成,并沿与沟槽84相邻的硅平台的顶部延伸。如所看到的,理想地形成第一绝缘层86,使得第一绝缘层86在硅平台上延伸的部分比第一绝缘层86在沟槽84内的部分厚。一种在平台区域上获得较厚的绝缘物的方法是以图13A-13L所述的类似方式(2006年5月24日提交的美国专利申请No.11/441,386,其全部内容结合于此作为参考)形成例如ONO的复合层。使用已知技术,第二绝缘层(例如包括氮化物)接着被形成在第一绝缘层86上,接着被蚀刻以形成绝缘物(例如氮化物)隔离物87。
在图2B中,绝缘层87起到保护隔离物的作用,第一绝缘层86的暴露部分被蚀刻,直到外延层82沿沟槽底部露出。假如第一绝缘层86被形成为在平台区域上的厚度比沿沟槽底部的厚度厚,在蚀刻后,平台表面保持由第一绝缘层(虽然较薄)覆盖。
在图2C中,执行另外的硅蚀刻,从而使得沟槽84的露出底面延伸完全穿过外延层82,进入衬底80,以形成较深的沟槽85。因此,沟槽85的下部比其上部窄。第一绝缘层86和绝缘隔离物87起到保护平台表面和上沟槽侧壁的作用,执行n型掺杂物的双通道倾斜注入83,以沿沟槽85的暴露的下侧壁形成n型硅区域88。如所示出的,n型层88与衬底80合并。绝缘隔离物87防止掺杂物进入沟槽区。
在图2E中,使用常规技术去除绝缘隔离物87和第一绝缘层86。接着使用常规技术,将屏蔽绝缘物89和屏蔽电极90形成在沟槽85的下部。使用已知方法将inter-poly绝缘(IPD)层92形成在屏蔽电极90之上。接着使用常规技术,将栅绝缘物96和栅电极94形成在IPD层92之上。使用已知技术形成源区93和重体区95。诸如BPSG的绝缘层97接着被沉积在结构的顶部之上,并被图样化以覆盖栅极94和源区93的一部分,接着,形成源互连层(未示出),以电接触源区93和重体区95。
可以执行和图2A-2E类似的处理,以在n型外延层而不是p型外延层中形成屏蔽栅结构。n型掺杂物的双通道倾斜注入迫使体扩散进入沟道区的底部,这有利地降低了沟道的电阻。这种注入还有助于降低在沟槽侧壁处看到的高电场。图3A-3E示出了用于形成这样的结构的示范性处理流程。在图3A中,使用例如选择性外延生长在n型衬底400上形成n型外延层402。用于形成图3E中的屏蔽栅结构的全部后续步骤与图2A-2E中的对应步骤类似,除了在图3中在形成源区413和重体区415之前,执行p型掺杂物的体注入以形成体区域418之外。如图3D和3E所示,通过双通道倾斜注入形成的硅区域408向上扩散进沟道区,因此降低沟道电阻。
根据本发明的另一实施例,使用n型外延层和用外延生长的p型硅填充的深坑形成的电荷平衡屏蔽栅MOSFET。这一实施例将使用图4中的示范性横截面示意图描述。在图4中,在每两个相邻的栅化沟槽131之间,深坑133延伸穿过体区136和n型外延层132,并在重掺杂n型衬底130中停止。坑133填充有p型硅材料134。n型外延层132的掺杂浓度和坑133中的硅材料134被选择以获得这两个区域之间的电荷平衡。另外,栅化沟槽结构与上述实施例中的结构类似,因此不再描述。
形成图4中的结构的示范方法如下。在重掺杂n型衬底130之上形成n型外延层132(例如,通过选择性外延生长)。通过将掺杂物注入外延层132来形成p型导电类型的体区域136。体区域136延伸至足以形成沟道区域的深度。执行后续硅蚀刻,以形成延伸穿过体区域136并在衬底130中停止深坑133。接着执行选择性外延生长处理,以用p型硅134填充深坑133。根据已知技术,形成栅沟槽131及其各种材料,以及源区140、重体区138和其它结构特征。在一个实施例中,在形成深坑之前形成栅沟槽和栅极及屏蔽电极。通过在衬底-外延层界面之下延伸坑133,可有利地减轻在柱的底部的高电场。这样允许较薄的n型外延层,进而降低导通状态电阻。
图5A和5B示出了用于形成图4中的深p-型区域134的可选方法。如图5A和5B所示,通过将p型掺杂物的多重高能注入物172注入穿过中空坑168,进入n型外延层162,形成p型柱164。正如所示出的,深坑比源区166稍微深些。坑深设置了p型柱164的参考点,原因在于注入物172进入了坑168的底面。注入物172的剂量和能量可被调节以在p型柱164中获得需要的掺杂特性(dopingprofile)。由于在处理结束时有非常少的扩散,所生成的p型柱164和n型外延层162两者的掺杂特性相对较平。这样就改善了处理的灵敏度。
根据本发明的其它实施例,用于电荷平衡MOSFET(尤其用于低压应用,但不限于此)的其它方法和结构使用栅极沟道之间的未栅化屏蔽沟槽。这些实施例将随后描述。
电荷平衡沟槽栅极FET依赖于平台宽度和漂移区域(通常是外延层)的掺杂浓度,以控制在高反转漏源电压之下的损耗,从而获得比常规沟槽栅极FET高的击穿电压。平台宽度由光刻技术的能力所限制,以在两个相邻的栅沟槽之间的平台的中央限定连续的重体接触区。然而,根据本发明的实施例,使用散布于栅沟槽之间的额外未栅化屏蔽沟槽能够降低相同击穿电压的漂移区域电阻,有效地减少期间的导通状态,并允许改善的电荷平衡特性。
图6A-6G是示出根据本发明的实施例的用于形成具有在栅化沟槽之间集成由自调整未栅化沟槽的沟槽栅极FET的示范处理流程的简化横截面图。在图6A中,使用常规技术,将沟槽202和204蚀刻进硅区域200。在一个实施例中,硅区域200包括重掺杂n型衬底和在衬底之上的n型外延层。
沟槽202被用来指示未栅化沟槽,沟槽204被用来指示栅化沟槽。使用已知技术形成绝缘层206(例如生长氧化物),在平台表面208上延伸并衬着沟槽202和204的侧壁和底面。在图6B中,使用常规方法沉积用来填充沟槽并在平台区域上延伸的绝缘材料210(例如,诸如SACVD的沉积膜)。在图6C中,使用已知技术,执行平坦化处理,以使绝缘材料210保留在沟槽中的顶面基本上与平台表面208齐平。
在图6D中,使用常规方法,掩模层(例如光刻胶)被沉积并被图样化,以形成用于覆盖未栅化沟槽202的掩模区域214,接着对栅化沟槽204的绝缘层206和绝缘材料210进行凹入处理,从而沿栅化沟槽204的底部形成厚底绝缘物(TBD)212。在图6E中,使用常规技术,去除掩模区域214,形成作为栅化沟槽204的侧壁的衬层并在平台表面和未栅化沟槽202之上延伸的栅绝缘层220(例如包括氧化物)。接着沉积多晶硅层,并将其凹进栅沟槽204,从而在栅化沟槽204中形成凹入的栅电极222。在器件的主动区执行常规的表层体和源注入,以顺序在硅区域200中形成p型体区域226,接着在体区域226中形成轻微掺杂的n型源区224。
在图6F中,使用已知技术,在衬底之上形成绝缘层(例如,包括BPSG),并接着对其图样化和蚀刻,以形成仅在栅沟槽204之上延伸的绝缘帽230。相同的绝缘蚀刻可被用来使绝缘材料206和210凹进未栅化沟槽202足够多,从而使得部分暴露体区域226的侧壁。绝缘区域252由此沿非栅化沟槽202的底部保留。
在图6G中,用导电材料(例如重掺杂p型多晶硅)填充未栅化沟槽202,以形成重体区234。接着在结构之上形成源互连层236(例如,包括金属),以接触源区224和重体区234。在一个实施例中,在形成重体区234的过程中,沉积的导电材料凹进未栅化沟槽202以部分暴露源区224的侧壁。这样能够使源互连层230直接接触源区224的侧壁,从而减少源接触电阻。
如所看到的,源区224与沟槽自调整(自对准)。在一个使用条状单元配置的实施例中,图6A至6G示出的处理顺序使得连续形成自调整的重体区234。所生成结构的这些和其他自调整特征允许非常紧的单元间距。同样,可去除在形成每个源区和重体区过程中通常需要的掩模步骤,从而降低了成本并使得生产复杂程度最小化。
在一个实施例中,在每两个栅化沟槽之间形成一个未栅化沟槽。在另一个实施例中,采用更大的未栅化沟槽与栅化沟槽之间的比率(例如,每两个栅化沟槽之间形成两个或更多个未栅化沟槽)。在另一实施例中,不是同时形成未栅化沟槽和栅化沟槽,而是在与栅化沟槽不同的处理阶段形成未栅化沟槽。然而,这就导致额外的处理步骤,这一实施例在优化处理和结构的各种特征方面提供了灵活性。
图7A-7H是示出根据本发明的另一实施例的用于形成具有在栅化沟槽之间集成由自调整未栅化沟槽的屏蔽栅极FET的示范处理流程的简化横截面图。在图7A中,栅化沟槽304和未栅化沟槽302被蚀刻进n型硅区域300。在一个实施例中,硅区域300包括重掺杂n型衬底和在衬底之上的n型外延层。在本实施例的一个变形例中,沟槽302和304在外延层内停止,在另一变型例中,沟槽320和304延伸穿过外延层并在衬底内停止。
在图7A中,使用已知技术,形成屏蔽绝缘层306(例如包括氧化物),在平台表面308上延伸并作为沟槽302和304的侧壁和底面的衬层。使用常规技术,沉积多晶硅层并接着深凹入沟槽302和304,从而在沟槽302和304中形成屏蔽电极310。在图7B中,使用常规方法,沉积填充沟槽并在平台区域上延伸的绝缘材料312(例如使用SACVD的沉积膜)。在图7C中,使用已知技术,执行平坦化处理,以使绝缘材料312保留在沟槽中的顶面基本上与平台表面308齐平。
在图7D中,使用常规方法,掩模层(例如光刻胶)被沉积并被图样化,以形成用于覆盖未栅化沟槽302的掩模区域314,接着使栅化沟槽304的绝缘层306和绝缘材料312凹入到预定深度,从而在屏蔽电极310之上形成电极间绝缘物316(IED)。在图7E中,使用常规技术,去除掩模区域314,形成作为栅化沟槽304的上侧壁的衬层并在平台表面和未栅化沟槽302之上延伸的栅绝缘层322(例如包括氧化物)。接着沉积多晶硅层,并将其凹进栅沟槽304,从而在栅化沟槽304中形成凹入的栅电极324。在图7F中,在器件的主动区执行常规的表层体和源注入,以在硅区域300中形成p型体区域328,接着在体区域328中形成重掺杂的n型源区326。
在图7G中,使用已知技术,在衬底之上形成绝缘层(例如,包括BPSG),并接着对其图样化和蚀刻,以形成在栅化沟槽304之上延伸的绝缘帽330。相同的绝缘蚀刻可被用来使绝缘材料306和310凹进未栅化沟槽302足够多,从而使得部分暴露体区域328的侧壁。绝缘区域325因此在非栅化沟槽302的屏蔽电极310之上保留。接着用导电材料(例如重掺杂p型多晶硅)填充未栅化沟槽302,以形成重体区332。接着在结构之上形成源互连层334(例如,包括金属),以接触源区326和重体区332。在一个实施例中,在形成重体区332的过程中,沉积的导电材料凹进未栅化沟槽302以部分暴露源区326的侧壁。这样能够使源互连层334直接接触源区326的侧壁,从而减少源接触电阻。
正如在上述实施例中,源区326与沟槽自调整。在一个使用条状单元配置的实施例中,图7A至7H示出的处理顺序使得连续形成自调整的重体区332。所生成结构的这些和其他自调整特征允许非常紧的单元间距。另外,在未栅化沟槽中的屏蔽电极够降低相同击穿电压的漂移区域电阻。另外,可去除在形成每个源区和重体区过程中通常需要的掩模步骤,从而降低了成本并使得生产复杂程度最小化。
栅化沟槽和未栅化沟槽中的屏蔽电极可被以第三尺寸电连接至源互连层,或者可被允许浮动。在一个实施例中,在每两个栅化沟槽之间形成一个未栅化沟槽。在另一个实施例中,采用更大的未栅化沟槽与栅化沟槽之间的比率(例如,每两个栅化沟槽之间形成两个或更多个未栅化沟槽)。在另一实施例中,不是同时形成未栅化沟槽和栅化沟槽,而是在与栅化沟槽不同的处理阶段形成未栅化沟槽。然而,这就导致额外的处理步骤,这一实施例在优化处理和结构的各种特征方面提供了灵活性。
图8A-8H是示出根据本发明的另一实施例的用于形成具有在栅化沟槽之间集成由自调整未栅化沟槽的屏蔽栅极FET的再一示范处理流程的简化横截面图。在图8A中,栅化沟槽404和未栅化沟槽402被蚀刻进n型硅区域400。在一个实施例中,硅区域400包括重掺杂n型衬底和在衬底之上的n型外延层。在本实施例的一个变形例中,沟槽402和404在外延层内停止。在本实施例的另一个变形例中,沟槽402和404延伸穿过外延层并在衬底内停止。
在图8A中,使用已知技术形成屏蔽绝缘层406(例如包括氧化物),在平台表面414上延伸并作为沟槽402和404的侧壁和底面的衬层。如所示出的,将多晶硅层沉积并回蚀刻至屏蔽绝缘层406的顶面稍微之下。在图8B中,使用常规方法,掩模层(例如光刻胶)被沉积并被图样化,以形成用于覆盖未栅化沟槽402的掩模区域412。在图8C中,将栅沟槽404中的多晶硅410接着深凹入沟槽,从而在栅化沟槽404中形成屏蔽电极410。如所示出的,去除掩模区域412,接着回蚀刻屏蔽绝缘层406。
在图8D中,使用常规技术生长栅极绝缘层420(例如包括氧化物),作为栅化沟槽404的侧壁和底面的衬层,并在屏蔽电极410、平台表面和未栅化沟槽402之上延伸。接着沉积多晶硅层并将其凹入栅化沟槽404,以在栅化沟槽404中形成凹入的栅电极418。在图8E中,在器件的主动区执行常规的表层体和源注入,以在硅区域400中形成p型体区域424,接着在体区域424中形成轻微掺杂的n型源区域422。
在图8F中,使用已知技术,在衬底之上形成绝缘层(例如,包括BPSG),并接着对其图样化和蚀刻,以形成在栅化沟槽404之上延伸的绝缘帽426。相同的绝缘蚀刻可被用来使屏蔽绝缘物406凹进未栅化沟槽402足够多,从而使得部分暴露体区域424的侧壁。在图8G中,沉积导电材料(例如重掺杂p型多晶硅)填充未栅化沟槽402,从而在未栅化沟槽402中形成重体区430。在图8H中,在结构之上形成源互连层432(例如,包括金属),以接触源区422和重体区430。
如所看到的,源区422与沟槽自调整。在一个使用条状单元配置的实施例中,图8A至8H示出的处理顺序使得连续形成自调整的重体区430。所生成结构的这些和其他自调整特征允许非常紧的单元间距。另外,在未栅化沟槽中的屏蔽电极够降低漂移区域电阻,而不降低击穿电压。另外,可去除在形成每个源区和重体区过程中通常需要的掩模步骤,从而降低了成本并使得生产复杂程度最小化。
如所看到的,未栅化沟槽402中的屏蔽电极408经由重体区430电连接至源互连432。在一个实施例中,在每两个栅化沟槽之间形成一个未栅化沟槽。在另一个实施例中,采用更大的未栅化沟槽与栅化沟槽之间的比率(例如,每两个栅化沟槽之间形成两个或更多个未栅化沟槽)。在另一实施例中,不是同时形成未栅化沟槽和栅化沟槽,而是在与栅化沟槽不同的处理阶段形成未栅化沟槽。然而,这就导致额外的处理步骤,这一实施例在优化处理和结构的各种特征方面提供了灵活性。
图9是具有未栅化沟槽的屏蔽栅极FET的简化横截面图,其中,重体区形成在体区内,而非形成在未栅化沟槽内部。图9中的屏蔽栅极FET结构与图7H中的结构类似,除了重体区520形成在体区516中,以及源互连层518延伸进并填充未栅化沟槽502的上部。如所示出的,源互连层沿着平台表面和源区的侧壁电接触源区514,并沿着它们的侧壁接触重体区520。图9中的FET的其它结构特征与图7H中的类似,不再描述。
用于形成图9中的FET结构的处理流程与图7A-7H类似,除了下述改变之外。在图7G中,在将绝缘材料306和310凹进未栅化沟槽302从而部分暴露体区328的侧壁之后,将p类型的掺杂物的双通道倾斜注入未栅化沟槽302的暴露的侧壁,以在体区域中形成重体区520(图9)。在一个实施例中,在执行双通道倾斜注入的过程中没有使用掩模,重体注入剂量被选择为低于源区的剂量,使得在未栅化沟槽的附近的源区的有效掺杂浓度不受任意方式的重体注入的影响。
在图7H中,在将源互连层沉积在衬底之上时,源互连层填充未栅化沟槽,从而沿其侧壁电接触重体区和源区,如图9所示。图9的实施例具有与如上述图7H所示的实施例的相同特征和优点。同样,上述的图7A至7H实施例的可选变形例和实施例同样适用于图9的FET结构。
图10是具有未栅化沟槽的沟槽栅极FET的简化横截面图,其中,重体区形成在体区内,而非形成在未栅化沟槽内部。图10中的沟槽栅极FET结构与图6G中的结构类似,除了重体区620形成在体区618中,以及源互连层622延伸进并填充未栅化沟槽602的上部之外。如所示出的,源互连层沿着平台表面和源区的侧壁电接触源区514,并沿着它们的侧壁接触重体区520。图10中的FET的其它结构特征与图6G中的类似,不再描述
用于形成图10中的FET结构的处理流程与图6A-6G类似,除了下述改变之外。在图6F中,在将绝缘材料206和210凹进未栅化沟槽202从而部分暴露体区226的侧壁之后,执行p类型的掺杂物的双通道倾斜注入未栅化沟槽202的暴露的侧壁,以在体区域中形成重体区620(图10)。在一个实施例中,在执行双通道倾斜注入的过程中没有使用掩模,重体注入剂量被选择为低于源区的剂量,使得在未栅化沟槽的附近的源区的有效掺杂浓度不受任意方式的重体注入的影响。
在图6G中,在将源互连层沉积在衬底之上时,源互连层填充未栅化沟槽,从而沿其侧壁电接触重体区和源区,如图10所示。图10的实施例具有与如上述图6G所示的实施例的相同特征和优点。同样,上述的图6A至6G实施例的可选变形例和实施例同样适用于图10的FET结构。
本发明的各种结构和方法可与一个或多个多个电荷平衡和屏蔽栅极技术(例如,图2A-2B、3A-3B、4A-4E、5B-5C、6-8、9A-9C、10-24所示出的)以及在2004年12月29日提交的美国专利申请No.11/026,276(其全部内容结合于此作为参考)中披露的其它器件结构和制造工艺结合,以实现其它优点和特征中的相当低的导通电阻,较高的阻挡能力和高效率。另外,一个或多个多种屏蔽栅结构(例如图4至7所示出的)和形成它们的方法(如2006年5月24日提交的美国专利申请No.11/441,386所披露的)可有利地与本说明书所披露的一个或多个电荷平衡技术(例如图3A-3E、4、5A-5B、7A-7H、8A-8H、9-10)结合,以获得具有优化的性能和结构特征的电荷平衡屏蔽栅器件。
本文所描述的不同实施例的横截面不是按照比例的,不能理解为构成对相应的结构的布图设计的可能变化的限制。
尽管以上示出并描述了多个特定实施例,但本发明的实施例并非限定性的。例如,尽管上述的多个实施例应用于常规硅,但是这些实施例及其显然的变形例同样可应用于碳化硅、砷化镓、氮化镓或其它半导体材料。作为另一个例子,尽管上述实施例在n沟道晶体管的环境中被描述,然而,通过简单的反转多个区域的导电类型,可以形成p沟道的反向晶体管。另外,本文描述的各种晶体管在以开放或封闭单元结构形成,包括六边形、椭圆形、或方形单元。另外,本发明的实施例并不限于MOSFET。例如,对于本领域技术人员而言,在考虑到本文的情况下,进行必要改变以形成上述MOSFET的IGBT对应部分是显而易见的。另外,尽管本文所描述的一些实施例对与低压应用尤其有用,但是,在考虑到本文的情况下,本领域技术人员可对上述的处理流程和结构进行改变,以形成适用于高压应用的晶体管,并具有很多和本发明相同的优点和特征。另外,本发明的一个或多个实施例的特征可与本发明的其它实施例的一个或多个特征结合,而不脱离本发明的范围。
因此,本发明的范围并不由上述描述所确定,而是参照所附的权利要求书及其所有的等同物所确定。
Claims (48)
1.一种场效应晶体管(FET),包括:
多个沟槽,延伸进第一导电类型的半导体区,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽;
多个第二类型的体区域,每个所述多个第二类型的体区域设置在所述多个沟槽中各对相邻沟槽之间的所述半导体区中;
绝缘材料,填充所述多个栅化沟槽和所述多个未栅化沟槽中的每个的底部;
多个栅电极,每个所述栅电极设置在所述多个沟槽中的一个相应栅化沟槽中;以及
所述第二导电类型的导电材料,设置在所述多个未栅化沟槽中的每个中,以便所述导电材料沿所述未栅化沟槽的侧壁接触与每个未栅化沟槽邻接的相应的体区域。
2.根据权利要求1所述的FET,进一步包括:
所述第一导电类型的多个源区,每个所述源区设置在所述多个体区域中的各个中,其中,设置在所述多个未栅化沟槽中的每个中的所述导电材料沿所述未栅化沟槽的侧壁接触与每个未栅化沟槽邻接的源区;以及
源互连层,接触所述多个源区中的每个和设置在所述多个未栅化沟槽中的每个中的所述导电材料。
3.根据权利要求1所述的FET,其中,填充所述多个未栅化沟槽中的每个的底部的所述绝缘材料具有位于与所未栅化沟槽邻接的所述体区域的底面之上的每个未栅化沟槽的顶面。
4.根据权利要求3所述的FET,其中,设置在所述多个体区域中的各个中的每个源区延伸穿过各平台区域的整个宽度,所述平台区域通过各对相邻的沟槽沿其横向尺寸限制。
5.根据权利要求1所述的FET,其中,所述半导体区包括重掺杂衬底和覆盖外延层,所述多个体区域形成在所述覆盖外延层的上部中。
6.根据权利要求1所述的FET,其中,设置在所述多个未栅化沟槽中的每个中的所述导电材料包括所述第二导电类型的多晶硅。
7.根据权利要求1所述的FET,其中,所述多个未栅化沟槽中的一个被设置在所述多个栅化沟槽中每对相邻的栅化沟槽之间。
8.根据权利要求1所述的FET,其中,所述未栅化沟槽中的两个或更多个形成在所述多个栅化沟槽中的每对相邻的栅化沟槽之间。
9.一种场效应晶体管(FET),包括:
多个沟槽,延伸进第一导电类型的半导体区,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽;
多个第二类型的体区域,每个所述多个第二类型的体区域设置在所述多个沟槽中各对相邻沟槽之间的所述半导体区中;
多个屏蔽电极,所述多个屏蔽电极中的一个设置在所述多个栅化沟槽和所述多个未栅化沟槽中每个的底部;
绝缘层,设置在设置于每个未栅化沟槽中的所述屏蔽电极之上;以及
所述第二导电类型的导电材料,设置在所述绝缘层之上的所述多个未栅化沟槽中的每个中,以便所述导电材料沿所述未栅化沟槽的侧壁接触与每个未栅化沟槽邻接的所述体区域。
10.根据权利要求9所述的FET,进一步包括:
多个所述第一导电类型的源区,所述多个所述第一导电类型的源区中的一个设置在所述多个体区域中的每个中,所述多个体区域中的每个设置在所述多个沟槽中各对相邻沟槽之间的半导体区中,
其中,设置在所述多个未栅化沟槽中的每个中的所述导电材料沿所述未栅化沟槽的侧壁接触与每个未栅化沟槽邻接的源区;以及
源互连层,接触所述源区和所述导电材料。
11.根据权利要求10所述的FET,其中,所述多个源区中的每个源区延伸穿过各平台区域的整个宽度,所述平台区域通过一对相邻的沟槽沿其横向尺寸限制。
12.根据权利要求10所述的FET,其中,所述多个屏蔽电极电连接至所述源互连层,其中,所述多个屏蔽电极中的一个设置在所述多个栅化沟槽和所述多个未栅化沟槽中的每个的底部中。
13.根据权利要求9所述的FET,进一步包括:
屏蔽绝缘层,衬着所述多个栅化沟槽和所述多个未栅化沟槽中的每个的下侧壁和底面;
电极间绝缘层,在所述多个栅化沟槽中设置的所述屏蔽电极之上延伸;以及
多个栅电极,所述多个栅电极中的一个位于所述多个栅化沟槽中的每个的所述电极间绝缘层之上。
14.根据权利要求9所述的FET,其中,设置在所述多个未栅化沟槽中的一个中的所述导电材料延伸至比与所述未栅化沟槽邻接的所述体区域的深度浅的深度。
15.根据权利要求9所述的FET,其中,所述半导体区包括重掺杂衬底和覆盖外延层,以及所述多个体区域被形成在所覆盖述外延层的上部,其中,所述多个栅化沟槽和未栅化沟槽在所述高掺杂衬底中停止。
16.根据权利要求9所述的FET,其中,所述半导体区包括重掺杂衬底和覆盖外延层,以及所述多个体区域被形成在所述覆盖外延层的上部,其中,所述多个栅化沟槽和未栅化沟槽在所述覆盖外延层中停止。
17.根据权利要求9所述的FET,其中,设置在所述多个未栅化沟槽中的每个的所述导电材料包括所述第二导电类型的多晶硅层。
18.根据权利要求9所述的FET,其中,所述多个未栅化沟槽中的一个设置在所述多个栅化沟槽中每对相邻的栅化沟槽之间。
19.根据权利要求9所述的FET,其中,所述多个未栅化沟槽中的两个或更多个形成在所述多个栅化沟槽中的每对相邻的栅化沟槽之间。
20.一种场效应晶体管(FET),包括:
多个沟槽,延伸进第一导电类型的半导体区,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽;
多个第二类型的体区域,所述多个第二类型的体区域中的每个设置在所述多个沟槽中的各对相邻沟槽之间的所述半导体区中;
多个屏蔽电极,所述多个屏蔽电极中的一个设置在所述多个栅化沟槽和所述多个未栅化沟槽中每个的底部,每个未栅化沟槽中的所述屏蔽电极具有在邻接体区域的底面之上的顶面;以及
所述第二导电类型的导电材料,设置在所述多个未栅化沟槽的每个中,以便所述导电材料沿所述未栅化沟槽的侧壁接触与每个未栅化沟槽邻接的体区域,所述导电材料同样与设置在每个未栅化沟槽中的所述屏蔽电极接触。
21.根据权利要求20所述的FET,进一步包括:
多个所述第一导电类型的源区,所述多个第一导电类型的源区中的每个设置在所述多个体区域中的各个中,其中,设置在所述多个未栅化沟槽中的每个中的所述导电材料沿所述未栅化沟槽的侧壁接触与每个未栅化沟槽邻接的源区;以及
源互连层,接触设置在所述多个未栅化沟槽中的每个中的所述导电材料和所述多个源区中的每个。
22.根据权利要求21述的FET,其中,所述多个源区中的每个源区延伸穿过各平台区域的整个宽度,所述平台区域通过各对相邻的沟槽沿其横向尺寸限制。
23.根据权利要求22所述的FET,其中,所述多个屏蔽电极电连接至所述源互连层,所述多个屏蔽电极中的一个设置在所述多个栅化沟槽和所述多个未栅化沟槽中的每个的底部。
24.根据权利要求20所述的FET,进一步包括:
屏蔽绝缘层,衬着所述多个栅化沟槽中的每个的下侧壁和底面;
栅绝缘层,衬着每个栅化沟槽的上侧壁,并在每个栅化沟槽中的所述屏蔽电极之上延伸;以及
栅电极,位于每个栅化沟槽中的所述栅绝缘层之上。
25.根据权利要求20所述的FET,其中,所述多个未栅化沟槽中的一个中设置的所述导电材料延伸至比与所述未栅化沟槽邻接的所述体区域的深度浅的深度。
26.根据权利要求20所述的FET,其中,所述半导体区包括重掺杂衬底和覆盖外延层,以及所述多个体区域被形成在所述覆盖外延层的上部,其中,所述多个栅化沟槽和未栅化沟槽在所述覆盖外延层中停止。
27.根据权利要求20所述的FET,其中,所述半导体区包括重掺杂衬底和覆盖外延层,以及所述多个体区域被形成在所述覆盖外延层的上部,其中,所述多个栅化沟槽和未栅化沟槽在所述覆盖外延层中停止。
28.根据权利要求20所述的FET,其中,设置在所述多个未栅化沟槽中的每个中的所述导电材料包括所述第二导电类型的多晶硅层。
29.根据权利要求20所述的FET,其中,所述多个未栅化沟槽中的一个设置在所述多个栅化沟槽中的每对相邻的栅化沟槽之间。
30.根据权利要求20所述的FET,其中,所述多个未栅化沟槽中的两个或更多个形成在所述多个栅化沟槽中的每对相邻的栅化沟槽之间。
31.一种场效应晶体管(FET),包括:
多个沟槽,延伸进第一导电类型的半导体区中,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽;
多个屏蔽电极,所述多个屏蔽电极中的一个设置在所述多个栅化沟槽和所述多个未栅化沟槽中的每个的底部;
绝缘层,设置在设置于每个未栅化沟槽中的所述屏蔽电极之上;以及
多个第二导电类型的体区域,所述多个第二导电类型的体区域中的每个设置在所述多个沟槽中的各对相邻沟槽之间的所述半导体区内,所述多个第二导电类型的体区域中的每个包括:
重体区,每个重体区均与各未栅化沟槽的侧壁相邻。
32.根据权利要求31所述的FET,进一步包括:
多个所述第一导电类型的源区,所述多个所述第一导电类型的源区中的每个设置在所述多个体区域中的各个中;以及
源互连层,接触所述多个源区中的每个的上表面,所述源互连层填充所述多个未栅化沟槽中的每个的上部,并沿着每个未栅化沟槽的上侧壁接触各源区和重体区。
33.根据权利要求32所述的FET,其中,所述多个源区中的每个源区延伸穿过各平台区域的整个宽度,所述平台区域通过各对相邻的沟槽沿其横向尺寸限制。
34.根据权利要求32所述的FET,其中,所述多个屏蔽电极电连接至所述源互连层,所述多个屏蔽电极中的一个设置在所述多个栅化沟槽和所述多个未栅化沟槽中的每个的底部。
35.根据权利要求32所述的FET,其中,所述源互连层延伸进每个未栅化沟槽至比各邻接体区域的深度浅的深度。
36.根据权利要求31所述的FET,进一步包括:
屏蔽绝缘层,衬着所述多个栅化沟槽和所述多个未栅化沟槽中的每个的下侧壁和底面;
电极间绝缘层,在设置于所述多个栅化沟槽中的所述屏蔽电极之上延伸;以及
多个栅电极,所述多个栅电极中的一个设置在所述多个栅化沟槽中的每个中的所述电极间绝缘层之上。
37.根据权利要求31所述的FET,其中,所述半导体区包括重掺杂衬底和覆盖外延层,所述多个体区域形成在所述覆盖外延层的上部,其中,所述多个所述栅化沟槽和未栅化沟槽在所述覆盖外延层中停止。
38.根据权利要求31所述的FET,其中,所述半导体区包括重掺杂衬底和覆盖外延层,所述多个体区域形成在所述覆盖外延层的上部中,其中,所述多个所述栅化沟槽和未栅化沟槽在所述覆盖外延层中停止。
39.根据权利要求31所述的FET,其中,所述多个未栅化沟槽中的一个设置在所述多个栅化沟槽中每对相邻的栅化沟槽之间。
40.根据权利要求31所述的FET,其中,所述多个未栅化沟槽中的两个或更多个形成在所述多个栅化沟槽中每对相邻的栅化沟槽之间。
41.一种场效应晶体管(FET),包括:
多个沟槽,延伸进第一导电类型的半导体区,所述多个沟槽包括多个栅化沟槽和多个未栅化沟槽;
多个第二导电类型的体区域,所述多个第二导电类型的体区域中的每个设置在所述多个沟槽中的各对相邻的沟槽之间的所述半导体区中,所述多个第二导电类型的体区域中的每个包括重体区,每个所述重体区与各未栅化沟槽的侧壁相邻;
绝缘材料,填充所述多个栅化沟槽和所述多个未栅化沟槽中的每个的底部;以及
在每个栅化沟槽中的所述绝缘材料之上的栅电极。
42.根据权利要求41所述的FET,进一步包括:
多个所述第一导电类型的源区,每个所述多个所述第一导电类型的源区设置在所述多个体区域中的各个中;以及
源互连层,接触所述多个源区中的每个的上表面,所述源互连层填充所述多个未栅化沟槽中每个的上部,并沿着每个未栅化沟槽的上侧壁接触各个源区和重体区。
43.根据权利要求42所述的FET,其中,所述多个源区中的每个源区延伸穿过各平台区域的整个宽度,所述平台区域通过各对相邻的沟槽沿其横向尺寸限制。
44.根据权利要求42所述的FET,其中,所述源互连层延伸进每个未栅化沟槽直至比所述体区域的深度浅的深度。
45.根据权利要求41所述的FET,其中,填充所述多个未栅化沟槽中的每个的底部的所述绝缘材料在每个未栅化沟槽中具有位于与所述未栅化沟槽邻接的所述体区域的底面之上的顶面。
46.根据权利要求41所述的FET,其中,所述半导体区包括重掺杂衬底和覆盖外延层,所述多个体区域形成在所述覆盖外延层的上部中。
47.根据权利要求41所述的FET,其中,所述多个未栅化沟槽中的一个被设置在所述多个栅化沟槽中的每对相邻的栅化沟槽之间。
48.根据权利要求41所述的FET,其中,所述多个未栅化沟槽中的两个或更多个形成在所述多个栅化沟槽中每对相邻的栅化沟槽之间。
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US20080258213A1 (en) | 2008-10-23 |
US8742401B2 (en) | 2014-06-03 |
DE112006001516T5 (de) | 2008-04-17 |
US7625799B2 (en) | 2009-12-01 |
US8278705B2 (en) | 2012-10-02 |
TW200705680A (en) | 2007-02-01 |
US20100038708A1 (en) | 2010-02-18 |
US20110303975A1 (en) | 2011-12-15 |
US7767524B2 (en) | 2010-08-03 |
TWI416741B (zh) | 2013-11-21 |
US7393749B2 (en) | 2008-07-01 |
US7955920B2 (en) | 2011-06-07 |
KR101296922B1 (ko) | 2013-08-14 |
CN101536163B (zh) | 2013-03-06 |
US20060281249A1 (en) | 2006-12-14 |
US20140054691A1 (en) | 2014-02-27 |
AT504290A2 (de) | 2008-04-15 |
US20130181282A1 (en) | 2013-07-18 |
KR20080032080A (ko) | 2008-04-14 |
JP2008546216A (ja) | 2008-12-18 |
KR101296984B1 (ko) | 2013-08-14 |
US20100258855A1 (en) | 2010-10-14 |
WO2006135746A2 (en) | 2006-12-21 |
TW201330286A (zh) | 2013-07-16 |
KR20120123159A (ko) | 2012-11-07 |
WO2006135746A3 (en) | 2009-04-30 |
US7514322B2 (en) | 2009-04-07 |
CN101536163A (zh) | 2009-09-16 |
CN103094348B (zh) | 2016-08-10 |
US20090191678A1 (en) | 2009-07-30 |
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US8592895B2 (en) | 2013-11-26 |
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