CN108269763B - 半导体元件的制作方法 - Google Patents

半导体元件的制作方法 Download PDF

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CN108269763B
CN108269763B CN201611258719.0A CN201611258719A CN108269763B CN 108269763 B CN108269763 B CN 108269763B CN 201611258719 A CN201611258719 A CN 201611258719A CN 108269763 B CN108269763 B CN 108269763B
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substrate
trench
doped region
gate electrode
forming
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CN108269763A (zh
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林哲平
王永铭
詹电鍼
詹书俨
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种半导体元件的制作方法。首先提供一基底，该基底上具有一存储区，然后形成一沟槽于基底内，进行一第一离子注入制作工艺以形成一第一掺杂区具有第一导电型式于基底内且位于该沟槽旁，形成一栅极电极于沟槽内，以及进行一第二离子注入制作工艺以形成一第二掺杂区具有第二导电型式于基底内并位于栅极电极上。

Description

半导体元件的制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作动态随机存取存储器单元的方法。
背景技术
随着各种电子产品朝小型化发展的趋势，动态随机存取存储器(Dynamic RandomAccess Memory,DRAM)单元的设计也必须符合高集成度及高密度的要求。对于一具备凹入式栅极结构的DRAM单元而言，由于其可以在相同的半导体基底内获得更长的载流子通道长度，以减少电容结构的漏电情形产生，因此在目前主流发展趋势下，其已逐渐取代仅具备平面栅极结构的DRAM单元。
一般来说，具备凹入式栅极结构的DRAM单元会包含一晶体管元件与一电荷贮存装置，以接收来自于位线及字符线的电压信号。然而，受限于制作工艺技术之故，现有具备凹入式栅极结构的DRAM单元仍存在有许多缺陷，还待进一步改良并有效提升相关存储器元件的效能及可靠度。
发明内容
本发明较佳实施例公开一种制作半导体元件的方法。首先提供一基底，该基底上具有一存储区，然后形成一沟槽于基底内，进行一第一离子注入制作工艺以形成一第一掺杂区具有第一导电型式于基底内且位于该沟槽旁，形成一栅极电极于沟槽内，以及进行一第二离子注入制作工艺以形成一第二掺杂区具有第二导电型式于基底内并位于栅极电极上。
附图说明
图1至图6为本发明较佳实施例制作一随机动态处理存储器元件的方法示意图。
主要元件符号说明
10 动态随机存取存储器元件 12 位线
14 字符线 16 基底
18 主动区 20 存储区(存储器区)
22 栅极 24 浅沟绝缘
26 阱区 28 沟槽
30 掺杂区 32 栅极电极
34 导电层 36 金属层
38 掺杂区 40 硬掩模
42 绝缘层 44 轻掺杂漏极
46 离子注入制作工艺 48 离子注入制作工艺
具体实施方式
请参照图1至图6，图1至图6为本发明较佳实施例制作一随机动态处理存储器元件的方法示意图，其中图1为俯视图，图2至图6则显示图1中沿着切线A-A’的剖视图。本实施例是提供一存储器元件，例如是具备凹入式栅极的随机动态处理存储器(dynamic randomaccess memory,DRAM)元件10，其包含有至少一晶体管元件(图未示)以及至少一电容结构(图未示)，以作为DRAM阵列中的最小组成单元并接收来自于位线12及字符线14的电压信号。
如图1所示，动态随机存取存储器元件10包含一基底16，例如一由硅所构成的半导体基底，然后于基底16内形成有至少一浅沟绝缘24，以于基底16上定义出多个主动区(active area,AA)18。此外，基底16上还定义有一存储区20以及一周边区(图未示)。其中，动态随机存取存储器元件10的多个字符线(word line,WL)14与多个位线(bit line,BL)12较佳形成于存储区20的基底16上而其他的主动元件等(未绘示)则可形成在周边区。需注意的是，为简化说明，本发明的图1仅绘示出位于存储区20的元件上视图并省略了位于周边区的元件。
在本实施例中，各主动区18例如是相互平行地朝向一第一方向延伸，而字符线14或多条栅极22是形成在基底16内并穿越各主动区18及浅沟绝缘24。具体来说，各栅极22是沿着不同于第一方向的一第二方向延伸，且第二方向与第一方向相交并小于90度。
另一方面，位线12是相互平行地形成在基底16上沿着一第三方向延伸，并同样横跨各主动区18及浅沟绝缘24。其中，第三方向同样是不同于第一方向，并且较佳是与第二方向垂直。也就是说，第一方向、第二方向及第三方向彼此皆不同，且第一方向与第二方向及第三方向皆不垂直。此外，字符线14两侧的主动区18内较佳设有接触插塞，例如包括位线接触插塞(bit line contact,BLC)(图未示)来电连接至各晶体管元件的源极/漏极区域(图未示)以及存储节点(storage node)接触插塞(图未示)来电连接一电容。
以下针对字符线14(或又称埋藏式字符线)的制作进行说明。如图2所示，
首先形成一较佳由氧化硅所构成的绝缘层42于基底16表面，然后再形成浅沟隔离24于基底16内并由此定义出存储区18。接着进行一离子注入制作工艺，将第一导电型式的离子，例如P型离子注入基底16内形成一阱区26，其中所注入的P型离子可包含例如硼，但不局限于此。在本实施例中，若选择注入的离子为硼，其所注入的能量约介于30KeV至200KeV且其剂量约5E12至1E14离子/平方厘米。
随后进行另一离子注入制作工艺，将第二导电型式离子，例如N型离子注入阱区26上方的基底16内以形成轻掺杂漏极44，其中N型离子可包含例如磷、砷等离子或其组合，但不局限于此。在本实施例中，若选择注入的离子为磷，其所注入的能量约介于5KeV至35KeV且其剂量约2E12至8E13离子/平方厘米。若选择注入的离子为砷，其所注入的能量约介于5KeV至25KeV且其剂量约5E12至1E14离子/平方厘米。
接着于形成轻掺杂漏极44后形成至少一沟槽28于存储区20的基底16内。在本实施例中，形成沟槽28的方式可先形成一图案化掩模(图未示)，例如一图案化光致抗蚀剂于基底16上，然后利用图案化掩模为掩模进行一蚀刻制作工艺，去除未被图案化掩模所遮蔽的部分基底16以形成多个穿过轻掺杂漏极44并暴露出基底16的沟槽28。需注意的是，本实施例虽较佳先形成绝缘层42于基底16后才形成多个沟槽28，但不局限于此，又可在不形成任何绝缘层42的情况下直接以光刻暨蚀刻方式去除部分基底16来形成多个沟槽28，此实施例也属本发明所涵盖的范围。
如图3所示，然后进行一离子注入制作工艺46，将第一导电型式的离子或与轻掺杂漏极44具有相反导电型式的离子，例如P型离子注入沟槽28两侧的基底16内以及沟槽28正下方的基底16内以形成一掺杂区30。从细部来看，所形成的掺杂区30较佳具有约略U型的剖面环绕沟槽28，且掺杂区30上表面较佳切齐绝缘层42上表面。在本实施例中，所注入的P型离子可包含例如硼、铟、镓等离子或其组合，其中注入离子的能量约介于0.2KeV至20KeV且其剂量约3E12至1E14离子/平方厘米。
随后如图4所示，形成一埋入式栅极于各沟槽28内。在本实施例中，形成埋入式栅极的方式可先利用现场蒸气成长(in-situ steam generation,ISSG)制作工艺形成一由氧化硅所构成的栅极介电层(图未示)于沟槽28内。然后形成栅极电极32于栅极介电层上，例如可依序形成一导电层34于栅极介电层表面以及一金属层36于导电层34上，接着再以蚀刻方式去除部分金属层36与部分导电层34，以于沟槽28中形成一栅极电极32，其中栅极电极32中所剩余的金属层36上表面在此阶段较佳切齐导电层34表面，且金属层36与导电层34上表面又较佳高于轻掺杂漏极44底部。此外，依据本发明一实施例，形成栅极电极32后可选择性去除部分导电层34，使导电层34上表面略低于金属层36上表面。在本实施例中，导电层34较佳包含氮化钛而金属层36则较佳包含钨、钛或其组合，但均不局限于此。
之后如图5所示，进行另一离子注入制作工艺48，将与图2中轻掺杂漏极44具有相同导电型式的离子或与图3中掺杂区30具有相反导电型式的离子注入基底16，以形成一掺杂区38于沟槽28两侧的基底16内并位于栅极电极32上，其中本实施例的掺杂区38较佳包含第二导电型式离子或N型离子。更具体而言，掺杂区38中经由离子注入所注入的N型离子浓度较佳大于原本掺杂区30中的P型离子浓度，由此使原本设于沟槽28两侧基底16中的P型掺杂区30被N型掺质所取代而转换为N型掺杂区38。另外需注意的是，图5中经由N型离子注入所形成的掺杂区38底度虽较佳略低于栅极电极32顶部，但不局限于此，本发明又可依据制作工艺需求调离子注入制作工艺的能量，使掺杂区38底部切齐栅极电极32顶部或高于栅极电极32顶部，这些实施例均属本发明所涵盖的范围。在本实施例中，掺杂区38所注入的N型离子可包含例如磷、砷、锑等离子或其组合，其中注入离子形成掺杂区38的能量约介于0.2KeV至20KeV且其剂量约5E12至5E14离子/平方厘米。
值得注意的是，本实施例虽以制作N型晶体管元件为例，但不局限于此，又可依据制作工艺需求比照图1至图5的实施例并通过改变掺质的导电型式来制备P型晶体管。举例来说，本发明又可于图2进行离子注入制作工艺时将N型离子注入基底16内形成阱区26以及利用P型离子形成轻掺杂漏极44、于图3进行离子注入制作工艺时将N型离子注入沟槽28两侧的基底16内形成掺杂区30以及于图5进行离子注入制作工艺时将P型离子注入栅极电极32上方两侧的基底16内形成掺杂区38，此实施例也属本发明所涵盖的范围。
随后如图6所示，形成一硬掩模40于沟槽28内的栅极电极32上，并使硬掩模40上表面切齐基底16上表面，其中硬掩模40较佳包含氮化硅，但不局限于此。至此即完成本发明较佳实施例的一埋藏式字符线的制作。
之后可依据制作工艺需求进行一选择性离子注入制作工艺，以于栅极电极32两侧的基底16内再形成一掺杂区(图未示)，例如一源极/漏极区域。最后进行接触插塞制作工艺，例如可分别于栅极电极32两侧形成位线接触插塞电连接源极/漏极区域与后续所制作的位线，以及形成存储节点接触插塞同时电连接源极/漏极区域与后续所制作的电容。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (8)

1.一种制作动态随机存取存储器元件的方法，包含：
提供一基底，该基底上具有一存储区；
形成一沟槽于该基底的该存储区内；
进行一第一离子注入制作工艺以形成一第一掺杂区具有第一导电型式于该基底内且位于该沟槽旁；
形成一栅极电极于该沟槽内；以及
形成该栅极电极之后，进行一第二离子注入制作工艺以形成一第二掺杂区具有第二导电型式于该基底内并位于该栅极电极上,其中该第二掺杂区的浓度大于该第一掺杂区的浓度。
2.如权利要求1所述的方法，另包含于形成该沟槽之前形成一浅沟隔离于该基底内并定义出该存储区。
3.如权利要求1所述的方法，另包含于形成该沟槽之前形成一阱区具有该第一导电型式于该基底内。
4.如权利要求1所述的方法，另包含形成该第一掺杂区于该沟槽两侧的该基底内以及该沟槽正下方的该基底内。
5.如权利要求1所述的方法，其中该栅极电极包含钨。
6.如权利要求1所述的方法，其中该栅极电极的上表面低于该第一掺杂区的上表面。
7.如权利要求1所述的方法，另包含形成该第二掺杂区于该沟槽两侧的该基底内并位于该栅极电极上方。
8.如权利要求1所述的方法，其中该第一导电型式不同于该第二导电型式。
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