CN107871787B - 一种制造沟槽mosfet的方法 - Google Patents

一种制造沟槽mosfet的方法 Download PDF

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CN107871787B
CN107871787B CN201710942472.2A CN201710942472A CN107871787B CN 107871787 B CN107871787 B CN 107871787B CN 201710942472 A CN201710942472 A CN 201710942472A CN 107871787 B CN107871787 B CN 107871787B
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layer
trench
insulating layer
forming
region
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CN107871787A (zh
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蔡金勇
廖忠平
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Hangzhou Silergy Semiconductor Technology Ltd
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Priority to US16/149,255 priority patent/US10686058B2/en
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Abstract

公开了一种制造沟槽MOSFET的方法。包括：在半导体衬底上形成外延半导体层；在外延半导体层中形成从第一表面延伸至其内部的沟槽；在沟槽的下部形成第一绝缘层和屏蔽导体；形成体区、源区以及漏极电极，其中，在形成第二绝缘层的步骤中，采用至少部分地填充所述沟槽的上部的硬掩模对第二绝缘层进行图案化。形成第二绝缘层的步骤包括：在沟槽的上部形成共形的第二绝缘层，第二绝缘层覆盖沟槽的上部侧壁和屏蔽导体的顶部；在沟槽的上部填充多晶硅层；采用多晶硅层作为硬掩模，刻蚀去除第二绝缘层位于沟槽的上部侧壁上的部分；以及去除所述多晶硅层。本发明简化现有技术中形成沟槽MOSFET的工艺步骤，从而降低生产成本。

Description

一种制造沟槽MOSFET的方法
技术领域
本发明涉及半导体技术，更具体地，涉及一种制造沟槽MOSFET的方法。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)作为功率半导体器件已经得到了广泛的应用，例如在功率变换器中作为开关。
其中，屏蔽栅极沟槽MOSFET相对于传统的MOSFET的优势在于，屏蔽电极减小了栅极-漏极电容，并提高了晶体管的截止电压。栅极电极和屏蔽电极通过介电层而彼此绝缘，该介电层还称作极间电介质或IED。IED必须具有足够的质量和厚度来支持可能存在于屏蔽电极和栅极电极之前的电势差。此外，屏蔽电极和IED层之间的接口处和IED层中的接口阱电荷和介电阱电荷与用于形成IED层的方法主要相关。
现有技术中，确保足够强度和足够可靠的高质量IED以提供需要的电学特性，在形成栅极电极和屏蔽电极之间的IED层时，一般采用沉淀高密度等离子体氧化膜等方式。沉淀等离子氧化膜的方式工艺繁琐，操作复杂，并且生产成本高。因此，需要一种用于形成屏蔽栅极沟槽MOSFET的方法来满足对高质量IED的需求，在降低生产成本的前提下，确保屏蔽栅极沟槽MOSFET的性能。
发明内容
有鉴于此，本发明的目的在于提供一种制造沟槽MOSFET的方法，简化现有技术中形成沟槽MOSFET的工艺步骤，从而降低生产成本。
根据本发明提供一种制造沟槽MOSFET的方法，包括：在半导体衬底上形成具有第一掺杂类型的外延半导体层；在所述外延半导体层中形成从第一表面延伸至其内部的沟槽；在所述沟槽的下部形成第一绝缘层和屏蔽导体，所述第一绝缘层位于所述沟槽的下部侧壁和底部，且将所述屏蔽导体与所述外延半导体层隔开；在所述屏蔽导体的顶部形成第二绝缘层；形成体区、源区以及漏极电极；其中，在形成第二绝缘层的步骤中，采用至少部分地填充所述沟槽的上部的硬掩模对所述第二绝缘层进行图案化。
优选地，其中，所述形成第二绝缘层的步骤包括：在所述沟槽的上部形成共形的第二绝缘层，所述第二绝缘层覆盖所述沟槽的上部侧壁和所述屏蔽导体的顶部；在所述沟槽的上部填充多晶硅层；采用所述多晶硅层作为所述硬掩模，刻蚀去除所述第二绝缘层位于所述沟槽的上部侧壁上的部分；以及去除所述多晶硅层。
优选地，其中，所述填充多晶硅层的步骤包括：沉积多晶硅层，所述多晶硅层包括位于所述沟槽内的第一部分和位于所述第一表面上的第二部分；采用回刻蚀去除所述多晶硅层的第二部分，以暴露所述第二绝缘层的顶端。
优选地，其中，还包括进一步回刻蚀去除所述多晶硅层的第一部分中至少一部分。
优选地，其中，所述回刻蚀为干法刻蚀。
优选地，其中，所述第一绝缘层为采用热氧化或低压化学气相沉积形成的氧化层。
优选地，其中，所述第二绝缘层为采用低压化学气相沉积或等离子体增强化学气相沉积形成的氧化层。
优选地，其中，所述栅介质层为采用热氧化形成的氧化层。
优选地，其中，所述屏蔽导体和所述栅极导体分别为采用低压化学气相沉积形成的多晶硅层。
优选地，所述体区在所述外延半导体层邻近所述沟槽的上部区域中形成，为第二掺杂类型，其中所述第二掺杂类型与所述第一掺杂类型相反；所述源区在所述体区中形成，为所述第一掺杂类型；所述漏极电极在所述半导体衬底的第二表面形成，所述第二表面与所述第一表面彼此相对。
优选地，在形成所述源区之后，还包括：在所述源区上方形成层间介质层；在层间介质层上方形成源极电极。
优选地，还包括：在所述体区中形成所述第二掺杂类型的体接触区；穿透所述层间介质层以及源区到达所述体接触区的导电通道，所述源极电极经由所述导电通道连接至所述体接触区。
优选地，其中，所述第一掺杂类型为N型和P型之一，所述第二掺杂类型为N型和P型中另一个。
根据本发明的实施例的制造沟槽MOSFET的方法在形成第二绝缘层时，首先在沟槽的上部形成共形的第二绝缘层，第二绝缘层覆盖沟槽的上部侧壁和屏蔽导体的顶部；其次在沟槽的上部填充多晶硅层；然后采用多晶硅层作为硬掩模，刻蚀去除第二绝缘层位于沟槽的上部侧壁上的部分；最后，去除多晶硅层。同时该方法的工艺步骤简单，不仅能够提高生产效率，而且能够大大减少制作成本。此外，该方法形成的第二绝缘层的厚度具有均一性和稳定性等优点，从而有足够的质量和厚度来支持可能存在于屏蔽导体和栅极代替之前的电势差。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出根据本发明的实施例的沟槽MOSFET的截面图；以及
图2a至图2k示出根据本发明的实施例的制造沟槽MOSFET的方法的各个阶段的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“A直接在B上面”或“A在B上面并与之邻接”的表述方式。在本申请中，“A直接位于B中”表示A位于B中，并且A与B直接邻接，而非A位于B中形成的掺杂区中。
在本申请中，术语“半导体结构”指在制造半导体器件的各个步骤中形成的整个半导体结构的统称，包括已经形成的所有层或区域。术语“横向延伸”是指沿着大致垂直于沟槽深度方向的方向延伸。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出，半导体器件的各个部分可以由本领域的技术人员公知的材料构成。半导体材料例如包括III-V族半导体，如GaAs、InP、GaN、SiC，以及IV族半导体，如Si、Ge。栅极导体可以由能够导电的各种材料形成，例如金属层、掺杂多晶硅层、或包括金属层和掺杂多晶硅层的叠层栅极导体或者是其他导电材料，例如为TaC、TiN、TaSiN、HfSiN、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、W、和所述各种导电材料的组合。栅极电介质可以由SiO2或介电常数大于SiO2的材料构成，例如包括氧化物、氮化物、氧氮化物、硅酸盐、铝酸盐、钛酸盐。并且，栅极电介质不仅可以由本领域的技术人员公知的材料形成，也可以采用将来开发的用于栅极电介质的材料。
本发明可以各种形式呈现，以下将描述其中一些示例。
图1示出根据本发明的实施例的沟槽MOSFET的截面图。
半导体衬底121例如由硅组成，并且是第一掺杂类型的。第一掺杂类型是N型和P型中的一种，第二掺杂类型是N型和P型中的另一种。为了形成N型外延半导体层或区域，可以在外延半导体层和区域中注入N型掺杂剂(例如P、As)。为了形成P型外延半导体层或区域，可以在外延半导体层和区域中掺入P型掺杂剂(例如B)。在一个示例中，半导体衬底121是N型掺杂。
第一掺杂类型的外延半导体层101位于半导体衬底121与漏极电极122相对的表面上(即，半导体衬底121的第一表面上)。外延半导体层101例如由硅组成。外延半导体层101相对于半导体衬底121是轻掺杂层。通过减薄技术减薄半导体衬底的第二表面，并在所述第二表面上形成漏极电极122。
沟槽从外延半导体层101的第一表面延伸进入其内部，沟槽终止于外延半导体层101中。在沟槽内形成第一绝缘层102和屏蔽导体104，第一绝缘层102位于沟槽的下部侧壁和底部，并且，第一绝缘层102将屏蔽导体104与外延半导体层101隔开。在屏蔽导体104的顶部形成第二绝缘层105。在沟槽的上部形成栅介质层108和栅极导体109，栅介质层108位于沟槽的上部侧壁，且将栅极导体109与外延半导体层101隔开。所述第二绝缘层105将屏蔽导体104以及栅极导体109隔开，同时也将第一绝缘层102和栅介质层108隔开。其中，第一绝缘层102以及第二绝缘层105可以由氧化物或者氮化物组成，例如，氧化硅或者氮化硅；屏蔽导体104和栅极导体109可以由掺杂多晶硅组成。
在外延半导体层101邻近沟槽的上部区域中形成第二掺杂类型的体区111；在体区111中形成第一掺杂类型的源区113；以及在体区111中形成第二掺杂类型的体接触区112。其中第二掺杂类型与第一掺杂类型相反，所述第一掺杂类型为N型和P型之一，所述第二掺杂类型为N型和P型中的另一个。在形成源区113之后，在源区113和栅极导体109上方形成层间介质层114，同时在紧邻源区113处形成穿透层间介质层114以及源区113到达体接触区112的导电通道115，在层间介质层114上方形成源极电极116，源极电极经由导电通道115连接至体接触区112。其中，层间介质层114可以是具有一定厚度的氧化物层，例如，氧化硅。
图2a至图2k描述根据本发明的制造沟槽MOSFET的方法的各个阶段。
如图2a所示，在半导体衬底121上形成外延半导体层101；在外延半导体层101上形成氧化物层。然后，在氧化物层上形成光致抗蚀剂层，然后进行刻蚀。该刻蚀可以采用干法刻蚀，例如离子铣刻蚀、等离子刻蚀、反应离子刻蚀、激光烧蚀，或者通过使用刻蚀溶液的选择型的湿法刻蚀，从光致抗蚀剂掩膜中的开口向下刻蚀，在氧化物层中形成开口，从而将氧化物层图案化成硬掩膜。由于刻蚀的选择，该刻蚀可以停止在外延半导体层101的表面。在形成硬掩膜之后，通过在溶剂中的溶解或灰化去除光致抗蚀剂层。
采用硬掩膜，通过上述已知的刻蚀工艺，进一步刻蚀外延半导体层101，进一步在外延半导体层101中形成沟槽。该沟槽从外延半导体层101的第一表面延伸进入外延半导体层101中。例如控制刻蚀的时间，可以控制沟槽的深度。在图2a所示中，沟槽终止于外延半导体层101中。在形成沟槽之后，可以通过选择性的刻蚀剂，相对于外延半导体层去除硬掩膜。
随后，在图2b所示中，通过热氧化的方式，在沟槽的内部以及外延半导体层101的第一表面形成第一绝缘层102；通过低压化学气相沉积的方式，在沟槽的内部以及外延半导体层101的第一表面形成屏蔽导体104。第一绝缘层102将屏蔽导体104与外延半导体层101隔开，第一绝缘层102和屏蔽导体104延伸分别至外延半导体层101第一表面。第一绝缘层102可以由氧化物或者氮化物组成，例如，氧化硅或者氮化硅；屏蔽导体104可以由掺杂多晶硅组成。
随后，在图2c所示中，首先对屏蔽导体104进行化学机械研磨。然后采用相对于第一绝缘层102选择性的回刻蚀屏蔽导体104，使得外延半导体层101上表面以及沟槽上部的屏蔽导体104去除。该回刻蚀可采用干法刻蚀。
随后，在图2d所示中，采用上述已知的刻蚀工艺，相对于外延半导体层101选择性的刻蚀第一绝缘层102，去除位于外延半导体层101上表面以及沟槽上部的第一绝缘层102，使得第一绝缘层102位于沟槽侧壁与屏蔽导体104之间，并且第一绝缘层102未覆盖屏蔽导体104顶部，例如，第一绝缘层102的表面低于屏蔽导体104的表面。该刻蚀工艺可以是湿法刻蚀，主要在较为平整的膜面上刻出绒面，从而增加光程，减少光的反射，湿法刻蚀可用稀释的盐酸等。
随后，在图2e所示中，通过低压化学气相沉积方式或者等离子体增强化学气相沉积方法，在屏蔽导体104和第一绝缘层102的顶部形成共形的第二绝缘层105。第二绝缘层105覆盖屏蔽导体104和第一绝缘层102的顶部，并且位于沟槽上部侧壁以及外延半导体层101的上表面。第二绝缘105可以由氧化物或者氮化物组成，例如，氧化硅或者氮化硅。
随后，在图2f所示中，采用低压化学气相沉积方式，在覆盖有第二绝缘层105的沟槽中填充多晶硅，形成多晶硅层106，多晶硅层106包括位于沟槽的第一部分和位于第一表面上的第二部分。
随后，在图2g所示中，采用回刻蚀或化学机械平面化去除多晶硅层106的第二部分，使得第二绝缘层105的顶端暴露。进一步地，采用回刻蚀去除多晶硅层106的位于沟槽上部的至少一部分，使得位于沟槽上部的侧壁的部分第二绝缘层105暴露。所述回刻蚀可以是干法刻蚀。干法刻蚀是用等离子体进行薄膜刻蚀的技术。当气体以等离子体形式存在时，它具备两个特点：一方面等离子体中的这些气体化学活性比常态下时要强很多，根据被刻蚀材料的不同，选择合适的气体，就可以更快地与材料进行反应，实现刻蚀去除的目的；另一方面，还可以利用电场对等离子体进行引导和加速，使其具备一定能量，当其轰击被刻蚀物的表面时，会将被刻蚀物材料的原子击出，从而达到利用物理上的能量转移来实现刻蚀的目的。因此，干法刻蚀是晶圆片表面物理和化学两种过程平衡的结果。
随后，在图2h所示中，位于沟槽上部的多晶硅层106作为硬掩膜，通过上述已知的刻蚀工艺，去除第二绝缘层105位于沟槽上部侧壁上的部分，使得屏蔽导体104以及多晶硅层106之间的第二绝缘层105得以保留。
随后，在图2i所示中，采用回刻蚀去除位于沟槽内部的多晶硅层106，使得第二绝缘层105的上端全部暴露。所述回刻蚀可以是干法刻蚀。
随后，在图2j所示中，采用热氧化技术，形成位于沟槽上部的侧壁的氧化层，为栅极介质层108，使得沟槽侧壁被所形成的栅极介质层108覆盖。其中热氧化技术一般为硅与含有氧化物质的气体，例如水汽和氧气在高温下进行化学反应，而在硅片表面产生一层致密的二氧化硅(SiO2)薄膜，是硅平面技术中一项重要的工艺。进一步地，采用低压化学气相沉积的方式，在覆盖有栅极介质层108的沟槽中填充多晶硅，形成栅极导体109，栅极导体109包括位于沟槽的第一部分和位于第一表面上的第二部分。
随后，在图2k所示中，采用回刻蚀或化学机械平面化，去除栅极导体109位于外延半导体层101上表面的第一部分，使得栅极导体109的上端终止于沟槽的开口处。可选择地，采用相对于外延半导体层101选择性去除形成栅极导体109的导体层，回刻蚀该导体层，使得在沟槽中的栅极导体109位于外延半导体层上表面处。被保留第二绝缘层105使得屏蔽导体104以及栅极导体109彼此绝缘，并且被保留第二绝缘层105具有一定的质量和厚度支持可能存在于屏蔽导体104以及栅极导体109之间的电势差。
随后，在图1所示中，采用常规的体注入和驱入技术，进行第一次离子注入，形成在外延半导体层101邻近沟槽的上部区域中的第二掺杂类型的体区111。进一步地，进行第二次离子注入，在体区111中形成第一掺杂类型的源区113。第二类掺杂类型的体区111与第一类掺杂类型的外延半导体层101类型相反。通过控制离子注入的参数，例如注入能量和剂量，可以达到所需要的深度和获得所需的掺杂浓度。采用附加的光致抗蚀剂掩模，可以控制体区111和源区113的横向延伸区域。优选地，体区111和源区113分别与沟槽相邻接，由栅极介质108与栅极导体109之间隔开。
随后，通过上述已知的沉积工艺，形成位于源区113上方的层间介质层114，并且如果需要，进一步进行化学机械平面化，以获得平整的表面。层间介质层114覆盖源区113和栅极导体109的顶部表面。通过上述已知的刻蚀工艺及离子注入工艺，在体区111中形成第二掺杂类型的体接触区112，通过上述已知的刻蚀工艺，形成穿透层间介质层114以及源区113到达体接触区112的导电通道115，以及在层间介质层114上方形成源极电极116，源极电极116经由导电通道115连接至体接触区112。
随后，通过上述已知的沉积工艺，在通过减薄技术减薄的半导体衬底121的第二表面上形成漏极电极122。
上述实施例中，导电通道115、源极电极116、栅极导体109、屏蔽导体104、以及漏极电极122可以分别由导电材料形成，包括诸如铝合金或铜之类的金属材料。
根据本发明的实施例的制造沟槽MOSFET的方法在形成第二绝缘层105的步骤中，采用至少部分地填充沟槽的上部的硬掩模对第二绝缘层105进行图案化：首先在沟槽的上部形成共形的第二绝缘层105，第二绝缘层105覆盖沟槽的上部侧壁和屏蔽导体104的顶部；其次在沟槽的上部填充多晶硅层106；然后采用多晶硅层106作为硬掩模，刻蚀去除第二绝缘层105位于沟槽的上部侧壁上的部分；最后，去除多晶硅层。该方法的工艺步骤简单，不仅能够提高生产效率，提高产品良率，而且能够大大减少制作成本。此外，该方法形成的第二绝缘层的厚度具有均一性和稳定性等优点，从而有足够的质量和厚度来支持可能存在于屏蔽导体和栅极代替之前的电势差。
应当说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

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1.一种制造沟槽MOSFET的方法，包括：
在半导体衬底上形成具有第一掺杂类型的外延半导体层；
在所述外延半导体层中形成从第一表面延伸至其内部的沟槽；
在所述沟槽的下部形成第一绝缘层和屏蔽导体，所述第一绝缘层位于所述沟槽的下部侧壁和底部，且将所述屏蔽导体与所述外延半导体层隔开；
在所述屏蔽导体的顶部形成第二绝缘层；
在所述沟槽的上部形成栅介质层和栅极导体，所述栅介质层位于所述沟槽的上部侧壁，且将所述栅极导体与所述外延半导体层隔开；
形成体区、源区以及漏极电极；
其中，在形成第二绝缘层的步骤中，采用至少部分地填充所述沟槽的上部的硬掩模对所述第二绝缘层进行图案化，
其中，形成第二绝缘层的步骤包括：
在所述沟槽的上部形成共形的所述第二绝缘层，所述第二绝缘层覆盖所述沟槽的上部侧壁和所述屏蔽导体的顶部；
在所述沟槽的上部填充牺牲层；
采用所述牺牲层作为所述硬掩模，刻蚀去除所述第二绝缘层位于所述沟槽的上部侧壁上的部分,使得屏蔽导体以及牺牲层之间的第二绝缘层保留；以及
去除所述牺牲层，
其中，所述第二绝缘层为采用低压化学气相沉积或等离子体增强化学气相沉积形成的氧化层。
2.根据权利要求1所述的方法，其中，所述牺牲层被设置为多晶硅层。
3.根据权利要求1所述的方法，其中，所述填充所述牺牲层的步骤包括：
沉积多晶硅层，所述多晶硅层包括位于所述沟槽内的第一部分和位于所述第一表面上的第二部分；
采用回刻蚀去除所述多晶硅层的第二部分，以暴露所述第二绝缘层的顶端。
4.根据权利要求3所述的方法，其中，还包括进一步回刻蚀去除所述多晶硅层的第一部分中至少一部分。
5.根据权利要求3所述的方法，其中，所述回刻蚀为干法刻蚀。
6.根据权利要求1所述的方法，其中，所述第一绝缘层为采用热氧化或低压化学气相沉积形成的氧化层。
7.根据权利要求1所述的方法，其中，所述栅介质层为采用热氧化形成的氧化层。
8.根据权利要求1所述的方法，其中，所述屏蔽导体和所述栅极导体分别为采用低压化学气相沉积形成的多晶硅层。
9.根据权利要求1所述的方法，其中
所述体区在所述外延半导体层邻近所述沟槽的上部区域中形成，为第二掺杂类型，其中所述第二掺杂类型与所述第一掺杂类型相反；
所述源区在所述体区中形成，为所述第一掺杂类型；
所述漏极电极在所述半导体衬底的第二表面形成，所述第二表面与所述第一表面彼此相对。
10.根据权利要求9所述的方法，在形成所述源区之后，还包括：
在所述源区上方形成层间介质层；
在层间介质层上方形成源极电极。
11.根据权利要求10所述的方法，还包括：
在所述体区中形成第二掺杂类型的体接触区；
穿透所述层间介质层以及源区到达所述体接触区的导电通道，所述源极电极经由所述导电通道连接至所述体接触区。
12.根据权利要求9至11中任一项所述的方法，其中，所述第一掺杂类型为N型和P型之一，所述第二掺杂类型为N型和P型中另一个。
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