WO2020125326A1 - 半导体超结功率器件 - Google Patents

半导体超结功率器件 Download PDF

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WO2020125326A1
WO2020125326A1 PCT/CN2019/120485 CN2019120485W WO2020125326A1 WO 2020125326 A1 WO2020125326 A1 WO 2020125326A1 CN 2019120485 W CN2019120485 W CN 2019120485W WO 2020125326 A1 WO2020125326 A1 WO 2020125326A1
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type
epitaxial layer
gate
type epitaxial
power device
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PCT/CN2019/120485
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English (en)
French (fr)
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袁愿林
刘磊
刘伟
王睿
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苏州东微半导体有限公司
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Publication of WO2020125326A1 publication Critical patent/WO2020125326A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the semiconductor super junction power device is formed with a plurality of p-type column doped regions in an n-type epitaxial layer.
  • the p-type column doped regions and n-type epitaxial layers have opposite doping types.
  • Carriers are easily depleted between n-type epitaxial layers to increase the breakdown voltage of semiconductor superjunction power devices.
  • This application provides a semiconductor super-junction power device, including: n-type drain region;
  • a gate trench located in the second n-type epitaxial layer and between the p-type body region and the p-type columnar doped region;
  • control gate and the shielding gate in the gate trench are separated by an insulating dielectric layer between the control gate, the shielding gate, the second n-type epitaxial layer, and the p-type columnar doped region.
  • the thickness of the second n-type epitaxial layer is smaller than the thickness of the first n-type epitaxial layer.
  • control gate is located in the upper part of the gate trench
  • shield gate is located in the lower part of the gate trench
  • the shielding grid extends upward into the upper part of the grid trench.
  • the width of the upper part of the gate trench is larger than the width of the lower part of the gate trench.
  • the semiconductor superjunction power device of the present application adopts a double-layer n-type epitaxial layer structure, and a gate structure containing a shielding gate is formed in the second n-type epitaxial layer to improve the withstand voltage of the second n-type epitaxial layer and is located at
  • the p-type columnar doped region in the second n-type epitaxial layer extends into the first n-type epitaxial layer to improve the withstand voltage of the first n-type epitaxial layer, so as not to affect the withstand voltage of the semiconductor superjunction power device Under the conditions, the resistivity of the first n-type epitaxial layer and the second n-type epitaxial layer can be reduced, so that the on-resistance of the semiconductor super-junction power device can be reduced.
  • FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor super-junction power device provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a gate trench in the semiconductor super-junction power device shown in FIG. 1.
  • FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor super-junction power device provided by an embodiment of the present application
  • the p-type body region 21 and the n-type source region 23 are both connected to the source voltage.
  • the gate trench 40 is only located in the second n-type epitaxial layer 32 and the bottom of the gate trench 40 coincides with the bottom of the second n-type epitaxial layer 32, so that the second n-type epitaxial layer 32 can be better improved Part of the withstand voltage, optionally, the bottom of the gate trench 40 may also extend into the first n-type substrate epitaxial layer 31 toward the side close to the n-type drain region 20.
  • the bottom of the gate trench 40 is shown in FIG. For example, it extends to the bottom of the second n-type epitaxial layer 32.
  • the control gate 24 and the shielding gate 25 located in the gate trench 40 are separated by an insulating dielectric layer 26 between the control gate 24, the shielding gate 25, and the second n-type epitaxial layer 32, usually the control gate 24 and the second n-type epitaxial layer
  • the insulating dielectric layer between 32 is a gate oxide layer
  • the shield gate 25 is separated from the control gate 24, the second n-type epitaxial layer 32, and the p-type columnar doped region 22 by a field oxide layer, and the thickness of the field oxide layer is greater than that of the gate oxide The thickness of the layer.
  • the control gate 24 controls the opening and closing of the current channel in the p-type body region 21 by connecting the gate voltage.
  • the shielding gate 25 can be connected to the gate voltage or the source voltage, and the shielding gate 25 is connected to the gate voltage Can increase the gate capacitance of the semiconductor super power device, when the shield gate 25 is connected to the source voltage, a lateral electric field can be formed in the second n-type epitaxial layer 32, which plays a role in improving the withstand voltage of the second n-type epitaxial layer 32 effect.
  • the width of the upper portion 41 of the gate trench 40 is generally larger than the width of the lower portion 42 of the gate trench 40, as shown in FIG.
  • the control gate 24 is located in the upper portion 41 of the gate trench 40, and the shield gate 25 may only be located in the lower portion 42 of the gate trench 40 (this structure is not shown in the drawings of the embodiments of the present application).
  • the shield gate 25 With the source voltage drawn, the shield gate 25 generally extends upward into the upper portion 41 of the gate trench 40, as shown in FIG.
  • the semiconductor superjunction power device of the present application adopts a double-layer n-type epitaxial layer structure, and a gate structure containing a shielding gate is formed in the second n-type epitaxial layer (the upper n-type epitaxial layer) to improve the second n-type epitaxial layer.
  • Withstand voltage increase the withstand voltage of the first n-type epitaxial layer (lower n-type epitaxial layer) by applying a source voltage to the p-type columnar doped region, so that without affecting the withstand voltage of the semiconductor superjunction power device,
  • the resistivity of the first n-type epitaxial layer and the second n-type epitaxial layer can be reduced, so that the on-resistance of the semiconductor super junction power device can be reduced, and at the same time, the resistivity of the second n-type epitaxial layer can be made smaller than that of the first n-type epitaxial layer
  • the resistivity of the epitaxial layer can further reduce the on-resistance of the semiconductor super-junction power device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种半导体超结功率器件，包括：n型漏区（20）；位于所述n型漏区（20）之上的第一n型外延层（31）；位于所述第一n型外延层（31）之上的第二n型外延层（32）；位于所述第二n型外延层（32）内的交替排列的p型体区（21）和p型柱状掺杂区（22），所述p型柱状掺杂区（22）向靠近所述n型漏区（20）的一侧延伸至所述第一n型外延层（31）内，所述p型柱状掺杂区（22）接源极电压；位于所述p型体区（21）内的n型源区（23）；位于所述第二n型外延层（32）内且介于所述p型体区（21）和所述p型柱状掺杂区（22）之间的栅沟槽（40）；位于所述栅沟槽（40）中的控制栅（24）和屏蔽栅（25），所述控制栅（24）、所述屏蔽栅（25）、所述第二n型外延层（32）之间由绝缘介质层（26）隔离。

Description

半导体超结功率器件
本公开要求在2018年12月17日提交中国专利局、申请号为201811541595.6的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请涉及半导体功率器件技术领域，例如涉及一种半导体超结功率器件。
背景技术
半导体超级结功率器件是在一层n型外延层内形成多个p型柱状掺杂区，p型柱状掺杂区与n型外延层具有相反的掺杂类型，在p型柱状掺杂区与n型外延层之间载流子容易互相耗尽从而提高半导体超级结功率器件的击穿电压。相关技术中，半导体超级结功率器件的制备方法通常是先在n型外延层内形成若干凹槽，然后进行p型外延层材料生长，从而在凹槽内形成p型柱状掺杂区，然后在p型柱状掺杂区的顶部形成p型体区，并在p型体区内形成n型源区。相关技术的半导体超级结功率器件在保持芯片面积和击穿电压不变的条件下，很难再降低导通电阻。
发明内容
本申请提供一种半导体超结功率器件，以解决相关技术中的半导体超结功率器件的导通电阻难以降低的问题。
本申请提供了一种半导体超结功率器件，包括：n型漏区；
位于所述n型漏区之上的第一n型外延层；
位于所述第一n型外延层之上的第二n型外延层；
位于所述第二n型外延层内的交替排列的p型体区和p型柱状掺杂区，所述p型柱状掺杂区向靠近所述n型漏区的一侧延伸至所述第一n型外延层内，所述p型柱状掺杂区接源极电压；
位于所述p型体区内的n型源区；
位于所述第二n型外延层内且介于所述p型体区和所述p型柱状掺杂区之间的栅沟槽；
位于所述栅沟槽中的控制栅和屏蔽栅，所述控制栅、所述屏蔽栅、所述第二n型外延层、所述p型柱状掺杂区之间由绝缘介质层隔离。
可选的，所述控制栅接栅极电压，所述屏蔽栅接源极电压。
可选的，所述第二n型外延层的厚度小于所述第一n型外延层的厚度。
可选的，所述第二n型外延层的电阻率小于所述第一n型外延层的电阻率。
可选的，所述控制栅位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内。
可选的，所述屏蔽栅向上延伸至所述栅沟槽的上部内。
可选的，所述栅沟槽的上部的宽度大于所述栅沟槽的下部的宽度。
可选的，所述栅沟槽的底部向靠近所述n型漏区的一侧延伸至所述第一n型外延层内。
本申请的半导体超结功率器件采用双层n型外延层结构，在第二n型外延层内形成含有屏蔽栅的栅极结构，用以提高第二n型外延层的耐压，并设置位于第二n形外延层内的p型柱状掺杂区延伸至第一n型外延层内，用以提高第一n型外延层的耐压，这样在不影响半导体超结功率器件的耐压的条件下，可以降低第一n型外延层和第二n型外延层的电阻率，从而可以降低半导体超结功率器件的导通电阻。
附图说明
为了更加清楚地说明本申请示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本申请实施例提供的一种半导体超结功率器件的剖面结构示意图；
图2是图1所示的半导体超结功率器件中的栅沟槽的结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。
应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸；说明书附图是示意性的，不应限 定本申请的范围。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图1是本申请实施例提供的一种半导体超结功率器件的剖面结构示意图，
图2是图1所示的半导体超结功率器件中的栅沟槽的结构示意图。如图1和图2所示，本申请实施列提供的半导体超结功率器件包括：n型漏区20，位于n型漏区20之上的第一n型外延层31，位于第一n型外延层31之上的第二n型外延层32，可选的，第二n型外延层32的厚度小于第一n型外延层31的厚度，这样栅沟槽40的底部可以比较容易地刻蚀到第二n型外延层32的底部。
位于第二n型外延层32内的交替排列的p型体区21和p型柱状掺杂区22，p型柱状掺杂区22向靠近n型漏区20的一侧延伸至第一n型外延层31内，p型柱状掺杂区22接源极电压，用以提高第一n型外延层31部分的耐压。p型柱状掺杂区通过金属层接源极电压，图1中并未展示金属层的具体结构，同时，图1中仅示例性的示出了3个p型体区21结构和3个p型柱状掺杂区22结构，具体的，p型体区21结构和p型柱状掺杂区22结构的数量由产品设计要求确定。
位于p型体区21内的n型源区23，通常p型体区21和n型源区23均接源极电压。
位于第二n型外延层32内且介于p型体区21和p型柱状掺杂区22之间的栅沟槽40。可选的，栅沟槽40仅位于第二n型外延层32内且栅沟槽40的底部与第二n型外延层32的底部重合，这样可以更好的提高第二n型外延层32部分的耐压，可选的，栅沟槽40的底部也可以向靠近n型漏区20的一侧延伸至第一n型衬底外延层31内，图1中以栅沟槽40的底部延伸至第二n型外延层32的底部为例。
位于栅沟槽40中的控制栅24和屏蔽栅25，控制栅24、屏蔽栅25、第二n型外延层32之间由绝缘介质层26隔离，通常控制栅24与第二n型外延层32之间的绝缘介质层为栅氧化层，屏蔽栅25通过场氧化层与控制栅24、第二n型外延层32、p型柱状掺杂区22隔离，场氧化层的厚度要大于栅氧化层的厚度。
控制栅24通过接栅极电压来控制位于p型体区21中的电流沟道的开启和关断，屏蔽栅25可以接栅极电压，也可以接源极电压，屏蔽栅25接栅极电压时可以增大半导体超级功率器件的栅极电容，屏蔽栅25接源极电压时可以在第二n型外延层32内形成横向的电场，起到提高第二n型外延层32的耐压的作用。
为了方便制造，栅沟槽40的上部41的宽度通常大于栅沟槽40的下部42的宽度，如图2所示。控制栅24位于栅沟槽40的上部41内，屏蔽栅25可以仅位于栅沟槽40的下部42内(该结构在本申请实施例附图中未展示)，但是，为了方便将屏蔽栅25引出接源极电压，屏蔽栅25通常向上延伸至栅沟槽40的上部41内，如图1所示。
本申请的半导体超结功率器件采用双层n型外延层结构，在第二n型外延层(上层n型外延层)内形成含有屏蔽栅的栅极结构用以提高第二n型外延层的耐压，通过对p型柱状掺杂区施加源极电压来提高第一n型外延层(下层n型外延层)的耐压，这样在不影响半导体超结功率器件的耐压的条件下，可以降低第一n型外延层和第二n型外延层的电阻率，从而可以降低半导体超结功率器件的导通电阻，同时，可以使得第二n型外延层的电阻率小于第一n型外延层的电阻率，这能够进一步降低半导体超结功率器件的导通电阻。

Claims (8)

  1. 一种半导体超结功率器件，包括：
    n型漏区；
    位于所述n型漏区之上的第一n型外延层；
    位于所述第一n型外延层之上的第二n型外延层；
    位于所述第二n型外延层内的交替排列的p型体区和p型柱状掺杂区，所述p型柱状掺杂区向靠近所述n型漏区的一侧延伸至所述第一n型外延层内，
    所述p型柱状掺杂区接源极电压；
    位于所述p型体区内的n型源区；
    位于所述第二n型外延层内且介于所述p型体区和所述p型柱状掺杂区之间的栅沟槽；
    位于所述栅沟槽中的控制栅和屏蔽栅，所述控制栅、所述屏蔽栅、所述第二n型外延层、所述p型柱状掺杂区之间由绝缘介质层隔离。
  2. 如权利要求1所述的半导体超结功率器件，其中，所述控制栅接栅极电压，所述屏蔽栅接源极电压。
  3. 如权利要求1所述的半导体超结功率器件，其中，所述第二n型外延层的厚度小于所述第一n型外延层的厚度。
  4. 如权利要求1所述的半导体超结功率器件，其中，所述第二n型外延层的电阻率小于所述第一n型外延层的电阻率。
  5. 如权利要求1所述的半导体超结功率器件，其中，所述控制栅位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内。
  6. 如权利要求5所述的半导体超结功率器件，其中，所述屏蔽栅向上延伸至所述栅沟槽的上部内。
  7. 如权利要求1所述的半导体超结功率器件，其中，所述栅沟槽的上部的宽度大于所述栅沟槽的下部的宽度。
  8. 如权利要求1所述的半导体超结功率器件，其中，所述栅沟槽向靠近所述n型漏区的一侧延伸至所述第一n型外延层内。
PCT/CN2019/120485 2018-12-17 2019-11-25 半导体超结功率器件 WO2020125326A1 (zh)

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CN114068526A (zh) * 2020-07-31 2022-02-18 苏州东微半导体股份有限公司 半导体功率器件
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100096692A1 (en) * 2008-10-16 2010-04-22 Kabushiki Kaisha Toshiba Semiconductor device
CN107359201A (zh) * 2017-08-31 2017-11-17 上海华虹宏力半导体制造有限公司 沟槽栅超结mosfet
CN108258027A (zh) * 2016-12-28 2018-07-06 苏州东微半导体有限公司 一种超级结功率晶体管及其制备方法
CN108767000A (zh) * 2018-08-16 2018-11-06 无锡新洁能股份有限公司 一种绝缘栅双极型半导体器件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100096692A1 (en) * 2008-10-16 2010-04-22 Kabushiki Kaisha Toshiba Semiconductor device
CN108258027A (zh) * 2016-12-28 2018-07-06 苏州东微半导体有限公司 一种超级结功率晶体管及其制备方法
CN107359201A (zh) * 2017-08-31 2017-11-17 上海华虹宏力半导体制造有限公司 沟槽栅超结mosfet
CN108767000A (zh) * 2018-08-16 2018-11-06 无锡新洁能股份有限公司 一种绝缘栅双极型半导体器件及其制造方法

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