CN111326585A - 半导体超结功率器件 - Google Patents

半导体超结功率器件 Download PDF

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CN111326585A
CN111326585A CN201811541595.6A CN201811541595A CN111326585A CN 111326585 A CN111326585 A CN 111326585A CN 201811541595 A CN201811541595 A CN 201811541595A CN 111326585 A CN111326585 A CN 111326585A
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epitaxial layer
type epitaxial
gate
power device
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袁愿林
刘磊
刘伟
王睿
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Suzhou Oriental Semiconductor Co Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

本发明属于半导体功率器件技术领域，具体公开了一种半导体超结功率器件，包括：n型漏区；位于所述n型漏区之上的第一n型外延层；位于所述第一n型外延层之上的第二n型外延层；位于所述第二n型外延层内的交替排列的p型体区和p型柱状掺杂区，所述p型柱状掺杂区向靠近所述n型漏区的一侧延伸至所述第一n型外延层内，所述p型柱状掺杂区接源极电压；位于所述p型体区内的n型源区；位于所述第二n型外延层内且介于所述p型体区和所述p型柱状掺杂区之间的栅沟槽；位于所述栅沟槽中的控制栅和屏蔽栅，所述控制栅、所述屏蔽栅、所述第二n型外延层之间由绝缘介质层隔离。

Description

半导体超结功率器件
技术领域
本发明属于半导体功率器件技术领域，特别是涉及一种半导体超结功率器件。
背景技术
半导体超级结功率器件是在一层n型外延层内形成多个p型柱状掺杂区，p型柱状掺杂区与n型外延层具有相反的掺杂类型，在p型柱状掺杂区与n型外延层之间载流子容易互相耗尽从而提高半导体超级结功率器件的击穿电压。现有技术中，半导体超级结功率器件的制备方法通常是先在n型外延层内形成若干凹槽，然后进行p型外延层材料生长，从而在凹槽内形成p型柱状掺杂区，然后在p型柱状掺杂区的顶部形成p型体区，并在p型体区内形成n型源区。现有技术的半导体超级结功率器件在保持芯片面积和击穿电压不变的条件下，很难再降低导通电阻。
发明内容
有鉴于此，本发明的目的是提供一种半导体超结功率器件，以解决现有技术中的半导体超结功率器件的导通电阻难以降低的问题。
为达到本发明的上述目的，本发明提供了一种半导体超结功率器件，包括：
n型漏区；
位于所述n型漏区之上的第一n型外延层；
位于所述第一n型外延层之上的第二n型外延层；
位于所述第二n型外延层内的交替排列的p型体区和p型柱状掺杂区，所述p型柱状掺杂区向靠近所述n型漏区的一侧延伸至所述第一n型外延层内，所述p型柱状掺杂区接源极电压；
位于所述p型体区内的n型源区；
位于所述第二n型外延层内且介于所述p型体区和所述p型柱状掺杂区之间的栅沟槽；
位于所述栅沟槽中的控制栅和屏蔽栅，所述控制栅、所述屏蔽栅、所述第二n型外延层、所述p型柱状掺杂区之间由绝缘介质层隔离。
可选的，所述控制栅接栅极电压，所述屏蔽栅接源极电压。
可选的，所述第二n型外延层的厚度小于所述第一n型外延层的厚度。
可选的，所述第二n型外延层的电阻率小于所述第一n型外延层的电阻率。
可选的，所述控制栅位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内。
可选的，所述屏蔽栅向上延伸至所述栅沟槽的上部内。
可选的，所述栅沟槽的上部的宽度大于所述栅沟槽的下部的宽度。
可选的，所述栅沟槽的底部向靠近所述n型漏区的一侧延伸至所述第一n型外延层内。
本发明的半导体超结功率器件采用双层n型外延层结构，在第二n型外延层内形成含有屏蔽栅的栅极结构，用以提高第二n型外延层的耐压，并设置位于第二n形外延层内的p型柱状掺杂区延伸至第一n型外延层内，用以提高第一n型外延层的耐压，这样在不影响半导体超结功率器件的耐压的条件下，可以降低第一n型外延层和第二n型外延层的电阻率，从而可以降低半导体超结功率器件的导通电阻。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本发明实施例提供的一种半导体超结功率器件的剖面结构示意图；
图2是图1所示的半导体超结功率器件中的栅沟槽的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下将结合本发明实施例中的附图，通过具体方式，完整地描述本发明的技术方案。
应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸；说明书附图是示意性的，不应限定本发明的范围。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图1是本发明实施例提供的一种半导体超结功率器件的剖面结构示意图，
图2是图1所示的半导体超结功率器件中的栅沟槽的结构示意图。如图1和图2所示，本发明实施列提供的半导体超结功率器件包括：n型漏区20，位于n型漏区20之上的第一n型外延层31，位于第一n型外延层31之上的第二n型外延层32，优选的，第二n型外延层32的厚度小于第一n型外延层31的厚度，这样栅沟槽40的底部可以比较容易地刻蚀到第二n型外延层32的底部。
位于第二n型外延层32内的交替排列的p型体区21和p型柱状掺杂区22，p型柱状掺杂区22向靠近n型漏区20的一侧延伸至第一n型外延层31内，p型柱状掺杂区22接源极电压，用以提高第一n型外延层31部分的耐压。p型柱状掺杂区通过金属层接源极电压，图1中并未展示金属层的具体结构，同时，图1中仅示例性的示出了3个p型体区21结构和3个p型柱状掺杂区22结构，具体的，p型体区21结构和p型柱状掺杂区22结构的数量由产品设计要求确定。
位于p型体区21内的n型源区23，通常p型体区21和n型源区23均接源极电压。
位于第二n型外延层32内且介于p型体区21和p型柱状掺杂区22之间的栅沟槽40。优选的，栅沟槽40仅位于第二n型外延层32内且栅沟槽40的底部与第二n型外延层32的底部重合，这样可以更好的提高第二n型外延层32部分的耐压，可选的，栅沟槽40的底部也可以向靠近n型漏区20的一侧延伸至第一n型衬底外延层31内，图1中以栅沟槽40的底部延伸至第二n型外延层32的底部为例。
位于栅沟槽40中的控制栅24和屏蔽栅25，控制栅24、屏蔽栅25、第二n型外延层32之间由绝缘介质层26隔离，通常控制栅24与第二n型外延层32之间的绝缘介质层为栅氧化层，屏蔽栅25通过场氧化层与控制栅24、第二n型外延层32、p型柱状掺杂区22隔离，场氧化层的厚度要大于栅氧化层的厚度。控制栅24通过接栅极电压来控制位于p型体区21中的电流沟道的开启和关断，屏蔽栅25可以接栅极电压，也可以接源极电压，屏蔽栅25接栅极电压时可以增大半导体超级功率器件的栅极电容，屏蔽栅25接源极电压时可以在第二n型外延层32内形成横向的电场，起到提高第二n型外延层32的耐压的作用。
为了方便制造，栅沟槽40的上部41的宽度通常大于栅沟槽40的下部42的宽度，如图2所示。控制栅24位于栅沟槽40的上部41内，屏蔽栅25可以仅位于栅沟槽40的下部42内(该结构在本发明实施例附图中未展示)，但是，为了方便将屏蔽栅25引出接源极电压，屏蔽栅25通常向上延伸至栅沟槽40的上部41内，如图1所示。
本发明的半导体超结功率器件采用双层n型外延层结构，在第二n型外延层(上层n型外延层)内形成含有屏蔽栅的栅极结构用以提高第二n型外延层的耐压，通过对p型柱状掺杂区施加源极电压来提高第一n型外延层(下层n型外延层)的耐压，这样在不影响半导体超结功率器件的耐压的条件下，可以降低第一n型外延层和第二n型外延层的电阻率，从而可以降低半导体超结功率器件的导通电阻，同时，可以使得第二n型外延层的电阻率小于第一n型外延层的电阻率，这能够进一步降低半导体超结功率器件的导通电阻。
以上具体实施方式及实施例是对本发明提出的半导体超结功率器件的技术思想的具体支持，不能以此限定本发明的保护范围。尽管本发明的实施方案已公开如上，但其并不仅仅限于说明书和实施方式中所列运用，对于熟悉本领域的人员而言，可容易地实现另外的修改，因此在不背离权利要求及等同范围所限定的一般概念下，本发明并不限于特定的细节和这里示出与描述的图例。

Claims (8)

1.一种半导体超结功率器件，其特征在于，包括：
n型漏区；
位于所述n型漏区之上的第一n型外延层；
位于所述第一n型外延层之上的第二n型外延层；
位于所述第二n型外延层内的交替排列的p型体区和p型柱状掺杂区，所述p型柱状掺杂区向靠近所述n型漏区的一侧延伸至所述第一n型外延层内，所述p型柱状掺杂区接源极电压；
位于所述p型体区内的n型源区；
位于所述第二n型外延层内且介于所述p型体区和所述p型柱状掺杂区之间的栅沟槽；
位于所述栅沟槽中的控制栅和屏蔽栅，所述控制栅、所述屏蔽栅、所述第二n型外延层、所述p型柱状掺杂区之间由绝缘介质层隔离。
2.如权利要求1所述的半导体超结功率器件，其特征在于，所述控制栅接栅极电压，所述屏蔽栅接源极电压。
3.如权利要求1所述的半导体超结功率器件，其特征在于，所述第二n型外延层的厚度小于所述第一n型外延层的厚度。
4.如权利要求1所述的半导体超结功率器件，其特征在于，所述第二n型外延层的电阻率小于所述第一n型外延层的电阻率。
5.如权利要求1所述的半导体超结功率器件，其特征在于，所述控制栅位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内。
6.如权利要求5所述的半导体超结功率器件，其特征在于，所述屏蔽栅向上延伸至所述栅沟槽的上部内。
7.如权利要求1所述的半导体超结功率器件，其特征在于，所述栅沟槽的上部的宽度大于所述栅沟槽的下部的宽度。
8.如权利要求1所述的半导体超结功率器件，其特征在于，所述栅沟槽向靠近所述n型漏区的一侧延伸至所述第一n型外延层内。
CN201811541595.6A 2018-12-17 2018-12-17 半导体超结功率器件 Pending CN111326585A (zh)

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