WO2022082885A1 - 半导体超结器件的制造方法 - Google Patents

半导体超结器件的制造方法 Download PDF

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WO2022082885A1
WO2022082885A1 PCT/CN2020/127699 CN2020127699W WO2022082885A1 WO 2022082885 A1 WO2022082885 A1 WO 2022082885A1 CN 2020127699 W CN2020127699 W CN 2020127699W WO 2022082885 A1 WO2022082885 A1 WO 2022082885A1
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Prior art keywords
insulating layer
type
trench
manufacturing
layer
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PCT/CN2020/127699
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English (en)
French (fr)
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刘伟
袁愿林
王睿
刘磊
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苏州东微半导体股份有限公司
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Priority to KR1020227000051A priority Critical patent/KR102607110B1/ko
Priority to US17/621,486 priority patent/US11973107B2/en
Priority to JP2021576568A priority patent/JP7291429B2/ja
Priority to DE112020002916.6T priority patent/DE112020002916T5/de
Publication of WO2022082885A1 publication Critical patent/WO2022082885A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the present application belongs to the technical field of semiconductor superjunction devices, and relates to a manufacturing method of a semiconductor superjunction device.
  • the main manufacturing process of the semiconductor superjunction device in the prior art includes: first, as shown in FIG. 1 , forming a first insulating layer 11 on an n-type substrate 10 An opening is formed in the n-type substrate 10 and a trench 12 is formed in the n-type substrate 10; next, as shown in FIG. 2, the first insulating layer is removed, and a p-type pillar 13 is formed in the formed trench by an epitaxy process; As shown in FIG.
  • the gate dielectric layer 14 and the gate electrode 15 are formed by a photolithography process and an etching process, and then a p-type body region 16 and an n-type body region 16 in the p-type body region 16 are formed in the n-type substrate 10 source region 17.
  • a photolithography process is required when forming a p-type column, and then a photolithography process is required when forming a gate, because the cost of the photolithography process is expensive. , and there is a risk of misalignment, resulting in higher manufacturing costs and manufacturing risks for semiconductor superjunction devices.
  • the purpose of the present application is to provide a method for manufacturing a semiconductor superjunction device, so as to reduce the manufacturing cost of the semiconductor superjunction device and reduce the manufacturing risk of the semiconductor superjunction device.
  • the present application provides a method for manufacturing a semiconductor superjunction device, comprising:
  • the insulating spacers are etched away, the n-type substrate is etched by using the first insulating layer and the second insulating layer as masks, and a second trench is formed in the n-type substrate.
  • the manufacturing method of the semiconductor superjunction device of the present invention further comprises:
  • the first insulating layer and the second insulating layer are etched away, a gate dielectric layer and a gate electrode are formed in the second trench, and the gate electrode is isolated from the p-type pillar by the gate dielectric layer ;
  • An n-type source region is formed within the p-type body region.
  • the first insulating layer includes a silicon oxide layer.
  • the second insulating layer is a silicon oxide layer.
  • the insulating spacer is a silicon nitride layer.
  • the second trench is formed by etching
  • an etching method combining anisotropic etching and isotropic etching is used.
  • the depth of the second trench is smaller than the depth of the first trench.
  • a first trench is formed by a single photolithography process
  • an n-type substrate is self-aligned by using the first insulating layer and the second insulating layer as masks
  • the n-type substrate is A second trench is formed in the substrate.
  • 1 to 3 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of a semiconductor superjunction device of the related art
  • 4 to 9 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of the manufacturing method of a semiconductor superjunction device provided by the present application.
  • 4 to 9 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of the manufacturing method of a semiconductor superjunction device provided by the present application.
  • a first insulating layer 30 is formed on the provided n-type substrate 20.
  • the n-type substrate 20 is usually a silicon substrate.
  • the first insulating layer 30 includes a silicon oxide layer, such as an oxide layer.
  • the silicon layer may be a stack of silicon oxide layer-silicon nitride layer-silicon oxide layer.
  • the position of the opening is defined by a photolithography process, and then the first insulating layer 30 is etched to form an opening 41 in the first insulating layer 30.
  • the number of the opening 41 is determined by the specifications of the designed semiconductor superjunction device.
  • the present invention implements Only two openings 41 are shown by way of example in the example.
  • an insulating spacer 31 is formed in the opening, and the insulating spacer 31 may be a silicon nitride layer.
  • the silicon nitride layer is etched back to form insulating spacers 31 at the sidewalls of the opening in a self-aligned manner.
  • the n-type substrate 20 is etched by using the first insulating layer 30 and the insulating spacers 31 as masks to form the first trenches 42 in the n-type substrate 20 .
  • a p-type pillar 21 is formed in the first trench by an epitaxy process, usually a layer of p-type silicon is epitaxially first, and then the p-type silicon is etched, and the remaining p-type silicon is etched.
  • the silicon layer forms a p-type pillar 21
  • the p-type pillar 21 and the n-type substrate 20 form a pn junction structure.
  • a second insulating layer 32 is formed on the surface of the p-type pillar 21 .
  • the second insulating layer 32 may be a silicon oxide layer and is formed by a thermal oxidation process.
  • the insulating spacers are etched away, the first insulating layer 30 and the second insulating layer 32 are used as masks to etch the n-type substrate 20 , and a second trench is formed in the n-type substrate 20
  • the depths of the grooves 43 and the second grooves 43 are smaller than the depths of the first grooves.
  • the second trench 43 is formed by etching
  • an etching method combining anisotropic etching and isotropic etching can be used, so that the width of the second trench 43 can be increased, so that the width of the second trench 43 can be increased.
  • the width is greater than the width of the insulating spacer, the upper portion of the p-type pillar 21 will also be partially etched away, so that the width of the upper portion of the p-type pillar 21 is smaller than the width of the lower portion of the p-type pillar 21 .
  • the width of the gate electrode formed later can be increased, so that the gate electrode can be more easily drawn out and the reliability of the semiconductor superjunction device is improved.
  • the first insulating layer and the second insulating layer are etched away, a gate dielectric layer 23 and a gate electrode 24 are formed in the second trench, and the gate electrode 24 is connected to the p-type pillar through the gate dielectric layer 23 21 Quarantine.
  • the gate dielectric layer 23 and the gate electrode 24 can also be formed in the second trench first, and then the first insulating layer and the second insulating layer can be etched away.
  • a p-type body region 34 is formed in the n-type substrate 20 , and an n-type source region 25 is formed in the p-type body region 34 .
  • a semiconductor superjunction device can be obtained by forming an isolation dielectric layer and a metal layer according to a conventional process.
  • a first trench is formed by a photolithography process, a p-type column is formed in the first trench, a second insulating layer is formed on the surface of the p-type column, and then a first The insulating layer and the second insulating layer are masks to etch the n-type substrate in a self-aligned manner, a second trench is formed in the n-type substrate, and a gate dielectric layer and a gate electrode are formed in the second trench.

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  • Power Engineering (AREA)
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  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
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  • Junction Field-Effect Transistors (AREA)
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Abstract

一种半导体超结器件的制造方法，包括：以第一绝缘层(30)和第二绝缘层(32)为掩膜自对准地刻蚀n型衬底(20)，在n型衬底(20)内形成第二沟槽(43)，在第二沟槽(43)内形成栅极结构。

Description

半导体超结器件的制造方法 技术领域
本申请属于半导体超结器件技术领域，涉及一种半导体超结器件的制造方法。
背景技术
半导体超结器件基于电荷平衡技术，可以降低导通电阻和寄生电容，使得半导体超结器件具有极快的开关特性，可以降低开关损耗，实现更高的功率转换效率。现有技术的半导体超结器件的主要制造工艺包括：首先，如图1所示，在n型衬底10上形成第一绝缘层11，然后进行光刻和刻蚀，在第一绝缘层11内形成开口并在n型衬底10内形成沟槽12；接下来，如图2所示，去除第一绝缘层，通过外延工艺在所形成的沟槽内形成p型柱13；之后，如图3所示，再通过一次光刻工艺和刻蚀工艺形成栅介质层14和栅极15，然后在n型衬底10内形成p型体区16和位于p型体区16内的n型源区17。不论是平面型还是沟槽型的半导体超结器件，在形成p型柱时需要进行一次光刻工艺，然后在形成栅极时，还需要再进行一次光刻工艺，由于光刻工艺的成本昂贵，而且存在对准偏差的风险，导致半导体超结器件的制造成本和制造风险较高。
发明内容
本申请的目的是提供一种半导体超结器件的制造方法，以降低半导体超结器件的制造成本并降低半导体超结器件的制造风险。
为达到本申请的上述目的，本申请提供了一种半导体超结器件的制造方法，包括：
在n型衬底上形成第一绝缘层，刻蚀所述第一绝缘层形成开口；
在所述开口内形成绝缘侧墙；
以所述第一绝缘层和所述绝缘侧墙为掩膜对所述n型衬底进行刻蚀，在所述n型衬底内形成第一沟槽；
在所述第一沟槽内形成p型柱，所述p型柱与所述n型衬底形成pn结结构；
在所述p型柱的表面形成第二绝缘层；和
刻蚀掉所述绝缘侧墙，以所述第一绝缘层和所述第二绝缘层为掩膜刻蚀所述n型衬底，在所述n型衬底内形成第二沟槽。
可选的，本发明的半导体超结器件的制造方法还包括：
刻蚀掉所述第一绝缘层和所述第二绝缘层，在所述第二沟槽内形成栅介质层和栅极，所述栅极通过所述栅介质层与所述p型柱隔离；
在所述n型衬底内形成p型体区；
在所述p型体区内形成n型源区。
可选的，所述第一绝缘层包括氧化硅层。
可选的，所述第二绝缘层为氧化硅层。
可选的，所述绝缘侧墙为氮化硅层。
可选的，在刻蚀形成所述第二沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
可选的，所述第二沟槽的深度小于所述第一沟槽的深度。
本申请提供的半导体超结器件的制造方法，通过一次光刻工艺形成第一沟槽，以第一绝缘层和第二绝缘层为掩膜自对准地刻蚀n型衬底，在n型衬底内形成第二沟槽。本申请的半导体超结器件的制造方法，形成栅极和p型柱只需要进行一次光刻工艺，可以极大的降低半导体超结器件的制造成本，并降低半 导体超结器件的制造风险。
附图说明
为了更加清楚地说明本申请示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1至图3是相关技术的半导体超结器件的制造工艺中的主要结构的剖面结构示意图；
图4至图9是本申请提供的半导体超结器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体实施方式，详细地描述本申请的技术方案。显然，所描述的实施例是本申请的一部分实施例。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，所列图形大小并不代表实际尺寸。
图4至图9是本申请提供的半导体超结器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
首先，如图4所示，在提供的n型衬底20之上形成第一绝缘层30，n型衬底20通常为硅衬底，第一绝缘层30包括氧化硅层，例如可以为氧化硅层或者为氧化硅层-氮化硅层-氧化硅层的叠层。通过光刻工艺定义开口的位置，然后对第一绝缘层30进行刻蚀，在第一绝缘层30中形成开口41，开口41的数量由所设计的半导体超结器件的规格确定，本发明实施例中仅示例性的示出了两个开口41。
接下来，如图5所示，在开口内形成绝缘侧墙31，绝缘侧墙31可以为氮化 硅层，具体工艺包括：先淀积一层氮化硅层，然后对所淀积形成的氮化硅层进行回刻，从而自对准地在开口的侧壁位置处形成绝缘侧墙31。形成绝缘侧墙31后，以第一绝缘层30和绝缘侧墙31为掩膜对n型衬底20进行刻蚀，在n型衬底20内形成第一沟槽42。
接下来，如图6所示，通过外延工艺在第一沟槽内形成p型柱21，通常是先外延一层p型硅，然后对p型硅进行刻蚀，刻蚀后剩余的p型硅层形成p型柱21，p型柱21与n型衬底20形成pn结结构。之后，在p型柱21的表面形成第二绝缘层32，第二绝缘层32可以为氧化硅层，通过热氧化的工艺形成。
接下来，如图7所示，刻蚀掉绝缘侧墙，以第一绝缘层30和第二绝缘层32为掩膜刻蚀n型衬底20，在n型衬底20内形成第二沟槽43，第二沟槽43的深度小于第一沟槽的深度。
在刻蚀形成第二沟槽43时，可以采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法，这样可以增加第二沟槽43的宽度，使得第二沟槽43的宽度大于绝缘侧墙的宽度，此时p型柱21的上部也会被部分刻蚀掉，从而p型柱21上部的宽度小于p型柱21下部的宽度。通过增加第二沟槽43的宽度，可以增加后面形成的栅极的宽度，从而使栅极更容易被引出，提高半导体超结器件的可靠性。
接下来，如图8所示，刻蚀掉第一绝缘层和第二绝缘层，在第二沟槽内形成栅介质层23和栅极24，栅极24通过栅介质层23与p型柱21隔离。可选的，也可以先在第二沟槽内形成栅介质层23和栅极24，之后再刻蚀掉第一绝缘层和第二绝缘层。
接下来，如图9所示，在n型衬底20内形成p型体区34，在p型体区34 内形成n型源区25。
最后，按照常规工艺形成隔离介质层和金属层等即可得到半导体超结器件。
本申请提供的半导体超结器件的制造方法，通过一次光刻工艺形成第一沟槽，在第一沟槽内形成p型柱并在p型柱的表面形成第二绝缘层，之后以第一绝缘层和第二绝缘层为掩膜自对准地刻蚀n型衬底，在n型衬底内形成第二沟槽，在第二沟槽内形成栅介质层和栅极。从而，本申请的半导体超结器件的制造方法，形成栅极和p型柱只需要进行一次光刻工艺，这可以极大的降低半导体超结器件的制造成本，并降低半导体超结器件的制造风险。
以上具体实施方式及实施例是对本申请技术思想的具体支持，不能以此限定本申请的保护范围。本申请的保护范围以权利要求书为准。

Claims (8)

  1. 半导体超结器件的制造方法，其包括：
    在n型衬底上形成第一绝缘层，刻蚀所述第一绝缘层形成开口；
    在所述开口内形成绝缘侧墙；
    以所述第一绝缘层和所述绝缘侧墙为掩膜对所述n型衬底进行刻蚀，在所述n型衬底内形成第一沟槽；
    在所述第一沟槽内形成p型柱，所述p型柱与所述n型衬底形成pn结结构；
    在所述p型柱的表面形成第二绝缘层；和
    刻蚀掉所述绝缘侧墙，以所述第一绝缘层和所述第二绝缘层为掩膜刻蚀所述n型衬底，在所述n型衬底内形成第二沟槽。
  2. 如权利要求1所述的半导体超结器件的制造方法，其还包括：
    刻蚀掉所述第一绝缘层和所述第二绝缘层，然后在所述第二沟槽内形成栅介质层和栅极，所述栅极通过所述栅介质层与所述p型柱隔离；
    在所述n型衬底内形成p型体区；和
    在所述p型体区内形成n型源区。
  3. 如权利要求1所述的半导体超结器件的制造方法，其还包括：
    在所述第二沟槽内形成栅介质层和栅极，所述栅极通过所述栅介质层与所述p型柱隔离，然后刻蚀掉所述第一绝缘层和所述第二绝缘层；
    在所述n型衬底内形成p型体区；和
    在所述p型体区内形成n型源区。
  4. 如权利要求1所述的半导体超结器件的制造方法，其中，所述第一绝缘层包括氧化硅层。
  5. 如权利要求1所述的半导体超结器件的制造方法，其中，所述第二绝缘 层为氧化硅层。
  6. 如权利要求1所述的半导体超结器件的制造方法，其中，所述绝缘侧墙为氮化硅层。
  7. 如权利要求1所述的半导体超结器件的制造方法，其中，在刻蚀形成所述第二沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
  8. 如权利要求1所述的半导体超结器件的制造方法，其中，所述第二沟槽的深度小于所述第一沟槽的深度。
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