JP5103118B2 - 半導体ウエハおよびその製造方法 - Google Patents
半導体ウエハおよびその製造方法 Download PDFInfo
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- JP5103118B2 JP5103118B2 JP2007252200A JP2007252200A JP5103118B2 JP 5103118 B2 JP5103118 B2 JP 5103118B2 JP 2007252200 A JP2007252200 A JP 2007252200A JP 2007252200 A JP2007252200 A JP 2007252200A JP 5103118 B2 JP5103118 B2 JP 5103118B2
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Description
により解決するものである。
2’ 第1のエピタキシャル層
2 第1半導体層
3 トレンチ
4’ 第2のエピタキシャル層
4 第2半導体層
5’ 第3のエピタキシャル層
5 第3半導体層
6’ 絶縁膜
6 絶縁層
M マスク
L1 第1の距離
L2 第2の距離
L3 第3の距離
W1 第1半導体層幅
W2 第2半導体層幅
W3 第3半導体層幅
d1、d2 第2のエピタキシャル層厚み
d3 第3のエピタキシャル層厚み
E、e 他の半導体層
S 空間部
Claims (7)
- 一導電型半導体基板と、
該半導体基板の上に第1の距離で離間して複数設けられた第1のエピタキシャル層よりなる第1半導体層と、
第2の距離で離間し且つ前記第1半導体層と隣接して複数設けられ、前記第1のエピタキシャル層と逆の導電型の第2のエピタキシャル層よりなる第2半導体層と、
第3の距離で離間し且つ前記第2半導体層と隣接して複数設けられ、前記第1のエピタキシャル層と同じ導電型の第3のエピタキシャル層よりなる第3半導体層と、
隣り合う前記第3半導体層の間に第4の距離で離間して埋め込まれた複数の絶縁層と、を具備し、
半導体ウエハ表面に対して垂直方向に複数のpn接合が設けられ、隣り合う前記絶縁層の間に前記第1半導体層、前記第2半導体層および前記第3半導体層が配置されることを特徴とする半導体ウエハ。 - 前記第3の半導体層と前記絶縁層の間に、導電型が交互になるように隣接する他の半導体層を設けることを特徴とする請求項1に記載の半導体ウエハ。
- 前記第1半導体層、前記第2半導体層、前記第3半導体層および前記他の半導体層は、前記半導体ウエハ表面に対して垂直方向に不純物濃度プロファイルが均一であることを特徴とする請求項2に記載の半導体ウエハ。
- 一導電型半導体基板を準備し、該半導体基板上に第1のエピタキシャル層を形成する工程と、
前記第1のエピタキシャル層にトレンチを複数形成し、第1半導体層を形成する工程と、
前記第1のエピタキシャル層と異なる導電型の第2エピタキシャル層を形成する工程と、
前記第2エピタキシャル層を全面異方性エッチングして前記第1半導体層に隣接する第2半導体層を形成する工程と、
前記第1のエピタキシャル層と同導電型の第3のエピタキシャル層を形成する工程と、
前記第3のエピタキシャル層を全面異方性エッチングし、前記第2半導体層に隣接する第3の半導体層を形成する工程と、
隣り合う前記第3の半導体層の間に絶縁層を埋め込む工程と、
を具備し、
半導体ウエハ表面に対して垂直方向に複数のpn接合を形成することを特徴とする半導体ウエハの製造方法。 - 前記トレンチ形成後、熱酸化によりダメージ層を除去することを特徴とする請求項4に記載の半導体ウエハの製造方法。
- 前記第3の半導体層を形成後で且つ前記絶縁層の形成前に、他のエピタキシャル層を形成する工程と、該他のエピタキシャル層の全面異方性エッチングを行う工程とを有し、導電型が交互になるように互いに隣接する他の半導体層を形成することを特徴とする請求項4に記載の半導体ウエハの製造方法。
- 前記第1半導体層、前記第2半導体層、前記第3半導体層および前記他の半導体層は、前記半導体ウエハ表面に対して垂直方向に不純物濃度プロファイルが均一であることを特徴とする請求項6に記載の半導体ウエハの製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2007252200A JP5103118B2 (ja) | 2007-09-27 | 2007-09-27 | 半導体ウエハおよびその製造方法 |
US12/236,348 US8217486B2 (en) | 2007-09-27 | 2008-09-23 | Semiconductor device and method of processing the same |
CN2008101657763A CN101414553B (zh) | 2007-09-27 | 2008-09-23 | 半导体晶片的制造方法 |
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JP2007252200A JP5103118B2 (ja) | 2007-09-27 | 2007-09-27 | 半導体ウエハおよびその製造方法 |
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JP2009087997A JP2009087997A (ja) | 2009-04-23 |
JP5103118B2 true JP5103118B2 (ja) | 2012-12-19 |
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JP (1) | JP5103118B2 (ja) |
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Families Citing this family (22)
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JP4496237B2 (ja) * | 2007-05-14 | 2010-07-07 | 株式会社 日立ディスプレイズ | 液晶表示装置 |
JP5261641B2 (ja) | 2007-09-13 | 2013-08-14 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体ウエハの製造方法 |
US9508805B2 (en) * | 2008-12-31 | 2016-11-29 | Alpha And Omega Semiconductor Incorporated | Termination design for nanotube MOSFET |
US7943989B2 (en) * | 2008-12-31 | 2011-05-17 | Alpha And Omega Semiconductor Incorporated | Nano-tube MOSFET technology and devices |
US10121857B2 (en) * | 2008-12-31 | 2018-11-06 | Alpha And Omega Semiconductor Incorporated | Nano-tube MOSFET technology and devices |
JP5400405B2 (ja) * | 2009-02-05 | 2014-01-29 | 株式会社東芝 | 半導体装置の製造方法 |
US8299494B2 (en) * | 2009-06-12 | 2012-10-30 | Alpha & Omega Semiconductor, Inc. | Nanotube semiconductor devices |
US7910486B2 (en) * | 2009-06-12 | 2011-03-22 | Alpha & Omega Semiconductor, Inc. | Method for forming nanotube semiconductor devices |
US7892924B1 (en) * | 2009-12-02 | 2011-02-22 | Alpha And Omega Semiconductor, Inc. | Method for making a charge balanced multi-nano shell drift region for superjunction semiconductor device |
JP5489855B2 (ja) * | 2010-05-14 | 2014-05-14 | キヤノン株式会社 | 固体撮像装置の製造方法 |
JP5560897B2 (ja) * | 2010-05-20 | 2014-07-30 | 富士電機株式会社 | 超接合半導体装置の製造方法 |
JP5839807B2 (ja) * | 2011-02-09 | 2016-01-06 | キヤノン株式会社 | 固体撮像装置の製造方法 |
CN102184859A (zh) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | 冷mos超结结构的制造方法以及冷mos超结结构 |
CN103022086A (zh) * | 2011-09-26 | 2013-04-03 | 朱江 | 一种半导体晶片及其制备方法 |
CN103035707B (zh) * | 2013-01-04 | 2017-05-10 | 电子科技大学 | 一种超结垂直氮化镓基异质结场效应晶体管 |
WO2015040938A1 (ja) * | 2013-09-18 | 2015-03-26 | 富士電機株式会社 | 半導体装置およびその製造方法 |
CN105304687B (zh) * | 2014-07-28 | 2019-01-11 | 万国半导体股份有限公司 | 用于纳米管mosfet的端接设计 |
US9852902B2 (en) | 2014-10-03 | 2017-12-26 | Applied Materials, Inc. | Material deposition for high aspect ratio structures |
CN104409334B (zh) * | 2014-11-06 | 2017-06-16 | 中航(重庆)微电子有限公司 | 一种超结器件的制备方法 |
CN108022924B (zh) * | 2017-11-30 | 2020-08-07 | 上海华虹宏力半导体制造有限公司 | 沟槽型超级结及其制造方法 |
CN108288587A (zh) * | 2018-01-29 | 2018-07-17 | 贵州芯长征科技有限公司 | 高压超结结构的制备方法 |
CN112086506B (zh) | 2020-10-20 | 2022-02-18 | 苏州东微半导体股份有限公司 | 半导体超结器件的制造方法 |
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US5177028A (en) * | 1991-10-22 | 1993-01-05 | Micron Technology, Inc. | Trench isolation method having a double polysilicon gate formed on mesas |
JP4088033B2 (ja) * | 2000-11-27 | 2008-05-21 | 株式会社東芝 | 半導体装置 |
US6821824B2 (en) * | 2001-02-21 | 2004-11-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
JP2004342660A (ja) * | 2003-05-13 | 2004-12-02 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4904673B2 (ja) * | 2004-02-09 | 2012-03-28 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP4773716B2 (ja) * | 2004-03-31 | 2011-09-14 | 株式会社デンソー | 半導体基板の製造方法 |
JP2006156989A (ja) * | 2004-11-05 | 2006-06-15 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4692313B2 (ja) * | 2006-02-14 | 2011-06-01 | トヨタ自動車株式会社 | 半導体装置 |
JP5261641B2 (ja) * | 2007-09-13 | 2013-08-14 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体ウエハの製造方法 |
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US20090085149A1 (en) | 2009-04-02 |
JP2009087997A (ja) | 2009-04-23 |
CN101414553B (zh) | 2011-04-20 |
US8217486B2 (en) | 2012-07-10 |
CN101414553A (zh) | 2009-04-22 |
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