CN112086506B - 半导体超结器件的制造方法 - Google Patents

半导体超结器件的制造方法 Download PDF

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CN112086506B
CN112086506B CN202011125896.8A CN202011125896A CN112086506B CN 112086506 B CN112086506 B CN 112086506B CN 202011125896 A CN202011125896 A CN 202011125896A CN 112086506 B CN112086506 B CN 112086506B
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CN112086506A (zh
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刘伟
袁愿林
王睿
刘磊
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Suzhou Dongwei Semiconductor Co ltd
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Abstract

本发明属于半导体超结器件技术领域，具体公开了一种半导体超结器件的制造方法，包括：以第一绝缘层和第二绝缘层为掩膜自对准的刻蚀n型衬底，在n型衬底内形成第二沟槽，在第二沟槽内形成栅极结构。本发明的半导体超结器件的制造方法，形成栅极和p型柱只需要进行一次光刻工艺，可以极大的降低半导体超结器件的制造成本，并降低半导体超结器件的制造风险。

Description

半导体超结器件的制造方法
技术领域
本发明属于半导体超结器件技术领域，特别是涉及一种半导体超结器件的制造方法。
背景技术
半导体超结器件基于电荷平衡技术，可以降低导通电阻和寄生电容，使得半导体超结器件具有极快的开关特性，可以降低开关损耗，实现更高的功率转换效率。现有技术的半导体超结器件的主要制造工艺包括：首先，如图1所示，在n型衬底10上形成第一绝缘层11，然后进行光刻和刻蚀，在第一绝缘层11内形成开口并在n型衬底10内形成沟槽12；接下来，如图2所示，去除第一绝缘层，通过外延工艺在所形成的沟槽内形成p型柱13；之后，如图3所示，再通过一次光刻工艺和刻蚀工艺形成栅介质层14和栅极15，然后在n型衬底10内形成p型体区16和位于p型体区16内的n型源区17。不论是平面型还是沟槽型的半导体超结器件，在形成p型柱时需要进行一次光刻工艺，然后在形成栅极时，还需要再进行一次光刻工艺，由于光刻工艺的成本昂贵，而且存在对准偏差的风险，导致半导体超结器件的制造成本和制造风险较高。
发明内容
有鉴于此，本发明的目的是提供一种半导体超结器件的制造方法，以降低半导体超结器件的制造成本并降低半导体超结器件的制造风险。
为达到本发明的上述目的，本发明提供了一种半导体超结器件的制造方法，包括：
在n型衬底上形成第一绝缘层，刻蚀所述第一绝缘层形成开口；
在所述开口内形成绝缘侧墙；
以所述第一绝缘层和所述绝缘侧墙为掩膜对所述n型衬底进行刻蚀，在所述n型衬底内形成第一沟槽；
在所述第一沟槽内形成p型柱，所述p型柱与所述n型衬底形成pn结结构；
在所述p型柱的表面形成第二绝缘层；
刻蚀掉所述绝缘侧墙，以所述第一绝缘层和所述第二绝缘层为掩膜刻蚀所述n型衬底，在所述n型衬底内形成第二沟槽。
可选的，本发明的半导体超结器件的制造方法还包括：
刻蚀掉所述第一绝缘层和所述第二绝缘层，在所述第二沟槽内形成栅介质层和栅极，所述栅极通过所述栅介质层与所述p型柱隔离；
在所述n型衬底内形成p型体区；
在所述p型体区内形成n型源区。
可选的，所述第一绝缘层包括氧化硅层。
可选的，所述第二绝缘层为氧化硅层。
可选的，所述绝缘侧墙为氮化硅层。
可选的，在刻蚀形成所述第二沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
可选的，所述第二沟槽的深度小于所述第一沟槽的深度。
本发明提供的半导体超结器件的制造方法，通过一次光刻工艺形成第一沟槽，以第一绝缘层和第二绝缘层为掩膜自对准的刻蚀n型衬底，在n型衬底内形成第二沟槽。本发明的半导体超结器件的制造方法，形成栅极和p型柱只需要进行一次光刻工艺，可以极大的降低半导体超结器件的制造成本，并降低半导体超结器件的制造风险。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1至图3是现有技术的半导体超结器件的制造工艺中的主要结构的剖面结构示意图；
图4至图9是本发明提供的半导体超结器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体实施方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，所列图形大小并不代表实际尺寸。
图4至图9是本发明提供的半导体超结器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
首先，如图4所示，在提供的n型衬底20之上形成第一绝缘层30，n型衬底20通常为硅衬底，第一绝缘层30包括氧化硅层，例如可以为氧化硅层或者为氧化硅层-氮化硅层-氧化硅层的叠层。通过光刻工艺定义开口的位置，然后对第一绝缘层30进行刻蚀，在第一绝缘层30中形成开口41，开口41的数量由所设计的半导体超结器件的规格确定，本发明实施例中仅示例性的示出了两个开口41。
接下来，如图5所示，在开口内形成绝缘侧墙31，绝缘侧墙31优选为氮化硅层，具体工艺包括：先淀积一层氮化硅层，然后对所淀积形成的氮化硅层进行回刻，从而自对准的在开口的侧壁位置处形成绝缘侧墙31。形成绝缘侧墙31后，以第一绝缘层30和绝缘侧墙31为掩膜对n型衬底20进行刻蚀，在n型衬底20内形成第一沟槽42。
接下来，如图6所示，通过外延工艺在第一沟槽内形成p型柱21，通常是先外延一层p型硅，然后对p型硅进行刻蚀，刻蚀后剩余的p型硅层形成p型柱21，p型柱21与n型衬底20形成pn结结构。之后，在p型柱21的表面形成第二绝缘层32，第二绝缘层32优选为氧化硅层，通过热氧化的工艺形成。
接下来，如图7所示，刻蚀掉绝缘侧墙，以第一绝缘层30和第二绝缘层32为掩膜刻蚀n型衬底20，在n型衬底20内形成第二沟槽43，第二沟槽43的深度小于第一沟槽的深度。
在刻蚀形成第二沟槽43时，可以采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法，这样可以增加第二沟槽43的宽度，使得第二沟槽43的宽度大于绝缘侧墙的宽度，此时p型柱21的上部也会被部分刻蚀掉，从而p型柱21上部的宽度小于p型柱21下部的宽度。通过增加第二沟槽43的宽度，可以增加后面形成的栅极的宽度，从而使栅极更容易被引出，提高半导体超结器件的可靠性。
接下来，如图8所示，刻蚀掉第一绝缘层和第二绝缘层，在第二沟槽内形成栅介质层23和栅极24，栅极24通过栅介质层23与p型柱21隔离。可选的，也可以先在第二沟槽内形成栅介质层23和栅极24，之后再刻蚀掉第一绝缘层和第二绝缘层。
接下来，如图9所示，在n型衬底20内形成p型体区34，在p型体区34内形成n型源区25。
最后，按照常规工艺形成隔离介质层和金属层等即可得到半导体超结器件。
本发明提供的半导体超结器件的制造方法，通过一次光刻工艺形成第一沟槽，在第一沟槽内形成p型柱并在p型柱的表面形成第二绝缘层，之后以第一绝缘层和第二绝缘层为掩膜自对准的刻蚀n型衬底，在n型衬底内形成第二沟槽，在第二沟槽内形成栅介质层和栅极。从而，本发明的半导体超结器件的制造方法，形成栅极和p型柱只需要进行一次光刻工艺，这可以极大的降低半导体超结器件的制造成本，并降低半导体超结器件的制造风险。
以上具体实施方式及实施例是对本发明技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (7)

1.半导体超结器件的制造方法，其特征在于，包括：
在n型衬底上形成第一绝缘层，刻蚀所述第一绝缘层形成开口；
在所述开口内形成绝缘侧墙；
以所述第一绝缘层和所述绝缘侧墙为掩膜对所述n型衬底进行刻蚀，在所述n型衬底内形成第一沟槽；
在所述第一沟槽内形成p型柱，所述p型柱与所述n型衬底形成pn结结构；
在所述p型柱的表面形成第二绝缘层；
在形成所述第二绝缘层之后，刻蚀掉所述绝缘侧墙，以所述第一绝缘层和所述第二绝缘层为掩膜刻蚀所述n型衬底，在所述n型衬底内形成第二沟槽。
2.如权利要求1所述的半导体超结器件的制造方法，其特征在于，还包括：
刻蚀掉所述第一绝缘层和所述第二绝缘层，在所述第二沟槽内形成栅介质层和栅极，所述栅极通过所述栅介质层与所述p型柱隔离；
在所述n型衬底内形成p型体区；
在所述p型体区内形成n型源区。
3.如权利要求1所述的半导体超结器件的制造方法，其特征在于，所述第一绝缘层包括氧化硅层。
4.如权利要求1所述的半导体超结器件的制造方法，其特征在于，所述第二绝缘层为氧化硅层。
5.如权利要求1所述的半导体超结器件的制造方法，其特征在于，所述绝缘侧墙为氮化硅层。
6.如权利要求1所述的半导体超结器件的制造方法，其特征在于，在刻蚀形成所述第二沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
7.如权利要求1所述的半导体超结器件的制造方法，其特征在于，所述第二沟槽的深度小于所述第一沟槽的深度。
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