CN113937150A - 半导体功率器件及其制造方法 - Google Patents

半导体功率器件及其制造方法 Download PDF

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CN113937150A
CN113937150A CN202010671084.7A CN202010671084A CN113937150A CN 113937150 A CN113937150 A CN 113937150A CN 202010671084 A CN202010671084 A CN 202010671084A CN 113937150 A CN113937150 A CN 113937150A
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epitaxial layer
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CN113937150B (zh
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刘磊
毛振东
徐真逸
龚轶
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Suzhou Dongwei Semiconductor Co ltd
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Abstract

本发明属于半导体功率器件技术领域，具体公开了一种半导体功率器件及其制造方法，半导体功率器件包括：n型外延层；凹陷在所述n型外延层内的若干个元胞区沟槽和若干个终端区沟槽，所述终端区沟槽的深度小于所述元胞区沟槽的深度；位于所述n型外延层内且位于所述终端区沟槽下方的p型掺杂区，每个所述终端区沟槽的下方均设置有所述p型掺杂区。本发明可以提高半导体功率器件的击穿电压。

Description

半导体功率器件及其制造方法
技术领域
本发明属于半导体功率器件技术领域，特别是涉及一种半导体功率器件及其制造方法。
背景技术
半导体功率器件的设计中，元胞区的设计决定器件的电阻、电容以及击穿电压等特性，但它受限于终端区保护设计的有效性和面积。好的终端区设计中，为保证器件可靠性，电压击穿点应落在元胞区，而不是终端区，同时终端区占用面积会直接影响元胞区的导通电阻。现有技术中的半导体功率器件为了降低特征导通电阻，需要提高n型外延层的掺杂浓度，这使得终端区在横向上难以耗尽，导致终端区耐压低于元胞区耐压，从而影响了半导体功率器件的耐压。
发明内容
有鉴于此，本发明的目的是提供一种半导体功率器件及其制造方法，以解决现有技术的半导体功率器件的耐压难以调整的问题。
为达到本发明的上述目的，本发明提供了一种半导体功率器件，包括：
n型外延层；
凹陷在所述n型外延层内的若干个元胞区沟槽和若干个终端区沟槽，所述终端区沟槽的深度小于所述元胞区沟槽的深度；
位于所述n型外延层内且位于所述终端区沟槽下方的p型掺杂区，每个所述终端区沟槽的下方均设置有所述p型掺杂区。
可选的，本发明的半导体功率器件，所述n型外延层包括第一n型外延层和位于所述第一n型外延层之上的第二n型外延层，所述第一n型外延层和所述第二n型外延层的掺杂浓度不同。
可选的，本发明的半导体功率器件，所述第二n型外延层的掺杂浓度大于所述第一n型外延层的掺杂浓度。
可选的，本发明的半导体功率器件，所述终端区沟槽的底部位于所述第二n型外延层内。
可选的，本发明的半导体功率器件，所述终端区沟槽的底部位于所述第一n型外延层内。
可选的，本发明的半导体功率器件，所述半导体功率器件还包括位于所述终端区沟槽内的场氧化层和导电多晶硅，至少有一个所述终端区沟槽内的导电多晶硅外接源极电压。
可选的，本发明的半导体功率器件，所述终端区沟槽与所述p型掺杂区一一对应。
可选的，本发明的半导体功率器件，位于每个所述终端区沟槽下方的所述p型掺杂区相连接形成一个p型扩散掺杂区。
本发明还提出了上述半导体功率器件的制造方法，包括：
在n型外延层上形成硬掩膜层；
通过光刻工艺和刻蚀工艺形成凹陷在所述n型外延层内的元胞区沟槽和终端区沟槽；
进行p型离子注入，在所述元胞区沟槽和所述终端区沟槽下方的所述n型外延层内形成p型注入区；
通过光刻工艺暴露出所述元胞区沟槽，对所述n型外延层进行刻蚀以刻蚀掉位于所述元胞区沟槽下方的所述p型注入区，保留位于所述终端区沟槽下方的所述p型注入区，所述终端区沟槽的深度小于所述元胞区沟槽的深度。
本发明提供的半导体功率器件，在终端区采用沟槽终端和场环终端相结合的结构，终端区的耐压由沟槽终端结构和场环终端结构共同决定，可以提高终端区的耐压，进而提高半导体功率器件的耐压和可靠性。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本发明提供的半导体功率器件的第一个实施例的剖面结构示意图；
图2是本发明提供的半导体功率器件的第二个实施例的剖面结构示意图；
图3是本发明提供的半导体功率器件的第三个实施例的剖面结构示意图；
图4-图5是本发明提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图1是本发明提供的半导体功率器件的第一个实施例的剖面结构示意图，如图1所示，本发明提供的半导体功率器件包括n型衬底20，位于n型衬底20之上的n型外延层21，凹陷在n型外延层21内的若干个元胞区沟槽201和若干个终端区沟槽202，终端区沟槽202的深度小于元胞区沟槽201的深度，在图1的实施例中，仅示例性的示出了两个元胞区沟槽201和三个终端区沟槽202。在半导体功率器件中，元胞区沟槽201位于元胞区100内，终端区沟槽位于终端区200内，且在俯视结构上，终端区200环绕包围元胞区100。
位于n型外延层21内且位于终端区沟槽202下方的p型掺杂区24，每个终端区沟槽202的下方均设置有p型掺杂区24。位于终端区沟槽202内的场氧化层22和导电多晶硅23，至少有一个终端区沟槽202内的导电多晶硅23外接源极电压。
本发明的半导体功率器件的终端区包括终端区沟槽结构和位于终端区沟槽下方的p型掺杂区，其中终端区沟槽结构作为沟槽终端结构，p型掺杂区作为场环终端结构，由此，终端区的耐压由沟槽终端结构和场环终端结构共同决定，这可以提高终端区的耐压，进而提高半导体功率器件的耐压和可靠性。
图2是本发明提供的半导体功率器件的第二个实施例的剖面结构示意图，如图2所示，本发明的半导体功率器件中的n型外延层可以包括第一n型外延层41和位于第一n型外延层41之上的第二n型外延层42，第一n型外延层41和第二n型外延层42的掺杂浓度不同。可选的，第二n型外延层42的掺杂浓度大于第一n型外延层41的掺杂浓度，由此，低掺杂浓度的第一n型外延层41用于提高半导体功率器件的耐压，高掺杂浓度的第二n型外延层用于降低半导体功率器件的导通电阻。当n型外延层包括第一n型外延层41和第二n型外延层42时，终端区沟槽202的底部可以位于第二n型外延层42内，也可以是终端区沟槽202的底部位于第一n型外延层41内，在图2中，示例性的示出了终端区沟槽202的底部位于第一n型外延层41内的结构。
图3是本发明提供的半导体功率器件的第三个实施例的剖面结构示意图，结合图1和图3所示，本发明的半导体功率器件，终端区沟槽202与p型掺杂区24一一对应，如图1所示；或者如图3所示，本发明的半导体功率器件，位于每个终端区沟槽202的下方的p型掺杂区相连接形成一个p型扩散掺杂区25。
图4-图5是本发明提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图，首先如图4所示，在n型衬底20上形成n型外延层21，并在n型外延层21上形成硬掩膜层31，硬掩膜层31通常包括氧化硅层和氮化硅层；之后通过光刻工艺和刻蚀工艺形成凹陷在n型外延层21内的元胞区沟槽201和终端区沟槽202，图4中仅示例性的示出了两个元胞区沟槽201和三个终端区沟槽202，然后进行p型离子注入，在元胞区沟槽201和终端区沟槽202下方的n型外延层21内形成p型注入区32。
接下来，如图5所示，通过光刻工艺暴露出元胞区沟槽201，然后继续对n型外延层21进行刻蚀以刻蚀掉位于元胞区沟槽21下方的p型注入区32，保留位于终端区沟槽202下方的所述p型注入区32，在该步刻蚀后，元胞区沟槽201的深度会增加，从而使得元胞区沟槽201的深度大于终端区沟槽202的深度。
最后，通过常规工艺即可制备得到本发明的半导体功率器件，需要说明的是，通过控制终端区沟槽202之间的间距以及p型注入区32的注入浓度，在后续制备工艺中，可以使p型注入区32在扩散后，在每个终端区沟槽202的下方均形成一个p型掺杂区；也可以是使p型注入区32在扩散后相连接形成一个p型扩散掺杂区，即在每个终端区沟槽202的下方的p型掺杂区相连接形成一个p型扩散掺杂区。
本发明的半导体功率器件的元胞区沟槽可以适用于不同的栅极结构，如栅极结构和源极多晶硅为上下位置关系，或者栅极结构和源极多晶硅为左右位置关系，同时为了匹配元胞区沟槽内的栅极结构，在终端区沟槽内也可以形成与之相对应的栅极结构，终端区沟槽内的栅极结构应浮空设置或外接源极电压。
以上具体实施方式及实施例是对本发明技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (9)

1.半导体功率器件，其特征在于，包括：
n型外延层；
凹陷在所述n型外延层内的若干个元胞区沟槽和若干个终端区沟槽，所述终端区沟槽的深度小于所述元胞区沟槽的深度；
位于所述n型外延层内且位于所述终端区沟槽下方的p型掺杂区，每个所述终端区沟槽的下方均设置有所述p型掺杂区。
2.如权利要求1所述的半导体功率器件，其特征在于，所述n型外延层包括第一n型外延层和位于所述第一n型外延层之上的第二n型外延层，所述第一n型外延层和所述第二n型外延层的掺杂浓度不同。
3.如权利要求2所述的半导体功率器件，其特征在于，所述第二n型外延层的掺杂浓度大于所述第一n型外延层的掺杂浓度。
4.如权利要求2所述的半导体功率器件，其特征在于，所述终端区沟槽的底部位于所述第二n型外延层内。
5.如权利要求2所述的半导体功率器件，其特征在于，所述终端区沟槽的底部位于所述第一n型外延层内。
6.如权利要求1所述的半导体功率器件，其特征在于，所述半导体功率器件还包括位于所述终端区沟槽内的场氧化层和导电多晶硅，至少有一个所述终端区沟槽内的导电多晶硅外接源极电压。
7.根据权利要求1所述的半导体功率器件，其特征在于，所述终端区沟槽与所述p型掺杂区一一对应。
8.如权利要求1所述的半导体功率器件，其特征在于，位于每个所述终端区沟槽下方的所述p型掺杂区相连接形成一个p型扩散掺杂区。
9.半导体功率器件的制造方法，其特征在于，包括：
在n型外延层上形成硬掩膜层；
通过光刻工艺和刻蚀工艺形成凹陷在所述n型外延层内的元胞区沟槽和终端区沟槽；
进行p型离子注入，在所述元胞区沟槽和所述终端区沟槽下方的n型外延层内形成p型注入区；
通过光刻工艺暴露出所述元胞区沟槽，对所述n型外延层进行刻蚀以刻蚀掉位于所述元胞区沟槽下方的所述p型注入区，保留位于所述终端区沟槽下方的所述p型注入区，所述终端区沟槽的深度小于所述元胞区沟槽的深度。
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