CN112864019A - 半导体功率器件的制造方法及半导体功率器件 - Google Patents

半导体功率器件的制造方法及半导体功率器件 Download PDF

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CN112864019A
CN112864019A CN201911194101.6A CN201911194101A CN112864019A CN 112864019 A CN112864019 A CN 112864019A CN 201911194101 A CN201911194101 A CN 201911194101A CN 112864019 A CN112864019 A CN 112864019A
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groove
oxide layer
trench
power device
gate
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龚轶
毛振东
刘伟
袁愿林
王鑫
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Suzhou Dongwei Semiconductor Co ltd
Suzhou Oriental Semiconductor Co Ltd
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Abstract

本发明实施例提供的半导体功率器件的制造方法，包括：以硬掩膜层为掩膜对半导体衬底进行刻蚀，在半导体衬底内形成第一沟槽；在第一沟槽的表面形成栅氧化层；在第一沟槽的侧壁处形成栅极；以硬掩膜层为掩膜对栅氧化层和半导体衬底进行刻蚀，在半导体衬底内形成第二沟槽；在第一沟槽和第二沟槽内形成氮化硅侧墙；以硬掩膜层和氮化硅侧墙为掩膜对半导体衬底进行刻蚀，在半导体衬底内形成第三沟槽；进行热氧化，在第三沟槽的表面形成第一场氧化层；淀积形成第二场氧化层；淀积第二层多晶硅并回刻，在第三沟槽、第二沟槽和第一沟槽内形成屏蔽栅。本发明在提高半导体功率器件耐压的同时保证了栅极多晶硅的宽度。

Description

半导体功率器件的制造方法及半导体功率器件
技术领域
本发明属于半导体功率器件技术领域，特别是涉及一种半导体功率器件的制造方法及半导体功率器件。
背景技术
现有技术的半导体功率器件包括n型漏区，位于n型漏区之上的n型漂移区，凹陷在n型漂移区中的栅沟槽，栅沟槽包括栅沟槽的上部和下部两部分。栅极多晶硅位于栅沟槽上部的侧壁位置处，屏蔽栅位于栅沟槽下部内并向上延伸至栅沟槽上部内，屏蔽栅通过场氧化层与n型漂移区和栅极多晶硅隔离。现有技术中，在刻蚀形成栅沟槽的下部时，栅极多晶硅会被横向刻蚀，造成栅极多晶硅的宽度缩小，同时，在通过氧化工艺形成场氧化层时，栅极多晶硅也会被氧化，造成栅极多晶硅的宽度被进一步缩小，这造成栅极多晶硅的引出变难。
发明内容
有鉴于此，本发明的目的是提供一种半导体功率器件的制造方法及半导体功率器件，以解决现有技术中的栅极多晶硅引出难的问题。
本发明实施例提供的半导体功率器件的制造方法，包括：
提供一半导体衬底；
在所述半导体衬底上形成硬掩膜层，并在所述硬掩膜层中形成开口；
以所述硬掩膜层为掩膜对所述半导体衬底进行刻蚀，在所述半导体衬底内形成第一沟槽，所述第一沟槽的宽度大于所述硬掩膜层中的开口的宽度；
在所述第一沟槽的表面形成栅氧化层；
淀积第一层多晶硅并以所述硬掩膜层为掩膜对所述第一层多晶硅进行回刻，在所述第一沟槽的侧壁处形成栅极；
以所述硬掩膜层为掩膜对所述栅氧化层和所述半导体衬底进行刻蚀，在所述半导体衬底内形成第二沟槽，所述第二沟槽位于所述第一沟槽下方；
淀积一层氮化硅并回刻，在所述第一沟槽和所述第二沟槽内形成氮化硅侧墙；
以所述硬掩膜层和所述氮化硅侧墙为掩膜对所述半导体衬底进行刻蚀，在所述半导体衬底内形成第三沟槽，所述第三沟槽位于所述第二沟槽下方；
进行热氧化，在所述第三沟槽的表面形成第一场氧化层；
淀积形成第二场氧化层，所述第二氧化层和所述第一氧化层共同构成半导体功率器件的场氧化层；
淀积第二层多晶硅并回刻，在所述第三沟槽、第二沟槽和第一沟槽内形成屏蔽栅。
可选的，在形成所述第一场氧化层后，先刻蚀掉所述氮化硅侧墙，再淀积形成所述第二场氧化层。
可选的，在刻蚀形成所述第三沟槽时，通过增加横向的刻蚀，使得第三沟槽的宽度大于所述第二沟槽的宽度。
本发明实施例提供的一种半导体功率器件，采用本发明实施例提供的半导体功率器件的制造方法制造，包括：
n型漏区；
位于所述n型漏区之上的n型漂移区；
凹陷在所述n漂移区中的栅沟槽，所述栅沟槽自上而下包括栅沟槽上部、栅沟槽中部和栅沟槽下部三部分；
位于所述n型漂移区内且位于所述栅沟槽上部的两侧的p型体区；
位于所述p型体区内的n型源区；
位于所述栅沟槽上部的侧壁处的栅极，所述栅极通过栅氧化层与所述p型体区隔离；
位于所述栅沟槽下部内的屏蔽栅，所述屏蔽栅自下而上延伸至所述栅沟槽上部内，所述屏蔽栅通过场氧化层与所述n型漂移区和所述栅极隔离。
可选的，所述栅沟槽上部的宽度大于所述栅沟槽中部的宽度。
可选的，所述栅沟槽下部的宽度大于所述栅沟槽中部的宽度。
可选的，所述栅沟槽下部内的场氧化层的厚度大于所述栅沟槽上部和所述栅沟槽中部内的场氧化层的厚度。
可选的，还包括位于所述栅沟槽上部和所述栅沟槽中部内的氮化硅侧墙，所述氮化硅侧墙在所述栅沟槽上部内将所述场氧化层于所述栅极隔离，所述氮化硅侧墙在所述栅沟槽中部内将所述场氧化层与所述n型漂移区隔离。
本发明实施例提供的一种半导体功率器件的制造方法，首先，在第三沟槽表面氧化形成第一场氧化层时，栅极多晶硅被氮化硅侧墙保护不被氧化，保证了栅极多晶硅的宽度；其次，在氧化形成第一场氧化层后，再淀积形成第二场氧化层，可以使得第三沟槽内有更厚的场氧化层厚度，有利于改善栅沟槽底部的电荷平衡，提高半导体功率器件的耐压；再次，在刻蚀形成第三沟槽时，可以通过增加横向的刻蚀来增加第三沟槽的宽度，从而可以减小相邻的第三沟槽之间的n型漂移区的宽度，这有利于提高n型漂移区的掺杂浓度，降低半导体功率器件的导通电阻。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本发明提供的一种半导体功率器件的一个实施例的剖面结构示意图；
图2至图7是本发明提供的半导体功率器件的制造方法中的主要工艺技术节点结构的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体方式，完整地描述本发明的技术方案。应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列图形大小并不代表实际尺寸，说明书附图是示意性的，不应限定本发明的范围。
图1是本发明提供的一种半导体功率器件的一个实施例的剖面结构示意图，如图1所示，本发明实施例提供的一种半导体功率器件，包括n型漏区21；位于n型漏区21之上的n型漂移区22；凹陷在n漂移区22内的栅沟槽，该栅沟槽自上而下包括栅沟槽上部、栅沟槽中部和栅沟槽下部三部分；位于所述n型漂移区22内且位于栅沟槽上部的两侧的p型体区28；位于p型体区28内的n型源区29。
位于栅沟槽上部的侧壁处的栅极24，栅极24通过栅氧化层23与p型体区28隔离；位于栅沟槽下部内的屏蔽栅27，屏蔽栅27自下而上延伸至栅沟槽上部内，屏蔽栅27在栅沟槽下部内通过场氧化层26与n型漂移区22隔离，屏蔽栅27在栅沟槽中部内通过氮化硅侧墙25和场氧化层26与n型漂移区22隔离，屏蔽栅27在栅沟槽上部内通过氮化硅侧墙25和场氧化层26与栅极24隔离；其中氮化硅侧墙25为可选结构，即可以不形成氮化硅侧墙，从而，屏蔽栅27在栅沟槽中部内仅通过场氧化层26与n型漂移区22隔离，屏蔽栅27在栅沟槽上部内仅通过场氧化层26与栅极24隔离。
为简化本发明的半导体功率器件的制造工艺，可选的，栅沟槽上部的宽度大于所述栅沟槽中部的宽度。
可选的，栅沟槽下部的宽度大于栅沟槽中部的宽度，这可以减小相邻的栅沟槽下部之间的n型漂移区22的宽度，这有利于提高n型漂移区22的掺杂浓度，降低半导体功率器件的导通电阻。
可选的，栅沟槽下部内的场氧化层26的厚度大于栅沟槽上部和栅沟槽中部内的场氧化层26的厚度，这有利于改善栅沟槽底部的电荷平衡，提高半导体功率器件的耐压。
图2至图7是本发明提供的半导体功率器件的制造方法中的主要工艺技术节点结构的剖面结构示意图，首先如图2所示，提供一半导体衬底20，半导体衬底20的材质通常为硅且具有n型掺杂，在半导体衬底20上形成硬掩膜层30，并在硬掩膜层30中形成开口；然后以硬掩膜层30为掩膜对半导体衬底20进行刻蚀，在半导体衬底20内形成第一沟槽，在刻蚀形成第一沟槽时，通过增加横向的刻蚀，使得第一沟槽的宽度大于硬掩膜层30中的开口的宽度；第一沟槽即为本发明实施例的半导体功率器件的栅沟槽上部。
接下来，如图3所示，在第一沟槽的表面形成栅氧化层23，然后淀积第一层多晶硅并以硬掩膜层30为掩膜对所淀积形成的第一层多晶硅进行回刻，在第一沟槽的侧壁处形成栅极24。
接下来，如图4所示，以硬掩膜层30为掩膜对栅氧化层23和半导体衬底20进行刻蚀，在半导体衬底20内形成第二沟槽，第二沟槽位于所述第一沟槽下方且第二沟槽的宽度小于第一沟槽的宽度，第二沟槽即为本发明实施例的半导体功率器件的栅沟槽中部。
接下来，如图5所示，淀积一层氮化硅并回刻，在第一沟槽和第二沟槽内形成氮化硅侧墙25；然后以硬掩膜层30和氮化硅侧墙25为掩膜对半导体衬底20进行刻蚀，在半导体衬底20内形成第三沟槽，第三沟槽位于第二沟槽下方，第三沟槽即为本发明实施例的半导体功率器件的栅沟槽下部。在刻蚀形成第三沟槽时，通过增加横向的刻蚀来增加第三沟槽的宽度，使得第三沟槽的宽度大于第二沟槽的宽度，这可以减小相邻的第三沟槽之间的n型漂移区的宽度，有利于提高n型漂移区的掺杂浓度，降低半导体功率器件的导通电阻。
接下来，如图6所示，进行热氧化，在第三沟槽的表面形成第一场氧化层，此时由于氮化硅侧墙25的包含，栅极26不会被氧化；然后淀积形成第二场氧化层，所述第二氧化层和所述第一氧化层共同构成半导体功率器件的场氧化层26。通过先热氧化再淀积的方法形成场氧化层26，可以使得第三沟槽内有更厚的场氧化层厚度，有利于改善栅沟槽底部的电荷平衡，提高半导体功率器件的耐压。可选的，在形成所述第一场氧化层后，可以先刻蚀掉氮化硅侧墙25，再淀积形成所述第二场氧化层。
接下来，如图7所示，淀积第二层多晶硅并回刻，在所述第三沟槽、第二沟槽和第一沟槽内形成屏蔽栅27。
最后，通过现有技术的半导体功率器件的制造方法制备得到半导体功率器件的源极接触金属层、栅极接触金属层、n型漏区、漏极接触金属层等结构即可，本发明实施例中不再具体展示该步骤。
以上具体实施方式及实施例是对本发明技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (8)

1.半导体功率器件的制造方法，其特征在于，包括：
提供一半导体衬底；
在所述半导体衬底上形成硬掩膜层，并在所述硬掩膜层中形成开口；
以所述硬掩膜层为掩膜对所述半导体衬底进行刻蚀，在所述半导体衬底内形成第一沟槽，所述第一沟槽的宽度大于所述硬掩膜层中的开口的宽度；
在所述第一沟槽的表面形成栅氧化层；
淀积第一层多晶硅并以所述硬掩膜层为掩膜对所述第一层多晶硅进行回刻，在所述第一沟槽的侧壁处形成栅极；
以所述硬掩膜层为掩膜对所述栅氧化层和所述半导体衬底进行刻蚀，在所述半导体衬底内形成第二沟槽，所述第二沟槽位于所述第一沟槽下方；
淀积一层氮化硅并回刻，在所述第一沟槽和所述第二沟槽内形成氮化硅侧墙；
以所述硬掩膜层和所述氮化硅侧墙为掩膜对所述半导体衬底进行刻蚀，在所述半导体衬底内形成第三沟槽，所述第三沟槽位于所述第二沟槽下方；
进行热氧化，在所述第三沟槽的表面形成第一场氧化层；
淀积形成第二场氧化层，所述第二氧化层和所述第一氧化层共同构成半导体功率器件的场氧化层；
淀积第二层多晶硅并回刻，在所述第三沟槽、第二沟槽和第一沟槽内形成屏蔽栅。
2.如权利要求1所述的半导体功率器件的制造方法，其特征在于，在形成所述第一场氧化层后，先刻蚀掉所述氮化硅侧墙，再淀积形成所述第二场氧化层。
3.如权利要求1所述的半导体功率器件的制造方法，其特征在于，在刻蚀形成所述第三沟槽时，通过增加横向的刻蚀，使得第三沟槽的宽度大于所述第二沟槽的宽度。
4.如权利要求1所述的半导体功率器件的制造方法制造的半导体功率器件，其特征在于，包括：
n型漏区；
位于所述n型漏区之上的n型漂移区；
凹陷在所述n漂移区中的栅沟槽，所述栅沟槽自上而下包括栅沟槽上部、栅沟槽中部和栅沟槽下部三部分；
位于所述n型漂移区内且位于所述栅沟槽上部的两侧的p型体区；
位于所述p型体区内的n型源区；
位于所述栅沟槽上部的侧壁处的栅极，所述栅极通过栅氧化层与所述p型体区隔离；
位于所述栅沟槽下部内的屏蔽栅，所述屏蔽栅自下而上延伸至所述栅沟槽上部内，所述屏蔽栅通过场氧化层与所述n型漂移区和所述栅极隔离。
5.如权利要求4所述的半导体功率器件，其特征在于，所述栅沟槽上部的宽度大于所述栅沟槽中部的宽度。
6.如权利要求4所述的半导体功率器件，其特征在于，所述栅沟槽下部的宽度大于所述栅沟槽中部的宽度。
7.如权利要求4所述的半导体功率器件，其特征在于，所述栅沟槽下部内的场氧化层的厚度大于所述栅沟槽上部和所述栅沟槽中部内的场氧化层的厚度。
8.如权利要求4所述的半导体功率器件，其特征在于，还包括位于所述栅沟槽上部和所述栅沟槽中部内的氮化硅侧墙，所述氮化硅侧墙在所述栅沟槽上部内将所述场氧化层于所述栅极隔离，所述氮化硅侧墙在所述栅沟槽中部内将所述场氧化层与所述n型漂移区隔离。
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