WO2021164246A1 - 半导体功率器件 - Google Patents

半导体功率器件 Download PDF

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Publication number
WO2021164246A1
WO2021164246A1 PCT/CN2020/116681 CN2020116681W WO2021164246A1 WO 2021164246 A1 WO2021164246 A1 WO 2021164246A1 CN 2020116681 W CN2020116681 W CN 2020116681W WO 2021164246 A1 WO2021164246 A1 WO 2021164246A1
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gate
drift region
type drift
type
semiconductor power
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PCT/CN2020/116681
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English (en)
French (fr)
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龚轶
刘磊
刘伟
毛振东
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苏州东微半导体有限公司
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Publication of WO2021164246A1 publication Critical patent/WO2021164246A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Definitions

  • the present disclosure relates to the technical field of semiconductor power devices, for example, to a semiconductor power device including a multilayer n-type drift region.
  • Related-art semiconductor power devices usually form a trench in the epitaxial layer through a deep trench process, and form a reduced surface field (RESURF) structure in the vertical direction by filling a dielectric layer and a polysilicon shielding gate in the trench, thereby Improve the breakdown voltage and on-resistance of semiconductor power devices.
  • RESURF reduced surface field
  • the on-resistance of the semiconductor power device can be reduced, but the increase of the doping concentration of the epitaxial layer will make it difficult to deplete the charge at the bottom of the trench, and the electric field at the bottom of the trench is more concentrated , Making the semiconductor power device unable to obtain a higher breakdown voltage.
  • the present disclosure provides a semiconductor power device to solve the problem that the on-resistance and breakdown voltage of the related-art semiconductor power device are difficult to be adjusted at the same time.
  • the present disclosure provides a semiconductor power device, including:
  • n-type epitaxial layer and the n-type epitaxial layer:
  • the first n-type drift region, the second n-type drift region and the third n-type drift region from bottom to top, the doping concentration of the first n-type drift region and the doping of the third n-type drift region The concentration is greater than the doping concentration of the second n-type drift region;
  • At least one gate trench and a gate structure located in the gate trench, the bottom of the gate trench is not higher than the upper surface of the second n-type drift region;
  • a p-type body region located on both sides of the gate trench and above the third n-type drift region, and an n-type source region located in the p-type body region.
  • the bottom of the gate trench is not lower than the bottom surface of the second n-type drift region.
  • the bottom of the gate trench is lower than the bottom surface of the second n-type drift region, and the bottom of the gate trench is located in the first n-type drift region.
  • it further includes an n-type electric field modulation layer located in the third n-type drift region, and the doping concentration of the n-type electric field modulation layer is greater than the doping concentration of the third n-type drift region.
  • the gate structure includes a shield gate and a gate, and the gate, the shield gate, and the n-type epitaxial layer are separated by an insulating dielectric layer.
  • the gate is located in the upper part of the gate trench, and the shielding gate is located in the lower part of the gate trench.
  • the gate is located in the upper part of the gate trench
  • the shield gate is located in the lower part of the gate trench
  • the shield gate extends upward into the upper part of the gate trench.
  • the gate is located on both sides of the shield gate.
  • the gate surrounds the shield gate.
  • it further includes an n-type drain region, and the first n-type drift region is located on the n-type drain region.
  • the semiconductor power device provided by the present disclosure can increase the breakdown voltage of the semiconductor power device while reducing the on-resistance of the semiconductor power device.
  • FIG. 1 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor power device provided by the present disclosure
  • FIG. 2 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor power device provided by the present disclosure
  • FIG. 3 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor power device provided by the present disclosure.
  • FIG. 1 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor power device provided by the present disclosure
  • FIG. 2 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor power device provided by the present disclosure. As shown in FIG. 1 and FIG.
  • a semiconductor power device provided by the embodiment of the present invention includes: an n-type epitaxial layer, the material of the n-type epitaxial layer is usually silicon, which is located in the n-type epitaxial layer and is from bottom to top
  • the first n-type drift region 21, the second n-type drift region 22, and the third n-type drift region 23, the doping concentration of the first n-type drift region 21 and the doping concentration of the third n-type drift region 23 are all greater than The doping concentration of the second n-type drift region 22.
  • FIG. 1 only exemplarily shows three gate trenches, a gate structure located in the gate trench, the gate structure includes The gate 25, the shielding gate 27, the gate 25 are isolated from the n-type epitaxial layer by the gate dielectric layer 24, and the shielding gate 27 is isolated from the n-type epitaxial layer and the gate 25 by the field oxide layer 26.
  • the gate 25 is located in the upper part of the gate trench, and the shielding gate 27 is only located in the lower part of the gate trench. Therefore, the gate 25 and the shielding gate 27 are in an up-and-down structure relationship (this structure is described in the present invention). Not shown in the examples).
  • the gate 25 is located in the upper part of the gate trench
  • the shield gate 27 is located in the lower part of the gate trench
  • the shield gate 27 extends upward into the upper part of the gate trench, as shown in FIG. 1 .
  • the gate 25 can be located on both sides of the shielding gate 27, or the gate 25 can surround the shielding gate 27. This structure is It will not be shown in the embodiment of the present invention.
  • the bottom of the gate trench is not higher than the upper surface of the second n-type drift region 22, and the bottom of the gate trench may be flush with the upper surface of the second n-type drift region 22 (not shown in the figure); or
  • the bottom of the gate trench is lower than the upper surface of the second n-type drift region 22 and higher than or equal to the lower surface of the second n-type drift region 22, that is, the bottom of the gate trench is located in the second n-type drift region 22 (eg 1) or the bottom of the gate trench is level with the bottom surface of the second n-type drift region 22; the bottom of the gate trench may also be lower than the bottom surface of the second n-type drift region 22, so that the bottom surface of the gate trench The bottom is located in the first n-type drift region 21, as shown in FIG. 2.
  • a p-type body region 28 located on both sides of the gate trench and above the third n-type drift region 23, and an n-type source region 29 located in the p-type body region 28.
  • the semiconductor power device of the present disclosure further includes an n-type drain region 20, the first n-type drift region 21 is located on the n-type drain region 20, and the n-type drain region 20 is connected to the drain voltage through the drain metal layer.
  • the bottom of the gate trench is not higher than the upper surface of the second n-type drift region.
  • the bottom of the gate trench is located in the second n-type drift region or located in the second n-type drift region.
  • the second n-type drift region has a low doping concentration, the charge is easily depleted, which can increase the breakdown voltage of the semiconductor power device.
  • the doping concentration of the first n-type drift region and the doping concentration of the third n-type drift region are both greater than the doping concentration of the second n-type drift region, this can reduce the on-resistance of the semiconductor power device.
  • the embodiment of the present invention does not limit the size of the doping concentration of the first n-type drift region and the doping concentration of the third n-type drift region, and the doping concentration of the first n-type drift region may be greater than that of the third n-type drift region.
  • the doping concentration of the third n-type drift region can also be that the doping concentration of the third n-type drift region is greater than the doping concentration of the first n-type drift region, or the doping concentration of the third n-type drift region is equal to the first n-type drift region.
  • the doping concentration of the first n-type drift region is not limited in the embodiment of the present invention.
  • the doping concentration of the first n-type drift region and the doping concentration of the third n-type drift region are both greater than the doping concentration of the second n-type drift region.
  • the impurity concentration can ensure that the on-resistance of the semiconductor power device can be reduced.
  • FIG. 3 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor power device provided by the present disclosure.
  • an n-type electric field modulation layer 30 is also formed in the third n-type drift region 23.
  • the doping concentration of the electric field modulation layer 30 is greater than the doping concentration of the third n-type drift region 23 to increase the average value of the electric field of the third n-type drift region 23, which can further reduce the on-resistance of the semiconductor power device.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本文公开了一种半导体功率器件。该半导体功率器件包括：n型外延层，以及位于所述n型外延层内的：自下而上的第一n型漂移区、第二n型漂移区和第三n型漂移区，所述第一n型漂移区的掺杂浓度和所述第三n型漂移区的掺杂浓度均大于所述第二n型漂移区的掺杂浓度；至少一个栅沟槽以及位于所述栅沟槽内的栅极结构，所述栅沟槽的底部不高于所述第二n型漂移区的上表面；位于所述栅沟槽的两侧且位于所述第三n型漂移区之上的p型体区，以及位于所述p型体区中的n型源区。

Description

半导体功率器件
本申请要求在2020年02月21日提交中国专利局、申请号为202010106676.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体功率器件技术领域，例如涉及一种包含多层n型漂移区的半导体功率器件。
背景技术
相关技术的半导体功率器件通常是通过深沟槽工艺在外延层内形成沟槽，通过在沟槽内填充介质层与多晶硅屏蔽栅形成垂直方向的降低表面电场(Reduced Surface Field，RESURF)结构，从而改善半导体功率器件的击穿电压和导通电阻等性能。通过提高外延层的掺杂浓度可以降低半导体功率器件的导通电阻，但是外延层的掺杂浓度的提高会使得沟槽底部位置处的电荷难以耗尽，而沟槽底部位置处的电场比较集中，使得半导体功率器件无法得到更高的击穿电压。
发明内容
本公开提供了一种半导体功率器件，以解决相关技术的半导体功率器件的导通电阻和击穿电压难以同时调整的问题。
本公开提供了一种半导体功率器件，包括：
n型外延层，以及位于所述n型外延层内的：
自下而上的第一n型漂移区、第二n型漂移区和第三n型漂移区，所述第一n型漂移区的掺杂浓度和所述第三n型漂移区的掺杂浓度均大于所述第二n型漂移区的掺杂浓度；
至少一个栅沟槽以及位于所述栅沟槽内的栅极结构，所述栅沟槽的底部不高于所述第二n型漂移区的上表面；
位于所述栅沟槽的两侧且位于所述第三n型漂移区之上的p型体区，以及位于所述p型体区中的n型源区。
可选的，所述栅沟槽的底部不低于所述第二n型漂移区的下表面。
可选的，所述栅沟槽的底部低于所述第二n型漂移区的下表面，所述栅沟 槽的底部位于所述第一n型漂移区内。
可选的，还包括位于所述第三n型漂移区内的n型电场调制层，所述n型电场调制层的掺杂浓度大于所述第三n型漂移区的掺杂浓度。
可选的，所述栅极结构包括屏蔽栅和栅极，所述栅极、所述屏蔽栅和所述n型外延层两两之间由绝缘介质层隔离。
可选的，所述栅极位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内。
可选的，所述栅极位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内且所述屏蔽栅向上延伸至所述栅沟槽的上部内。
可选的，在所述栅沟槽的上部内，所述栅极位于所述屏蔽栅的两侧。
可选的，在所述栅沟槽的上部内，所述栅极环绕包围所述屏蔽栅。
可选的，还包括n型漏区，所述第一n型漂移区位于所述n型漏区之上。
本公开提供的一种半导体功率器件在降低半导体功率器件的导通电阻的同时还可以提高半导体功率器件的击穿电压。
附图说明
图1是本公开提供的一种半导体功率器件的第一个实施例的剖面结构示意图；
图2是本公开提供的一种半导体功率器件的第二个实施例的剖面结构示意图；
图3是本公开提供的一种半导体功率器件的第三个实施例的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体方式，描述本公开的技术方案。本公开所使用的诸如“具有”、“包含”以及“包括”等术语并不排除一个或多个其它元件或其组合的存在或添加。同时，为说明本公开的具体实施方式，附图中所列示意图，放大了本公开所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图1是本公开提供的一种半导体功率器件的第一个实施例的剖面结构示意图，图2是本公开提供的一种半导体功率器件的第二个实施例的剖面结构示意图。如图1和图2所示，本发明实施列提供的一种半导体功率器件包括：n型外 延层，n型外延层的材质通常为硅，位于所述n型外延层内且自下而上的第一n型漂移区21、第二n型漂移区22和第三n型漂移区23，第一n型漂移区21的掺杂浓度和第三n型漂移区23的掺杂浓度均大于第二n型漂移区22的掺杂浓度。
凹陷在所述n型外延层内的至少一个栅沟槽，图1中仅示例性的示出了3个栅沟槽，位于所述栅沟槽内的栅极结构，所述栅极结构包括栅极25、屏蔽栅27，栅极25通过栅介质层24与n型外延层隔离，屏蔽栅27通过场氧化层26与n型外延层和栅极25隔离。可选的，在栅沟槽内，栅极25位于栅沟槽上部内，屏蔽栅27仅位于栅沟槽下部内，由此栅极25和屏蔽栅27为上下结构关系(该结构在本发明实施例中未示出)。可选的，在栅沟槽内，栅极25位于栅沟槽的上部内，屏蔽栅27位于栅沟槽的下部内且屏蔽栅27向上延伸至栅沟槽的上部内，如图1所示。当屏蔽栅27向上延伸至栅沟槽的上部内时，在栅沟槽的上部内，栅极25可以是位于屏蔽栅27两侧，也可以是栅极25环绕包围屏蔽栅27，该结构在本发明实施例中不再展示。
栅沟槽的底部不高于第二n型漂移区22的上表面，可以是栅沟槽的底部与第二n型漂移区22的上表面齐平(图中未示出)；也可以是栅沟槽的底部低于第二n型漂移区22的上表面并高于或等于第二n型漂移区22的下表面，即栅沟槽的底部位于第二n型漂移区22内(如图1所示)或者栅沟槽的底部与第二n型漂移区22的下表面持平；栅沟槽的底部也可以是低于第二n型漂移区22的下表面，使得栅沟槽的底部位于第一n型漂移区21内，如图2所示。
位于所述栅沟槽的两侧且位于第三n型漂移区23之上的p型体区28，以及位于p型体区28中的n型源区29。
本公开的半导体功率器件还包括n型漏区20，第一n型漂移区21位于n型漏区20之上，n型漏区20通过漏极金属层外接漏极电压。
本公开的半导体功率器件，使栅沟槽的底部不高于第二n型漂移区的上表面，例如使栅沟槽的底部位于第二n型漂移区内或者位于第二n型漂移区的附近，由于第二n型漂移区具有低的掺杂浓度，因此电荷容易耗尽，可以提高半导体功率器件的击穿电压。同时，由于第一n型漂移区的掺杂浓度和第三n型漂移区的掺杂浓度均大于第二n型漂移区的掺杂浓度，这可以降低半导体功率器件的导通电阻。
本发明实施例对第一n型漂移区的掺杂浓度和第三n型漂移区的掺杂浓度的大小不进行限定，可以是第一n型漂移区的掺杂浓度大于第三n型漂移区的掺杂浓度，也可以是第三n型漂移区的掺杂浓度大于第一n型漂移区的掺杂浓度，还可以是第三n型漂移区的掺杂浓度等于第一n型漂移区的掺杂浓度，本 发明实施例对此不进行限定，只需保证第一n型漂移区的掺杂浓度和第三n型漂移区的掺杂浓度均大于第二n型漂移区的掺杂浓度，保证可以降低半导体功率器件的导通电阻即可。
图3是本公开提供的一种半导体功率器件的第三个实施例的剖面结构示意图，在该实施例中，在第三n型漂移区23内还形成有n型电场调制层30，n型电场调制层30的掺杂浓度大于第三n型漂移区23的掺杂浓度，用以提升第三n型漂移区23的电场均值，这可以进一步降低半导体功率器件的导通电阻。

Claims (10)

  1. 半导体功率器件，包括：
    n型外延层，以及位于所述n型外延层内的：
    自下而上的第一n型漂移区、第二n型漂移区和第三n型漂移区，所述第一n型漂移区的掺杂浓度和所述第三n型漂移区的掺杂浓度均大于所述第二n型漂移区的掺杂浓度；
    至少一个栅沟槽以及位于所述栅沟槽内的栅极结构，所述栅沟槽的底部不高于所述第二n型漂移区的上表面；
    位于所述栅沟槽的两侧且位于所述第三n型漂移区之上的p型体区，以及位于所述p型体区中的n型源区。
  2. 如权利要求1所述的半导体功率器件，其中，所述栅沟槽的底部不低于所述第二n型漂移区的下表面。
  3. 如权利要求1所述的半导体功率器件，其中，所述栅沟槽的底部低于所述第二n型漂移区的下表面，所述栅沟槽的底部位于所述第一n型漂移区内。
  4. 如权利要求1所述的半导体功率器件，还包括位于所述第三n型漂移区内的n型电场调制层，所述n型电场调制层的掺杂浓度大于所述第三n型漂移区的掺杂浓度。
  5. 如权利要求1所述的半导体功率器件，其中，所述栅极结构包括屏蔽栅和栅极，所述栅极、所述屏蔽栅和所述n型外延层两两之间由绝缘介质层隔离。
  6. 如权利要求5所述的半导体功率器件，其中，所述栅极位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内。
  7. 如权利要求5所述的半导体功率器件，其中，所述栅极位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内且所述屏蔽栅向上延伸至所述栅沟槽的上部内。
  8. 如权利要求7所述的半导体功率器件，其中，在所述栅沟槽的上部内，所述栅极位于所述屏蔽栅的两侧。
  9. 如权利要求7所述的半导体功率器件，其中，在所述栅沟槽的上部内，所述栅极环绕包围所述屏蔽栅。
  10. 如权利要求1所述的半导体功率器件，还包括n型漏区，所述第一n型漂移区位于所述n型漏区之上。
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