TWI512844B - 利用耗盡ｐ－屏蔽的低輸出電容的高頻開關ｍｏｓｆｅｔ - Google Patents

利用耗盡ｐ－屏蔽的低輸出電容的高頻開關ｍｏｓｆｅｔ Download PDF

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TWI512844B
TWI512844B TW102145737A TW102145737A TWI512844B TW I512844 B TWI512844 B TW I512844B TW 102145737 A TW102145737 A TW 102145737A TW 102145737 A TW102145737 A TW 102145737A TW I512844 B TWI512844 B TW I512844B
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trench
layer
region
gate
insulating
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TW102145737A
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TW201426881A (zh
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Madhur Bobde
Hamza Yilmaz
Sik Lui
Daniel Ng
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Alpha & Omega Semiconductor
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Description

利用耗盡P-屏蔽的低輸出電容的高頻開關
本發明涉及金屬氧化物半導體場效應晶體管(MOSFET)，更確切地說是基於高密度溝槽的功率MOSFET。
低壓功率MOSFET通常用於負載開關器件。在負載開關器件中，要求必須降低器件的導通電阻(Rds )。確切地說，應該是器件的Rds A必須最小，其中Rds A就是器件的導通電阻與器件的有源區面積的乘積。另外，低壓功率MOSFET常用於高頻直流-直流器件。在這些應用中，通常要求器件的開關速度達到最大。優化開關速度最關鍵的三個因素為：1)Rds ×Qg ；2)Rds ×Qoss ；以及3)Qgd /Qgs 之比。首先，Rds 和閘極電荷(Qg )的乘積可測試器件傳導和開關的共同損耗。Qg 為閘汲電荷(Qgd )和閘源電荷(Qgs )之和。在第二個參數中，輸出電荷Qoss用於測量當器件接通或斷開時，需要充電和放電的電容。最後，使Qgd /Qgs 的比值最小，當器件斷開時，可以減少由很大的dV/dt導致器件接通的可能性。
如圖1A所示，設計基於溝槽的MOSFET的目的之一是降低器件的RdsA 。基於溝槽的MOSFET可以除去平面型MOSFET中原有的JFET結構通過除去JFET，可以降低晶胞間距。然而，基本的基於溝槽的MOSFET在本體區中不具備任何電荷平衡，從而增大了Rds A。而且，閘極氧化物比較薄，在溝槽下方產生很高的電場，致使擊穿電壓較低。為了承載電壓，漂流區中的摻雜濃度必須很低，從而對於帶有較薄閘極氧化物的結構來說，增大了Rds A。另外，由於很難進一步減小閘極氧化物的厚度，所以隨著晶胞間距持續減小，基於溝槽的MOSFET並非是一個理想的選擇。
人們一直試圖利用各種方法，解決上述問題。圖1B表示Baliga在美國專利號5,998,833中提出的第一種示例--屏蔽閘MOSFET。 利用一個連接到源極電勢的基於溝槽的屏蔽電極，代替較大的閘極電極，降低了MOSFET的閘汲電容(Cgd)，在高頻操作時，通過減少閘極放電和充電的電量，提高了開關速度。然而，由於源極電勢通過屏蔽電極電容耦合到汲極，因此Baliga提出的MOSFET器件具有很高的輸出電容。而且，為了承載閉鎖電壓，需要很厚的氧化物。最後，為了在同一個溝槽中，制備兩個電氣性分隔的多晶矽電極，需要進行複雜的工藝。當器件的間距縮至很深的亞微米級別時，制備的複雜性將進一步增大。
最後，Temple在美國專利申請號4,941,026中提出的圖1C所示的MOSFET設計圖，具有有利於優化器件開關特性的某些特點。Temple提出的器件利用二階閘極氧化物，在閘極頂部附近具有薄氧化層，在閘極底部具有厚氧化層，以便制成低通道電阻和低漂流電阻的器件。閘極頂部的薄氧化物可以在閘極和本體區之間提供良好的耦合，在薄氧化物附近的溝槽中，產生很強的反轉以及低導通電阻。閘極底部較厚的閘極氧化物產生電荷平衡效果，使得漂流區的摻雜濃度增高。漂流區中較高的摻雜濃度降低了它的電阻。
然而，由於圖1C所示器件對本體接觸區的失准誤差高度敏感，並不能輕鬆地減小它的尺寸。例如，如果器件的間距尺寸降至深亞微米級別(例如0.5-0.6μm)，那麼接觸掩膜的失准就相當於閘極的失准，可能會對器件的性能造成很大的影響。為了形成到本體區良好的歐姆接觸，在使用接觸掩膜之後，注入歐姆接觸區，其中歐姆接觸區用導電類型與本體區相同的摻雜物重摻雜。如果接觸掩膜中的開口對準得太靠近閘極，也就是說不是准確地位於矽臺面結構的中心，那麼使用摻雜層注入，形成同本體產生歐姆接觸區後，注入的重摻雜物會終止在通道中。如果重摻雜歐姆接觸區處於通道中，那麼器件的閾值電壓和導通電阻將受到影響。而且，如果接觸掩膜對準得離閘極過遠，那麼雙極結型晶體管(BJT)的接通將成為一個問題。因為如果接觸離溝槽較遠的話，本體區的長度及其電阻都會增大。隨著本體區電阻的增大，落在本體區的電壓也會增大。本體區上較大的壓降將更容易地接通寄生BJT，對器件造成損壞。
因此，為了制備深亞微米器件，優化後作為負載開關和高頻 直流-直流器件，必須使用將接觸自對準到閘極的器件和方法，以避免上述不良效果。
正是在這一前提下，提出了本發明的實施例。
本发明提供了一種用於制備MOSFET器件的方法，包括：a)在第一導電類型的半導體襯底頂面上方，制備一個硬掩膜，其中硬掩膜包括第一和第二絕緣層，其中第二絕緣層抵抗刻蝕第一絕緣層的第一次刻蝕工藝，第一絕緣層可以抵抗刻蝕第二絕緣層的第二次刻蝕工藝；b)通過硬掩膜中的開口，刻蝕半導體襯底，以便在半導體襯底中形成多個溝槽，其中溝槽包括溝槽頂部和溝槽底部；c)用第一厚度T1的頂部絕緣層內襯溝槽頂部，用第二厚度T2的底部絕緣層內襯溝槽底部，其中T2大於T1；d)在溝槽中沉積導電材料，形成多個閘極電極；e)在閘極電極上方制備絕緣閘極蓋至少達到硬掩膜第二絕緣層的水平處，其中絕緣閘極蓋由可以被第一次刻蝕工藝刻蝕，同時抵抗第二次刻蝕工藝的材料制成；f)利用第一次刻蝕工藝，除去硬掩膜的第一絕緣層，保留與溝槽對準的絕緣閘極蓋，絕緣閘極蓋突出至硬掩膜第二絕緣層的上方；g)在襯底頂部，制備一個本體層，其中本體層為與第一導電類型相反的第二導電類型；h)制備一個第二導電類型的耗盡屏蔽區，在半導體襯底的深處，至少部分在溝槽底面以下，其中耗盡屏蔽區電連接到本體層；i)在硬掩膜的第二絕緣層和絕緣閘極蓋上方，制備一個絕緣墊片層；j)在絕緣墊片層上方，制備一個導電或半導體墊片層，並且各向異性地刻蝕導電或半導體墊片層和絕緣墊片層，保留沿著絕緣閘極蓋側壁的那部分導電或半導體墊片層和絕緣墊片層，作為導電或半導體墊片和絕緣墊片；並且 k)利用導電或半導體墊片作為自對準掩膜，在半導體襯底中形成開口，用於源極接觸。
上述的方法，其中一個或多個耗盡屏蔽區穿過襯底延伸到第一導電類型的汲極區中，汲極區形成在襯底底部。
上述的方法，其中一個或多個耗盡屏蔽區完全形成在溝槽底面以下。
上述的方法，其中耗盡屏蔽區和本體層之間的連接建立在器件的一個主平面中。
上述的方法，其中耗盡屏蔽區和本體層之間的連接建立在器件的二次平面中，其中器件的二次平面和器件的主平面正交。
上述的方法，其中一部分耗盡屏蔽區未連接到本體層，其中配置一部分襯底，將耗盡屏蔽區未連接到本體層的部分與耗盡屏蔽區連接到本體層的部分隔開，以便將溝槽附近第一導電類型的外延區，連接到襯底底部第一導電類型的汲極區。
上述的方法，其中耗盡屏蔽區的未連接到本體層的部分繼續延伸到主平面中的兩個或多個溝槽以下，與外延區連接到汲極區的部分襯底形成正交的超級結結構。
上述的方法，其中制備多個溝槽包括穿過硬掩膜和襯底中的開口刻蝕，形成溝槽的頂部；沿溝槽頂部的側壁和底面生長一個頂部絕緣層，並且沿側壁在頂部絕緣層上制備墊片；將墊片作為掩膜，刻蝕沉積在溝槽頂部底面上的絕緣層，以及溝槽頂部下方的襯底，形成溝槽的底部；沿溝槽底部的側壁和底面，生長底部絕緣層；並且除去墊片。
上述的方法，其中制備多個溝槽包括穿過硬掩膜和襯底中的開口刻蝕，形成溝槽的頂部和底部；沿溝槽頂部和底部的側壁和底面生長一個底部絕緣層；用第一部分導電材料填充溝槽底部；從溝槽頂部除去底部絕緣層；沿溝槽頂部側壁以及沿溝槽底部中導電材料的頂面，生長頂部絕緣層；利用第二部分導電材料在頂部絕緣層上沿側壁形成墊片；並且從溝槽底部中導電材料的頂面上刻蝕掉頂部絕緣層。
上述的方法，還包括：在襯底頂部，制備一個第一導電類型的源極區。
上述的方法，其中在襯底中制備多個溝槽還包括制備一個或多個閘極拾取溝槽，其中在溝槽中沉積導電材料還包括在閘極拾取溝槽中沉積導電材料，以形成閘極拾取電極。
上述的方法，其中一個或多個閘極拾取溝槽形成在第二導電類型的摻雜槽中，摻雜槽形成在半導體襯底中。
上述的方法，還包括：在通過硬掩膜的第一層上方沉積一層導電材料，並且利用ESD掩膜和ESD刻蝕工藝，除去硬掩膜的第一層之前，先在硬掩膜的第一層上方，制備一個靜電放電(ESD)保護電極。
上述的方法，還包括在除去硬掩膜的第二層之前，先氧化ESD保護電極的表面。
上述的方法，還包括：配置一個或多個肖特基接觸結構，以終止器件，其中制備肖特基接觸結構還包括制備一個或多個本體鉗位(BCL)結構。
上述的方法，還包括：在半導體襯底中的開口附近，制備一個歐姆接觸區，用於源極接觸，其中歐姆接觸區具有高濃度的第二導電類型摻雜物。
本发明还提供了一種MOSFET器件，包括：一個第一導電類型的半導體襯底，其中襯底包括一個輕摻雜的外延區，在襯底頂部；一個第二導電類型的本體區，形成在半導體襯底頂部，其中第二導電類型與第一導電類型相反；半導體襯底和本體區構成的多個有源器件結構，其中每個有源器件結構都含有一個與閘極氧化物絕緣的閘極電極，其中閘極氧化物頂部的厚度為T1，閘極氧化物底部的厚度為T2，其中T2大於T1；一個第二導電類型的耗盡屏蔽區形成在半導體襯底中，在半導體襯底的深處，至少部分在溝槽底面以下，其中耗盡屏蔽區電連接到本體層；一個絕緣閘極蓋形成在每個閘極電極上方，其中絕緣墊片形成在絕緣閘極蓋的側壁上，導 電或半導體墊片形成在絕緣墊片的裸露側壁上，絕緣層在本體區的頂面上；一個導電源極金屬層形成在絕緣層上方；一個或多個電連接，將源極金屬層與一個或多個源極區連接起來，其中絕緣墊片將一個或多個電連接與絕緣閘極蓋分開。
上述的方法，其中耗盡屏蔽區中的一個或多個耗盡屏蔽區穿過襯底延伸到襯底底部第一導電類型的汲極區。
上述的方法，其中一個或多個耗盡屏蔽區全部形成在溝槽的底面以下。
上述的方法，其中耗盡屏蔽區和本體層之間的連接在器件的主平面中。
上述的方法，其中耗盡屏蔽區和本體層之間的連接在器件的二次平面中，其中器件的二次平面與器件的主平面正交。
上述的方法，其中一部分耗盡屏蔽區未連接本體層，其中配置一部分襯底，將耗盡屏蔽區未連接本體層的部分與耗盡屏蔽區的連接本體層的部分隔開，以便將溝槽附近第一導電類型的外延區，連接到襯底底部第一導電類型的汲極區。
上述的方法，其中耗盡屏蔽區的未連接本體層的部分繼續延伸到主平面中的兩個或多個溝槽以下，與將外延區連接到汲極區的部分襯底形成正交超級結結構。
上述的MOSFET器件，其中導電或半導體墊片為多晶矽墊片，其中用第一導電類型的摻雜物摻雜多晶矽墊片。
上述的MOSFET器件，還包括：多個第一導電類型的源極區，形成在多個溝槽附近的半導體襯底頂部。
上述的MOSFET器件，還包括一個或多個靜電放電(ESD)保護結構。
上述的MOSFET器件，還包括一個或多個閘極拾取溝槽。
上述的MOSFET器件，還包括一個肖特基接觸結構，其中肖特基接觸結構還包括一個本體鉗位結構。
374‧‧‧閘極氧化物
307‧‧‧外延層
300‧‧‧器件
391‧‧‧積累區
344‧‧‧耗盡的P-屏蔽區
303‧‧‧汲極端P-本體層
317‧‧‧源極金屬
309‧‧‧閘極電極
370‧‧‧溝槽
301‧‧‧襯底
302‧‧‧N+ 汲極區
304‧‧‧N+ -摻雜源極區
342‧‧‧N+ -摻雜多晶矽墊片
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355‧‧‧絕緣層
341‧‧‧絕緣墊片
345‧‧‧P-連接器區
300’‧‧‧器件
300”‧‧‧器件
346‧‧‧N-連接區
300’”‧‧‧器件
361‧‧‧P深摻雜區
389‧‧‧自對準接觸開口
357‧‧‧導電插頭
343‧‧‧歐姆接觸區
395‧‧‧ESD保護結構
396‧‧‧導電材料
321‧‧‧金屬接觸結構
325‧‧‧肖特基金屬
322‧‧‧閘極拾取電極
320‧‧‧電連接結構
324‧‧‧閘極金屬
397‧‧‧絕緣層
370’‧‧‧閘極拾取溝槽
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319‧‧‧閘極滑道
500‧‧‧器件結構
501‧‧‧襯底
502‧‧‧汲極接觸區
507‧‧‧外延層
561‧‧‧重摻雜P-槽
556‧‧‧第一絕緣層
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570‧‧‧溝槽
570’‧‧‧閘極拾取溝槽
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508‧‧‧絕緣閘極蓋
544‧‧‧耗盡P-屏蔽區
545‧‧‧P-連接器區
576‧‧‧N-連接區
503‧‧‧P-本體層
504‧‧‧N+ -源極區
541‧‧‧絕緣墊片
517‧‧‧源極金屬
542‧‧‧多晶矽墊片
547‧‧‧自對準接觸開口
543‧‧‧歐姆接觸區
595‧‧‧ESD結構
596‧‧‧ESD二極管
597‧‧‧絕緣層
516‧‧‧光致抗蝕劑層
520‧‧‧接觸結構
557‧‧‧源極接觸結構
524‧‧‧閘極金屬
525‧‧‧肖特基金屬
601‧‧‧襯底
670、670’‧‧‧溝槽
656‧‧‧第一絕緣層
655‧‧‧第二絕緣層
602‧‧‧重摻雜N+ 汲極區
607‧‧‧外延層
770‧‧‧溝槽
770’‧‧‧溝槽
700‧‧‧器件
761‧‧‧P-槽
674‧‧‧絕緣層
6091‧‧‧第一部分
672‧‧‧底部
671‧‧‧頂部
673‧‧‧頂部絕緣層
673’‧‧‧絕緣層
6092‧‧‧第二部分
6093‧‧‧第三部分
圖1A-1C表示原有技術的MOSFET器件。
圖2A-2C表示依據本發明的各個方面，用於解釋MOSFET器件電學性能的圖表及圖形。
圖3A-1到3F表示依據本發明的各個方面，多種MOSFET器件的剖面圖。
圖4表示依據本發明的各個方面，MOSFET器件架空布局的模式。
圖5A-5J表示依據本發明的各個方面，MOSFET器件制備方法的剖面圖。
圖6A-6E表示依據本發明的各個方面，二階氧化物的可選制備方法的剖面圖。
盡管為了解釋說明，以下詳細說明包含了許多具體細節，但是本領域的技術人員應明確以下細節的各種變化和修正都屬於本發明的範圍。因此，提出以下本發明的典型實施例，並沒有使所聲明的方面損失任何普遍性，也沒有提出任何局限。在下文中，N型器件用於解釋說明。利用相同的工藝，相反的導電類型，就可以制備P型器件。
依據本發明的各個方面，可以通過自對準的源極接觸，制備基於高密度溝槽的功率MOSFET。源極接觸與導電或半導體墊片自對準。墊片沿閘極蓋的側壁形成。另外，有源器件具有二階閘極氧化物，其中閘極氧化物的底部厚度為T2 ，閘極氧化物的頂部厚度為T1 ，T2 大於T1 。二階閘極氧化物與自對準源極接觸相結合，用於制備尺寸可大幅縮減的器件，有源器件間距在深亞微米級別，例如0.5-0.6微米。
本發明的其他方面提出了一種類似的器件，這種器件在矽外延部分中沒有源極區。依據本發明的這一方面，半導體墊片，例如N+ -摻雜多晶矽墊片，也可以作為源極區，因此可以不必在襯底中添加源極區。本發明的其他方面提出了一種類似的器件，通過將摻雜物從摻雜多晶矽墊片擴散到器件的矽外延部分中，所形成的器件源極區形成在器件的矽外延部 分中。
二階閘極氧化物使得閘極氧化物374的底部承載絕大部分的電壓，從而減少外延層307必須承載的電壓。圖2A表示有源器件的剖面圖，顯示出電場強度，其中陰影越暗表示電場強度越大。如圖中沿溝槽底部的深色陰影所示，閘極氧化物374的底部承載了電場的絕大部分。圖2B表示器件300閉鎖的電壓與襯底中深度的關系圖。器件300在0.5微米左右的深度上開始閉鎖電壓。該深度與閘極氧化物374的底部開始厚度為T2 處的深度是一致的。在溝槽底部和氧化物374附近(約1.0微米)，器件總共閉鎖了18V左右，大幅減少了外延層307的電壓閉鎖負擔。因此，可以增大外延漂流層307的摻雜濃度，以降低器件的Rds A。外延層307摻雜濃度的增大，以及較小的晶胞間距導致較低的通道電阻，使得當該器件承載與圖1A所示相同的電壓時，與原有技術基於溝槽的MOSFET相比，RdsA 下降約90%或更多，當該器件承載與圖1B所示相同的電壓時，與原有技術的分裂閘極MOSFET相比，RdsA 下降約37%或更多。
器件的RdsA 會因積累區391的位置進一步降低。如圖2C所示，當閘極接通時，一個很窄的積累區391形成在溝槽側壁附近的外延層307頂部。作為示例，積累區391的寬度約為300-400Å。沿積累區的電荷載流子濃度降低了外延層307頂部的電阻。此外，由於積累區391很薄，只要晶胞間距大於積累區391的寬度，那麼減小晶胞間距就不會影響電阻。參見圖1B，上述分裂閘極MOSFET器件並不具備這種特性。在分裂閘極MOSFET器件中，溝槽底部的導體保持在源極電勢，防止沿側壁附近的狹窄路徑形成積累區391。因此，將分裂閘極MOSFET的間距縮減至深亞微米級別並不現實。
由於增加一個耗盡的P-屏蔽區344或屏蔽結構，通過汲極端P-本體層303的連接，使耗盡的P-屏蔽區344電連接到源極金屬317，降低了器件的閘汲耦合，從而改善了器件的開關速度。用於降低閘汲耦合的非耗盡結構(例如分裂閘極器件)，是以大幅提高器件的輸出電容為代價的。然而，使用耗盡的P-屏蔽區344降低閘汲耦合，只會使輸出電容小幅增大。這是由於在低汲極偏壓下，P-屏蔽區344與閘極電極309的耦合更接近於常 用的分裂閘極器件，降低了閘汲耦合，從而產生這種效果。與常用的分裂閘極器件不同，當汲極處於高偏壓時，P-屏蔽區344耗盡，從而產生一個N-摻雜外延層307的電荷平衡區。通過增大電介質寬度，完全耗盡的外延層307降低了器件的輸出電容。
圖3A-1及3A-2表示依據本發明的各個方面，器件結構300的剖面圖。右側3A-2的剖面圖表示MOSEET器件300的主平面(Primary plane)視圖，左側的剖面圖3A-1表示MOSET器件的二次平面(Secondary plane)視圖。主平面和二次平面相互正交，主平面用X-Y平面表示，二次平面用Z-Y平面表示。因此，二次平面使得第三維度的視圖隱藏在主平面中。在一些僅作為示範但不構成限制性的實施例中，作為理解主平面、二次平面的途徑，本發明提及的主平面可認為是垂直於襯底所在平面且正交於溝槽370長度方向的平面，二次平面可認為是垂直於襯底所在平面且平行於溝槽370長度方向的平面，可參考圖4的俯視圖。器件結構300位於半導體襯底301上。襯底301可以適當摻雜為N-型或P-型襯底。作為示例，但不作為局限，半導體襯底301可以是N-型襯底。半導體襯底具有一個重摻雜的N+ 汲極區302。在汲極區302上方的是輕摻雜N-型外延層307。在外延層307頂部，形成一個適當摻雜的P-本體層303。在本體層303頂部，形成一個N+ -摻雜源極區304。然而，由於N-型摻雜物的濃度很高，N+-摻雜多晶矽墊片342可以作為源極區，從而可以省去源極區304。
依據本發明的各個方面，器件結構300的有源區包括多個基於溝槽的MOSFET。通過制備穿過P-本體層303或稱本體區延伸到外延層307中的溝槽370，形成基於溝槽的MOSFET。每個溝槽都含有頂部371和底部372。厚度為T1 的頂部絕緣層373內襯在溝槽頂部371，厚度為T2 的底部絕緣層374內襯在溝槽底部372。依據本發明的各個方面，厚度T1 小於厚度T2 。作為示例，頂部和底部絕緣層可以是氧化物。用適當的材料填充溝槽的剩餘部分，構成一個閘極電極309。作為示例，閘極電極309可以用多晶矽制備。雖然圖3A-1或3A-2沒有表示出來，但是閘極電極309連接到閘極墊，並且維持在閘極電勢。每個閘極電極309都通過設置在溝槽上方的絕緣閘極蓋308，與源極金屬317材料電絕緣。絕緣層355也可以形成在源 極區304上方。通過沿閘極蓋308的垂直邊緣形成一個絕緣墊片341，可以降低閘極電極309短接至源極金屬317上的可能性。作為示例，絕緣墊片341可以是氧化物。實際上，如果自對準接觸幹刻蝕進一步減薄了拐角處的氧化物，導致泄漏增加，那麼閘極多晶矽和源極金屬之間的薄閘極氧化物就不足以提供絕緣。
一個或多個重摻雜耗盡P-屏蔽區344形成在溝槽370的深度以下。文中所述的溝槽370的深度以下包括在溝槽下方的位置，以及偏離溝槽的位置。另外，P-屏蔽區344的頂部可以延伸到溝槽370底面的上方。P-屏蔽區344所選的摻雜濃度會在汲極偏壓達到最大汲源電壓的50%時，使P-屏蔽區344完全耗盡。作為示例，但不作為局限，P-屏蔽區344的摻雜濃度範圍為5×1015 cm-3 -5×1016 cm-3 。P-屏蔽區344向下延伸到接觸汲極區302，或者在觸及汲極接觸302之前就終止。通過P-本體層303的連接，P-屏蔽區344電連接到源極金屬317上。在圖3A-1中，二次平面的剖面圖中可以看到連接。耗盡的P-屏蔽區344在Z-方向上延伸，直到觸及P-連接器區345。P-連接器區345是一個用P-型摻雜物摻雜的區域，在P-本體層303和耗盡的P-屏蔽區344之間提供連接。由於P-連接器區345也會在高汲極偏壓下基本耗盡，因此可以作為P-屏蔽區的一部分。
依據本發明的另一方面，器件結構300’也可以在MOSFET器件300’主平面中的耗盡P-屏蔽區344和P-本體層303之間制成P-連接器區345。圖3B表示與圖3A-1所示器件300基本類似的結構300’，但是耗盡P-屏蔽區在X-Y平面中具有P-連接器區345，連接P-本體層303和耗盡的P-屏蔽區344。雖然，P-連接器區345在溝槽370之間延伸，但是仍然有部分N-外延層307在溝槽370的側壁附近。
依據本發明的另一方面，圖3C-1和3C-2表示器件300”。器件300”含有一個N-連接區346，將外延層307連接到汲極區302。從主平面上觀察的話，器件300”與器件300類似。然而，從二次平面觀察的話，可以看到N-連接區346穿過P-屏蔽區344延伸。將外延層307連接到汲極區可防止在器件有源區中產生浮動區，影響開關時Rds.on等器件性能。
依據本發明的另一方面，圖3D-1和3D-2表示器件300’”。 器件300’”利用正交超級結結構。超級結結構通常包括P-型和N-型摻雜立柱交替形成在器件的外延層中。在MOSFET斷開狀態時，立柱在較低的電壓下完全耗盡，從而保持了較高的擊穿電壓。如圖中主平面所示，P-屏蔽區344在溝槽370下面沿X-方向連續延伸。而且要注意的是，P-屏蔽區344的頂部可以延伸到溝槽370的底面上。N-型和P-型交替立柱形成在Z-方向上。從二次平面上觀察，N-連接區346作為超級結器件的N-型摻雜立柱。部分P-屏蔽區通過P-連接器區345連接到P-本體層303。X-Y平面中所示的那部分P-屏蔽區344可以連接到深P-槽或說P深摻雜區361(圖中沒有表示出)。
參見圖3A-2，通過襯底中穿過絕緣層355和源極區304延伸的自對準接觸開口389，源極區304電連接到源極金屬317。沿絕緣墊片341的裸露側壁形成在N+ -摻雜多晶矽墊片342，使接觸開口389自對準。這些墊片作為刻蝕的掩膜層，用於形成接觸開口389。N+ -摻雜多晶矽墊片342通過增加到源極的接觸面積，降低了接觸電阻，有利於形成歐姆接觸。作為示例，但不作為局限，電連接結構可以通過導電插頭357形成。作為示例，但不作為局限，導電插頭357可以由鎢等導電材料制成。增加一個歐姆接觸區343，可以改善導電插頭357和P-本體層303之間的歐姆接觸。歐姆接觸區為重摻雜P-區，形成在自對準接觸開口389的裸露表面上。作為示例，通過注入摻雜濃度約為1019 cm-3 的P-型摻雜物(例如硼)，形成歐姆接觸區343。
自對準的接觸開口389互相離得很近，使得MOSFET器件中有源器件的間距P小於1.0微米。更確切地說，本發明的各個方面提出了允許器件的間距P小於0.6微米。即使當器件的間距尺寸小於1.0微米時，由於接觸開口389的自對準消除了對準誤差，因此這個間距也是可能的。這樣可以確保來自於歐姆接觸區343的摻雜物仍然在通道外，從而保持了器件的閾值電壓。另外，由於溝槽側壁和導電插頭之間的距離將在這個器件上基本保持恒定，因此接觸開口389的自對準有利於精確控制寄生BJT的開啟。恒定的間距使得本體區電阻和本體區中的電壓降在整個器件上也基本保持恒定。因此，對於每個有源器件來說，使寄生BJT開啟的情況有 微小的差別。
如圖3E所示，器件300還可以含有一個靜電放電(ESD)保護結構395。ESD保護結構395可以是形成在雙層硬掩膜中第一層356上方的導電材料396。選擇性摻雜導電材料396，使其含有N-型和P-型區。絕緣層397形成在導電材料396的頂面上方。
如圖3E所示，器件300還可以選擇含有一個或多個閘極拾取溝槽370’。閘極拾取溝槽370’與有源器件溝槽370基本類似。然而，閘極拾取電極322代替電絕緣閘極電極309，穿過閘極拾取溝槽370’上方的閘極蓋308的電連接結構320將閘極拾取電極322電連接到閘極金屬324上。作為示例，但不作為局限，電連接結構320可以是鎢。閘極拾取溝槽370’可以形成在深摻雜區361中，深摻雜區361的摻雜物導電類型與襯底301相反。作為示例，但不作為局限，如果襯底301為N-型，那麼深摻雜區361將摻雜P-型，在這種情況下，有時也稱為“P-槽(P-Tub)”。還可選擇，如果襯底301為P-型，那麼深摻雜區361將摻雜N-型，在這種情況下，有時也稱為“N-槽(N-Tub)”。
圖3F表示還可以選擇為器件300配置一個或多個肖特基接觸結構，使電場終止。肖特基接觸結構與P-深摻雜區361相結合，也可以作為本體鉗位(Body clamp，簡稱BCL)，用於防止有源器件在高於它們擊穿電壓的情況下運行。如圖3F所示，金屬接觸結構321或稱電連接結構將肖特基金屬325電連接到P-深摻雜區361以外的半導體襯底301。作為示例，接觸結構321可以穿過具有第一層356和第二層(第二層可以是前述的絕緣層355)的硬掩膜延伸。作為示例，但不作為局限，第一層可以是氮化層，第二層可以是氧化層。作為示例，但不作為局限，金屬接觸結構321可以是鎢。肖特基金屬325可以形成在金屬接觸321和硬掩膜的第一層356上方，並且與閘極金屬324絕緣。另外，閘極金屬324和肖特基金屬325之間相互電絕緣。肖特基金屬325可連接到源極金屬。
圖4表示器件結構300的布局圖。該布局表示閘極電極309和導電插頭357交替出現在器件區中。作為源極接觸結構的導電插頭357垂直於圖平面延伸，與源極金屬317電接觸。閘極滑道319電連接到閘極電 極309，連接到閘極拾取電極322。閘極電極、閘極滑道和閘極拾取電極可以由同種材料(例如多晶矽)制成，在一個共同的過程中這種材料形成在相應的溝槽中。作為閘極接觸結構的金屬接觸結構321垂直於圖平面延伸，以便與閘極金屬324電接觸(圖中沒有表示出)。閘極金屬324最初作為與源極金屬317部分相同的金屬層形成。例如通過常用的掩膜、刻蝕、電介質填充等工藝，閘極金屬324與源極金屬317和/或肖特基金屬325電絕緣。
BCL區位於有源器件區外部，這可以從圖4所示肖特基金屬325的位置看出。另外，ESD結構395可以形成在有源器件區外部。ESD結構395形成在絕緣層355等絕緣物上方。
本發明的各個方面提出了圖3A-1到3E所示器件的制備方法。結合所述的制備方法，圖5A-5J表示在制備過程的不同階段中，器件結構500的剖面圖。
圖5A表示半導體襯底501。襯底501可以適當摻雜成N-型或P-型襯底。為了解釋說明，此處所用的半導體襯底501將是N-型襯底。半導體襯底501包括一個重摻雜汲極接觸區502，用於汲極接觸，帶有一個輕摻雜外延層507或外延區生長在汲極接觸區502上方。重摻雜P-槽561形成在外延層507中。利用離子注入或其他任意適當的方法，制備P-槽。作為示例，但不作為局限，P-槽掩膜可以和P-型摻雜物的掩膜注入一起使用。硬掩膜具有一個第一絕緣層556和一個第二絕緣層555，形成在半導體襯底501的頂面上。第二絕緣層555可以抵抗刻蝕第一絕緣層556的第一次刻蝕工藝，第一絕緣層556可以抵抗刻蝕第二絕緣層555的第二次刻蝕工藝。作為示例，但不作為局限，第一絕緣層556可以是氮化層，第二絕緣層555可以是氧化物。作為示例，第一絕緣層556的厚度約為0.2μm至0.5μm，第二絕緣層555的厚度約為50Å至250Å。
在圖5B中，利用溝槽掩膜，穿過硬掩膜的第一和第二絕緣層556、555刻蝕，限定溝槽570的位置。另外，閘極拾取溝槽570’也可以在同一個刻蝕工藝中限定。然後，在圖5C中，利用部分溝槽刻蝕，制備溝槽570和570’的頂部571。溝槽571的頂部大約為溝槽570總深度的一半左右。作為示例，但不作為局限，溝槽頂部的深度D1 約為0.5μm。通過寬 度為WM 的臺面結構將每個溝槽570與其他溝槽分開。作為示例，寬度WM 為0.2μm至0.5μm之間。作為示例，每個溝槽寬度WT 為0.2μm至0.5μm之間。
在圖5D中，薄襯墊氧化物575和絕緣墊片546內襯在溝槽571的頂部。襯墊氧化物575和絕緣墊片546防止溝槽的頂部571在溝槽底部572的處理過程中生長氧化物。絕緣墊片546還作為一個額外的掩膜層，以縮減溝槽底部572的寬度。作為示例，絕緣墊片546可以是氮化物。形成絕緣墊片546之後，可以通過刻蝕工藝，制備溝槽底部572。作為示例，但不作為局限，溝槽第二部分即底部572的深度D2 增加到約0.5μm，致使溝槽570、570’的總深度DT 約為1.0μm。
然後，在圖5E中，形成底部絕緣層574。作為示例，但不作為局限，通過熱氧化，生長氧化物，形成底部絕緣層574。厚度T2 的範圍通常為400Å-1500Å。在圖5F中，首先除去襯墊氧化物575和絕緣墊片546。然後，生長頂部絕緣層573，如閘極氧化物。厚度T1 的範圍通常為50Å-500Å。雖然厚度T1 和T2 的範圍稍有重疊，但是我們要求底部絕緣層574的厚度T2 大於頂部絕緣層573的厚度T1 。生長頂部絕緣層573之後，用導電材料填充溝槽570和570’，以便在有源器件中形成閘極電極509，在閘極拾取溝槽570’中形成閘極拾取電極522。為了使溝槽內閘極電極509和閘極拾取電極522中形成空隙的可能性降至最低，溝槽的寬度和深度之比應不應超過1：6。作為示例，但不作為局限，用於填充閘極電極509和閘極拾取電極522的導電材料可以是摻雜了N-型摻雜物的多晶矽。一旦填充溝槽570和570’之後，向下刻蝕導電材料，以便與半導體襯底501的頂面基本相平。
在圖5G中，形成絕緣閘極蓋508。絕緣閘極蓋508可以用沉積的氧化物制備，例如但不局限於含有硼酸的矽玻璃(BPSG)或四乙基原矽酸鹽(TEOS)。沉積絕緣閘極蓋508之後，使其表面與硬掩膜的第一絕緣層556的頂面相平。作為示例，但不作為局限，可以利用化學機械平整化(CMP)進行平整。由於最初刻蝕硬掩膜第一絕緣層556和第二絕緣層555的存在，以形成溝槽掩膜，因此閘極蓋508自對準。無需額外的掩膜對準工藝，就可以改善閘極蓋508的對準。另外，閘極蓋508的自對準為自 對準的源極接觸提供了基礎。因此，准確地對準閘極蓋508是非常關鍵的。
絕緣閘極蓋508制成之後，通過掩膜和第一刻蝕工藝，在器件500的有源區中除去硬掩膜的第一絕緣層556。第一次刻蝕工藝選擇性地除去硬掩膜的第一層556，對硬掩膜的第二絕緣層555基本不會造成影響。作為示例，如果硬掩膜的第一絕緣層556為氮化物，硬掩膜第二絕緣層555為氧化物，那麼熱磷酸濕法腐蝕就會優先除去氮化物，而保留氧化物。
一旦除去了硬掩膜第一絕緣層556，則在外延層507中形成耗盡P-屏蔽區544和P-連接器區545，譬如圖5H”-1所示。在700KeV和1000KeV的注入能量下，通過離子注入系統，將P-型摻雜物注入到外延層中。當P-屏蔽區544需要延伸到溝槽570下方時，例如當制備類似於圖3D-1和3D-2所示的正交超級結器件300’”時，可以在底部或頂部絕緣層574、573內襯溝槽之前，通過溝槽570的底部，注入P-型摻雜物。依據本發明的一個可選方面，P-屏蔽區544和P-連接器區545可以生長成為外延層507的一部分。依據本發明的這一方面，當制備外延層507時，可以生長外延層507的底部作為P-型外延層。然後，在需要N-型的底部外延層區域中注入N-型摻雜物，以便形成N-連接區576，譬如圖5H”-2所示。如果有必要，還可以穿過溝槽底部，注入N-型摻雜物，從而在溝槽570下面，形成N-型外延層507。
除去了第一硬掩膜層556，則在外延層507的頂部注入P-本體層503和N+ -源極區504。注入P-本體層503和N+ -源極區504可以發生在注入P-屏蔽區544之前、之後或之中。然後，沿閘極蓋508的側壁形成絕緣墊片541，以避免在閘極電極509和源極金屬517之間發生短路。在器件的裸露表面上沉積一個絕緣層，然後通過各向異性刻蝕工藝刻蝕掉絕緣層，形成絕緣墊片541。各向異性刻蝕會留下沿閘極蓋508側壁的那部分絕緣層，作為絕緣墊片541。作為示例，但不作為局限，各向異性刻蝕工藝可以是反應離子刻蝕(RIE)。絕緣墊片541應足夠厚，以承載滿閘極額定電壓。作為示例，墊片厚度約為500Å至1500Å。
氧化之後，沿硬掩膜第二層555的頂面，在絕緣墊片541的裸露表面上以及閘極蓋508的頂面上，沉積一個多晶矽層。用高濃度的N- 型摻雜物，摻雜多晶矽層。然後，利用各向異性刻蝕除去多晶矽層，僅保留多晶矽墊片542，絕緣墊片541將多晶矽墊片542與閘極蓋508的側壁分隔開。作為示例，但不作為局限，各向異性刻蝕工藝可以是反應離子刻蝕(RIE)。穿過硬掩膜第二層555，也進行各向異性刻蝕工藝。此外，利用多晶矽墊片542，通過擴散工藝代替上述注入工藝，形成源極區504。將N-型摻雜物從多晶矽墊片542，擴散到墊片542下方的外延層507頂部，形成源極區504。
外延層507的頂部裸露出來之後，穿過外延層，再一次利用各向異性刻蝕工藝，使帶有自對準接觸開口547的P-本體層503裸露出來。多晶矽墊片542保護下面的源極區504，從而使源極區504在整個器件500上保持尺寸一致。為了提供更好的源極金屬517歐姆接觸，可以在自對準的接觸開口547的表面中注入高濃度的P-型摻雜物，以便形成歐姆接觸區543。作為示例，可以利用硼表面注入，形成歐姆接觸區543。
依據本發明的其他方面器件500還可以具有ESD結構595。圖5H’表示在從有源區中除去硬掩膜第一絕緣層556之前，形成ESD結構595。作為示例，可以通過在器件500的頂面上方首先沉積一個未摻雜的多晶矽層，制備ESD結構。然後利用第一個ESD掩膜，將N-型摻雜物選擇性地摻雜到多晶矽區域，成為ESD二極管596。可以在P-本體注入時注入ESD二極管596的P-型部分。然後，利用第二個ESD掩膜，選擇性地除去多晶矽層，以便形成ESD二極管596。在ESD二極管596上方生長一個絕緣層597，在後續的處理工藝中提供保護。此後，依據圖5H所示的工藝，處理器件500。
回到器件500，按照標准的接觸形成工藝繼續進行。在圖5I中，在器件的頂面上沉積一個光致抗蝕劑層516。利用閘極接觸掩膜，穿過閘極拾取電極522上方的閘極蓋508，形成一個開口。另外，閘極接觸掩膜所提供的開口，使得第一和第二硬掩膜層556、555在非有源區中可以被刻蝕穿透，形成肖特基結構的接觸結構520。在圖5J中，除去光致抗蝕劑層，制備器件500，用於金屬化。源極接觸結構557或稱導電插頭形成在自對準接觸開口547中。作為示例，但不作為局限，源極接觸結構可以是鎢。還 可以制備接觸結構520，閘極拾取電極522上方的絕緣閘極蓋508中的開口內的接觸結構520(或稱電連接結構)將閘極拾取電極522連接到閘極金屬524，並且第一和第二絕緣層556、555在器件的非有源區被刻蝕形成的開口內的接觸結構520將肖特基金屬525連接到襯底501。作為示例，接觸結構520可以由鎢制成。最終，在器件的頂面上沉積一個金屬層。然後利用金屬掩膜刻蝕金屬層，形成源極金屬517，閘極拾取金屬524以及肖特基金屬525，並將肖特基金屬525連接到源極金屬517。
本發明的各個方面還提出了一個制備二階溝槽氧化層的額外工藝。首先，在圖6A中，利用刻蝕工藝，穿過硬掩膜，在襯底601中形成溝槽670、670’，硬掩膜具有第一絕緣層656和第二絕緣層655形成在半導體襯底601的頂面上。襯底601含有一個重摻雜N+ 汲極區602和外延層607。溝槽770和溝槽770’基本類似。溝槽770可以用作有源MOSFET結構，位於器件700的有源區中。溝槽770’可用作閘極拾取結構，位於器件的非有源區中。如圖所示，溝槽770’形成在P-槽761中。所形成的溝槽670、670’深度為DT ，寬度為WT 。作為示例，深度DT 約為1.0微米，寬度WT 約在0.2μm至0.5μm之間。溝槽通過一個臺面結構相互分隔開，臺面結構的寬度WM 約為0.2μm-0.5μm。
形成溝槽670、670’之後，如圖6B所示，沿溝槽壁和溝槽底面，形成一個絕緣層674。絕緣層674的厚度為T2 。作為示例，但不作為局限，厚度T2 約為400Å至1500Å。然後，用導電材料的第一部分6091 填充溝槽670、670’。向下回刻導電材料6091 ，使它僅填充溝槽的底部672。
在圖6C中，刻蝕掉溝槽頂部671的絕緣層674。導電材料的第一部分6091保護溝槽底部672的絕緣層674不受刻蝕影響。然後，在溝槽的頂部671側壁上生長頂部絕緣層673。頂部絕緣層673的厚度為T1 。作為示例，但不作為局限，厚度T1 約為50Å至500Å。另外，要注意的是，雖然厚度T1 和T2 的範圍稍有重疊，但是我們要求T2 仍然應大於T1 。在生長頂部絕緣層673時，還可以在導電材料的第一部分6091 頂面上方，形成一個絕緣層673’。導電材料609兩部分之間的絕緣層673’將使閘極電極的底部不處於閘極電勢。然而，僅刻蝕掉不需要的絕緣層673’會對頂部絕緣層 673造成損壞。
因此，在圖6D中，用導電材料第二部分6092 填充溝槽670。然後，利用各向異性刻蝕工藝，除去導電材料的第二部分6092 ，僅僅保留側壁墊片，保護頂部絕緣層673不受後續刻蝕工藝的影響。然後，通過適當的刻蝕工藝，除去不需要的絕緣層673’。除去後，用導電材料的第三部分6093 填充溝槽770的剩餘部分，如圖6E所示。此後的處理工藝按照器件500的工藝進行。
盡管以上是本發明的較佳實施例的完整說明，但是也有可能使用各種可選、修正和等效方案。因此，本發明的範圍不應局限於以上說明，而應由所附的申請專利範圍書及其全部等效內容決定。本方法中所述步驟的順序並不用於局限進行相關步驟的特定順序的要求。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。在以下申請專利範圍中，除非特別聲明，否則不定冠詞“一個”或“一種” 都指下文內容中的一個或多個項目的數量。除非在指定的申請專利範圍中用“意思是”特別指出，否則所附的申請專利範圍書應認為是包括意義及功能的限制。
317‧‧‧源極金屬
308‧‧‧絕緣閘極蓋
389‧‧‧自對準接觸開口
341‧‧‧絕緣墊片
342‧‧‧N+ -摻雜多晶矽墊片
357‧‧‧導電插頭
341‧‧‧絕緣墊片
308‧‧‧絕緣閘極蓋
355‧‧‧絕緣層
357‧‧‧導電插頭
304‧‧‧N+ -摻雜源極區
343‧‧‧歐姆接觸區
301‧‧‧襯底
303‧‧‧汲極端P-本體層
371‧‧‧頂部
309‧‧‧閘極電極
307‧‧‧外延層
373‧‧‧頂部絕緣層
309‧‧‧閘極電極
372‧‧‧底部
374‧‧‧閘極氧化物
344‧‧‧耗盡的P-屏蔽區
307‧‧‧外延層
370‧‧‧溝槽
302‧‧‧N+ 汲極區

Claims (28)

  1. 一種用於制備MOSFET器件的方法，包括：a)在第一導電類型的半導體襯底頂面上方，制備一個硬掩膜，其中硬掩膜包括第一和第二絕緣層，其中第二絕緣層抵抗刻蝕第一絕緣層的第一次刻蝕工藝，第一絕緣層可以抵抗刻蝕第二絕緣層的第二次刻蝕工藝；b)通過硬掩膜中的開口，刻蝕半導體襯底，以便在半導體襯底中形成多個溝槽，其中溝槽包括溝槽頂部和溝槽底部；c)用第一厚度T1的頂部絕緣層內襯溝槽頂部，用第二厚度T2的底部絕緣層內襯溝槽底部，其中T2大於T1；d)在溝槽中沉積導電材料，形成多個閘極電極；e)在閘極電極上方制備絕緣閘極蓋至少達到硬掩膜第二絕緣層的水平處，其中絕緣閘極蓋由可以被第一次刻蝕工藝刻蝕，同時抵抗第二次刻蝕工藝的材料制成；f)利用第一次刻蝕工藝，除去硬掩膜的第一絕緣層，保留與溝槽對準的絕緣閘極蓋，絕緣閘極蓋突出至硬掩膜第二絕緣層的上方；g)在襯底頂部，制備一個本體層，其中本體層為與第一導電類型相反的第二導電類型；h)制備一個第二導電類型的耗盡屏蔽區，在半導體襯底的深處，至少部分在溝槽底面以下，其中耗盡屏蔽區電連接到本體層；i)在硬掩膜的第二絕緣層和絕緣閘極蓋上方，制備一個絕緣墊片層；j)在絕緣墊片層上方，制備一個導電或半導體墊片層，並且各向異性地刻蝕導電或半導體墊片層和絕緣墊片層，保留沿著絕緣閘極蓋側壁的那部分導電或半導體墊片層和絕緣墊片層，作為導電或半導體墊片和絕緣墊片；並且k)利用導電或半導體墊片作為自對準掩膜，在半導體襯底中形成開口，用於源極接觸。
  2. 如申請專利範圍第1項所述的方法，其中一個或多個耗盡屏蔽區穿過襯底延伸到第一導電類型的汲極區中，汲極區形成在襯底底部。
  3. 如申請專利範圍第1項所述的方法，其中一個或多個耗盡屏蔽區完全形成在溝槽底面以下。
  4. 如申請專利範圍第1項所述的方法，其中耗盡屏蔽區和本體層之間的連接建立在器件的一個主平面中。
  5. 如申請專利範圍第1項所述的方法，其中耗盡屏蔽區和本體層之間的連接建立在器件的二次平面中，其中器件的二次平面和器件的主平面正交。
  6. 如申請專利範圍第5項所述的方法，其中一部分耗盡屏蔽區未連接到本體層，其中配置一部分襯底，將耗盡屏蔽區未連接到本體層的部分與耗盡屏蔽區連接到本體層的部分隔開，以便將溝槽附近第一導電類型的外延區，連接到襯底底部第一導電類型的汲極區。
  7. 如申請專利範圍第6項所述的方法，其中耗盡屏蔽區的未連接到本體層的部分繼續延伸到主平面中的兩個或多個溝槽以下，與外延區連接到汲極區的部分襯底形成正交的超級結結構。
  8. 如申請專利範圍第1項所述的方法，其中制備多個溝槽包括穿過硬掩膜和襯底中的開口刻蝕，形成溝槽的頂部；沿溝槽頂部的側壁和底面生長一個頂部絕緣層，並且沿側壁在頂部絕緣層上制備墊片；將墊片作為掩膜，刻蝕沉積在溝槽頂部底面上的絕緣層，以及溝槽頂部下方的襯底，形成溝槽的底部；沿溝槽底部的側壁和底面，生長底部絕緣層；並且除去墊片。
  9. 如申請專利範圍第1項所述的方法，其中制備多個溝槽包括穿過硬掩膜和襯底中的開口刻蝕，形成溝槽的頂部和底部；沿溝槽頂部和底部的側壁和底面生長一個底部絕緣層；用第一部分導電材料填充溝槽底部；從溝槽頂部除去底部絕緣層；沿溝槽頂部側壁以及沿溝槽底部中導電材料的頂面，生長頂部絕緣層；利用第二部分導電材料在頂部絕緣層上沿側壁形成墊片；並且從溝槽底部中導電材料的頂面上刻蝕掉頂部絕緣層。
  10. 如申請專利範圍第1項所述的方法，還包括：在襯底頂部，制備一個第一導電類型的源極區。
  11. 如申請專利範圍第1項所述的方法，其中在襯底中制備多個溝槽還包括制備一個或多個閘極拾取溝槽，其中在溝槽中沉積導電材料還包括在閘極拾取溝槽中沉積導電材料，以形成閘極拾取電極。
  12. 如申請專利範圍第11項所述的方法，其中一個或多個閘極拾取溝槽形成在第二導電類型的摻雜槽中，摻雜槽形成在半導體襯底中。
  13. 如申請專利範圍第1項所述的方法，還包括：在通過硬掩膜的第一層上方沉積一層導電材料，並且利用ESD掩膜和ESD刻蝕工藝，除去硬掩膜的第一層之前，先在硬掩膜的第一層上方，制備一個靜電放電(ESD)保護電極。
  14. 如申請專利範圍第13項所述的方法，還包括在除去硬掩膜的第二層之前，先氧化ESD保護電極的表面。
  15. 如申請專利範圍第1項所述的方法，還包括：配置一個或多個肖特基接觸結構，以終止器件，其中制備肖特基接觸結構還包括制備一個或多個本體鉗位(BCL)結構。
  16. 如申請專利範圍第1項所述的方法，還包括：在半導體襯底中的開口附近，制備一個歐姆接觸區，用於源極接觸，其中歐姆接觸區具有高濃度的第二導電類型摻雜物。
  17. 一種MOSFET器件，包括：一個第一導電類型的半導體襯底，其中襯底包括一個輕摻雜的外延區，在襯底頂部；一個第二導電類型的本體區，形成在半導體襯底頂部，其中第二導電類型與第一導電類型相反；半導體襯底和本體區構成的多個有源器件結構，其中每個有源器件結構都含有一個與閘極氧化物絕緣的閘極電極，其中閘極氧化物頂部的厚度為T1，閘極氧化物底部的厚度為T2，其中T2大於T1；一個第二導電類型的耗盡屏蔽區形成在半導體襯底中，在半導體襯底的深處，至少部分在溝槽底面以下，其中耗盡屏蔽區電連接到本體層；一個絕緣閘極蓋形成在每個閘極電極上方，其中絕緣墊片形成在絕緣閘極蓋的側壁上，導電或半導體墊片形成在絕緣墊片的裸露側壁上，絕緣層在本體區的頂面上；一個導 電源極金屬層形成在絕緣層上方；一個或多個電連接，將源極金屬層與一個或多個源極區連接起來，其中絕緣墊片將一個或多個電連接與絕緣閘極蓋分開。
  18. 如申請專利範圍第17項所述的MOSFET器件，其中耗盡屏蔽區中的一個或多個耗盡屏蔽區穿過襯底延伸到襯底底部第一導電類型的汲極區。
  19. 如申請專利範圍第17項所述的MOSFET器件，其中一個或多個耗盡屏蔽區全部形成在溝槽的底面以下。
  20. 如申請專利範圍第17項所述的MOSFET器件，其中耗盡屏蔽區和本體層之間的連接在器件的主平面中。
  21. 如申請專利範圍第17項所述的MOSFET器件，其中耗盡屏蔽區和本體層之間的連接在器件的二次平面中，其中器件的二次平面與器件的主平面正交。
  22. 如申請專利範圍第21項所述的MOSFET器件，其中一部分耗盡屏蔽區未連接本體層，其中配置一部分襯底，將耗盡屏蔽區未連接本體層的部分與耗盡屏蔽區的連接本體層的部分隔開，以便將溝槽附近第一導電類型的外延區，連接到襯底底部第一導電類型的汲極區。
  23. 如申請專利範圍第22項所述的MOSFET器件，其中耗盡屏蔽區的未連接本體層的部分繼續延伸到主平面中的兩個或多個溝槽以下，與將外延區連接到汲極區的部分襯底形成正交超級結結構。
  24. 如申請專利範圍第17項所述的MOSFET器件，其中導電或半導體墊片為多晶矽墊片，其中用第一導電類型的摻雜物摻雜多晶矽墊片。
  25. 如申請專利範圍第24項所述的MOSFET器件，還包括：多個第一導電類型的源極區，形成在多個溝槽附近的半導體襯底頂部。
  26. 如申請專利範圍第17項所述的MOSFET器件，還包括一個或多個靜電放電(ESD)保護結構。
  27. 如申請專利範圍第17項所述的MOSFET器件，還包括一個或多個閘極拾取溝槽。
  28. 如申請專利範圍第17項所述的MOSFET器件，還包括一個肖特基接觸結構，其中肖特基接觸結構還包括一個本體鉗位結構。
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US20140239382A1 (en) 2014-08-28
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