WO2021042582A1 - 半导体功率器件 - Google Patents

半导体功率器件 Download PDF

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WO2021042582A1
WO2021042582A1 PCT/CN2019/120486 CN2019120486W WO2021042582A1 WO 2021042582 A1 WO2021042582 A1 WO 2021042582A1 CN 2019120486 W CN2019120486 W CN 2019120486W WO 2021042582 A1 WO2021042582 A1 WO 2021042582A1
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gate
type
power device
semiconductor power
type body
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PCT/CN2019/120486
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English (en)
French (fr)
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龚轶
刘伟
刘磊
袁愿林
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苏州东微半导体有限公司
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Priority to US17/257,125 priority Critical patent/US20220328618A1/en
Publication of WO2021042582A1 publication Critical patent/WO2021042582A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode

Definitions

  • This application belongs to the technical field of semiconductor power devices, for example, it relates to a semiconductor power device with a super junction structure.
  • FIG. 1 The cross-sectional structure of a semiconductor power device with a super junction structure in the related art is shown in FIG. 1, and includes: an n-type drain region 31 and an n-type epitaxial layer 30 located on the n-type drain region 31.
  • the n-type drain region 31 passes through
  • the drain metal layer 70 is connected to the drain voltage;
  • a gate trench is formed in the n-type epitaxial layer 30, a gate dielectric layer 35 and a gate 36 are formed in the gate trench, and the gate 36 is controlled by the gate voltage
  • the current channel located in the p-type body region 33 is turned on and off.
  • the p-type body region 33 and the n-type source region 34 are connected to a source voltage through the source metal layer 47.
  • the p-type body contact region 38 with a high doping concentration is used to reduce ohmic contact.
  • a p-type columnar epitaxial doped region 32 is formed under the p-type body region 33.
  • the insulating dielectric layer 50 is an interlayer insulating layer.
  • Miller capacitance (Crss) and its corresponding gate-drain capacitance (Cgd) play an important role in the switching process of semiconductor power devices. Since the gate-drain capacitance of the semiconductor power device of the structure is too small, it will cause a sudden change in the gate-drain capacitance when it is turned on and off, resulting in serious electromagnetic interference.
  • the present application provides a semiconductor power device to solve the problem of serious electromagnetic interference caused by too small gate-drain capacitance of the semiconductor power device in the related art.
  • a semiconductor power device provided by this application includes:
  • An n-type drain region and an n-type epitaxial layer located on the n-type drain region, and the n-type epitaxial layer is provided with:
  • At least two first p-type body regions where an n-type source region is provided in the first p-type body region;
  • Two gate trenches located between two adjacent first p-type body regions, and a second p-type body region is provided between the two gate trenches;
  • a gate dielectric layer and a gate are arranged in the gate trench.
  • the second p-type body region described in the present application is externally connected to a source voltage.
  • the width of the second p-type body region of the present application is smaller than the width of the first p-type body region.
  • the gate trench of the present application includes an upper part and a lower part, the gate and the gate dielectric layer are located in the upper part of the gate trench, and the lower part of the gate trench is provided There are shielding gates and field oxide layers.
  • the shielding gate and the field oxide layer of the present application extend upward into the upper part of the gate trench, and the shielding gate is isolated from the gate by the field oxide layer.
  • the shielding gate of the present application divides the gate into a first gate on the side close to the first p-type body region and a second gate on the side close to the second p-type body region .
  • the first gate of the present application is externally connected to a gate voltage
  • the second gate is externally connected to a source voltage
  • the semiconductor power device provided by the present application has a relatively large gate-drain capacitance, which can reduce electromagnetic interference caused by a sudden change in the gate-drain capacitance when the semiconductor power device is turned on and off.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor power device in the related art
  • FIG. 2 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor power device provided by the present application
  • FIG. 3 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor power device provided by the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor power device provided by the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor power device provided by the present application.
  • a semiconductor power device provided by an embodiment of the present application includes an n-type drain region 20 and an n-type drain region 20.
  • the drain region 20 can be externally connected to the drain voltage through the drain metal layer.
  • FIG. 2 exemplarily shows the structure of three first p-type body regions 24, and at the same time, for the convenience of display and description, FIG. 2 exemplifies the structure of the present application A minimum unit structure 101.
  • An n-type source region 26 is provided in the first p-type body region 24, and a p-type columnar doped region 27 is provided below the first p-type body region 24.
  • the p-type columnar doped region 27 may be the same as the first p-type body region. 24 is connected or not connected.
  • the p-type columnar doped region 27 in FIG. 2 may be connected to the first p-type body region 24.
  • the first p-type body region 24 and the n-type source region 26 may be externally connected to the source voltage through the source metal layer.
  • a second p-type body region 25 is provided between the two gate trenches, optionally, a second p-type body region
  • the width of the body region 25 is smaller than the width of the first p-type body region 24, so that the chip size of the semiconductor power device can be reduced, and the manufacturing cost of the semiconductor power device can be reduced.
  • a gate dielectric layer 22 and a gate 23 are provided in the gate trench.
  • the gate 23 can be externally connected to the gate voltage through the gate metal layer, so that the gate 23 is controlled to be located in the first p-type body region 24 by the gate voltage The opening and closing of the current channel.
  • two gate trenches are provided between adjacent first p-type body regions to form two gate structures, which can increase the gate-drain capacitance of the semiconductor power device Therefore, the electromagnetic interference caused by the sudden change of the gate-drain capacitance when the semiconductor power device is turned on and off can be reduced.
  • Arranging a second p-type body region between the two gate trenches can reduce the electric field intensity at the bottom of the gate, so that the manufacturing process window of the semiconductor power device becomes larger, and the manufacturing stability of the semiconductor power device is improved.
  • a source voltage can be applied to the second p-type body region, which can further reduce the electric field intensity at the bottom of the gate.
  • FIG. 3 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor power device provided by the present application.
  • the gate trench of the semiconductor power device in the embodiment of the present application includes two parts, an upper part and a lower part. 23 and the gate dielectric layer 22 are located in the upper part of the gate trench, and a shield gate 28 and a field oxide layer 27 are provided in the lower part of the gate trench.
  • the shielding gate 28 can be externally connected to the source voltage, so that the electric field strength at the lower part of the gate trench can be adjusted, and the withstand voltage of the semiconductor power device can be improved.
  • FIG. 4 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor power device provided by the present application.
  • the semiconductor power device in the embodiment of the present application is based on the semiconductor power device shown in FIG. 3 .
  • the shielding gate 28 and the field oxide layer 27 are extended up to the upper part of the gate trench, and the shielding gate 28 is isolated from the gate by the field oxide layer 27.
  • the gate can be divided into a first gate 23a close to the first p-type body region 24 and a second p-type body region 25.
  • One side of the second gate 23b One side of the second gate 23b.
  • the first gate 23a and the second gate 23b can be connected to the gate voltage at the same time, or the first gate 23a is connected to the gate voltage, and the second gate 23b is connected to the source. Voltage.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

一种半导体功率器件，包括：n型漏区（20）以及位于所述n型漏区（20）之上的n型外延层（21），所述n型外延层（21）中设有：至少两个第一p型体区（24），所述第一p型体区（24）内设有n型源区（26）；位于所述第一p型体区（24）下方的p型柱状掺杂区（27）；位于相邻两个所述第一p型体区（24）之间的两个栅极沟槽，该两个栅极沟槽之间设有第二p型体区（25）；所述栅极沟槽内设有栅介质层（22）和栅极（23）。

Description

半导体功率器件
本公开要求在2019年09月03日提交中国专利局、申请号为201910829144.0的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请属于半导体功率器件技术领域，例如涉及一种超结结构的半导体功率器件。
背景技术
相关技术的一种超结结构的半导体功率器件的剖面结构如图1所示，包括：n型漏区31和位于n型漏区31之上的n型外延层30，n型漏区31通过漏极金属层70接漏极电压；在n型外延层30内形成有栅极沟槽，在栅极沟槽内形成有栅介质层35和栅极36，栅极36通过栅极电压来控制位于p型体区33内的电流沟道的开启和关断。p型体区33和n型源区34通过源极金属层47接源极电压。高掺杂浓度的p型体区接触区38用于降低欧姆接触。在p型体区33的下方形成有p型柱状外延掺杂区32。绝缘介质层50为层间绝缘层。
超结结构的半导体功率器件在开启和关断过程中，米勒电容(Crss)及其所对应的栅漏电容(Cgd)对半导体功率器件的开关过程起到重要的作用，相关技术的超结结构的半导体功率器件由于栅漏电容过小，在开启和关断时会导致栅漏电容发生突变，从而导致电磁干扰严重。
发明内容
本申请提供一种半导体功率器件，以解决相关技术中的半导体功率器件由于栅漏电容过小导致的电磁干扰严重的问题。
本申请提供的一种半导体功率器件，包括：
n型漏区以及位于所述n型漏区之上的n型外延层，所述n型外延层中设有：
至少两个第一p型体区，所述第一p型体区内设有n型源区；
位于所述第一p型体区下方的p型柱状掺杂区；
位于相邻两个所述第一p型体区之间的两个栅极沟槽，该两个栅极沟槽之间设有第二p型体区；
所述栅极沟槽内设有栅介质层和栅极。
可选的，本申请所述第二p型体区外接源极电压。
可选的，本申请所述第二p型体区的宽度小于所述第一p型体区的宽度。
可选的，本申请所述栅极沟槽包括上部和下部两部分，所述栅极和所述栅介质层位于所述栅极沟槽的上部内，所述栅极沟槽的下部内设有屏蔽栅和场氧化层。
可选的，本申请所述屏蔽栅和所述场氧化层向上延伸至所述栅极沟槽的上部内，所述屏蔽栅通过所述场氧化层与所述栅极隔离。
可选的，本申请所述屏蔽栅将所述栅极分割为靠近所述第一p型体区一侧的第一栅极和靠近所述第二p型体区一侧的第二栅极。
可选的，本申请所述第一栅极外接栅极电压，所述第二栅极外接源极电压。
本申请提供的一种半导体功率器件具有较大的栅漏电容，可以降低半导体功率器件在开启和关断时由于栅漏电容突变导致的电磁干扰。
附图说明
图1是相关技术的一种半导体功率器件的剖面结构示意图；
图2是本申请提供的一种半导体功率器件的第一个实施例的剖面结构示意图；
图3是本申请提供的一种半导体功率器件的第二个实施例的剖面结构示意图；
图4是本申请提供的一种半导体功率器件的第三个实施例的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。
应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列图形大小并不代表实际尺寸，说明书附图是示意性的，不应限定本申请的范围。说明书中所列实施例不应仅限于说明 书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图2是本申请提供的一种半导体功率器件的第一个实施例的剖面结构示意图，如图2所示，本申请实施例提供的一种半导体功率器件，包括n型漏区20，n型漏区20可以通过漏极金属层外接漏极电压。位于n型漏区20之上的n型外延层21，以及位于n型外延层21中的：
至少两个第一p型体区24，图2中示例性的示出了3个第一p型体区24结构，同时为了方便展示和说明，图2中示例性的框出了本申请的一个最小单元结构101。
第一p型体区24内设有n型源区26，第一p型体区24的下方设有p型柱状掺杂区27，p型柱状掺杂区27可以与第一p型体区24相连接，也可以不连接，示例性的，图2中的p型柱状掺杂区27可以与第一p型体区24相连接。第一p型体区24和n型源区26可以通过源极金属层外接源极电压。
位于相邻的两个第一p型体区24之间的两个栅极沟槽，该两个栅极沟槽之间设有第二p型体区25，可选的，第二p型体区25的宽度小于第一p型体区24的宽度，这样可以减小半导体功率器件的芯片尺寸，降低半导体功率器件的制造成本。
栅极沟槽中设有栅介质层22和栅极23，栅极23可以通过栅极金属层外接栅极电压，由此栅极23通过栅极电压来控制位于第一p型体区24中的电流沟道的开启和关断。
本申请实施列的一种半导体功率器件，在相邻的第一p型体区之间设置两个栅极沟槽，从而形成两个栅极结构，这样能够增大半导体功率器件的栅漏电容，从而可以降低半导体功率器件在开启和关断时由于栅漏电容突变导致的电磁干扰。在两个栅极沟槽之间设置第二p型体区，可以降低栅极底部处的电场强度，使得半导体功率器件的制造工艺窗口变大，提高半导体功率器件的制造稳定性，同时，可选的，可以使第二p型体区外加源极电压，可以进一步降低栅极底部处的电场强度。
图3是本申请提供的一种半导体功率器件的第二个实施例的剖面结构示意图，如图3所示，本申请实施列的半导体功率器件栅极沟槽包括上部和下部两部分，栅极23和栅介质层22位于栅极沟槽的上部内，栅极沟槽的下部内设有 屏蔽栅28和场氧化层27。屏蔽栅28可以外接源极电压，从而可以调节栅极沟槽的下部处的电场强度，提高半导体功率器件的耐压。
图4是本申请提供的一种半导体功率器件的第三个实施例的剖面结构示意图，如图4所示，本申请实施列的半导体功率器件是在图3所示的半导体功率器件的基础上，将屏蔽栅28和场氧化层27向上延伸至栅沟槽的上部内，屏蔽栅28通过场氧化层27与栅极隔离。屏蔽栅28和场氧化层27向上延伸至栅沟槽的上部内时，可以将栅极分割为靠近第一p型体区24一侧的第一栅极23a和靠近第二p型体区25一侧的第二栅极23b，此时第一栅极23a和第二栅极23b可以同时外接栅极电压，也可以是第一栅极23a外接栅极电压，第二栅极23b外接源极电压。

Claims (7)

  1. 一种半导体功率器件，包括：
    n型漏区以及位于所述n型漏区之上的n型外延层，所述n型外延层中设有：
    至少两个第一p型体区，所述第一p型体区内设有n型源区；
    位于所述第一p型体区下方的p型柱状掺杂区；
    位于相邻两个所述第一p型体区之间的两个栅极沟槽，该两个栅极沟槽之间设有第二p型体区；
    所述栅极沟槽内设有栅介质层和栅极。
  2. 如权利要求1所述的一种半导体功率器件，其中，所述第二p型体区外接源极电压。
  3. 如权利要求1所述的一种半导体功率器件，其中，所述第二p型体区的宽度小于所述第一p型体区的宽度。
  4. 如权利要求1所述的一种半导体功率器件，其中，所述栅极沟槽包括上部和下部两部分，所述栅极和所述栅介质层位于所述栅极沟槽的上部内，所述栅极沟槽的下部内设有屏蔽栅和场氧化层。
  5. 如权利要求4所述的一种半导体功率器件，其中，所述屏蔽栅和所述场氧化层向上延伸至所述栅极沟槽的上部内，所述屏蔽栅通过所述场氧化层与所述栅极隔离。
  6. 如权利要求5所述的一种半导体功率器件，其中，所述屏蔽栅将所述栅极分割为靠近所述第一p型体区一侧的第一栅极和靠近所述第二p型体区一侧的第二栅极。
  7. 如权利要求6所述的一种半导体功率器件，其中，所述第一栅极外接栅极电压，所述第二栅极外接源极电压。
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Publication number Priority date Publication date Assignee Title
CN116137282A (zh) * 2021-11-17 2023-05-19 苏州东微半导体股份有限公司 半导体超结功率器件
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020175383A1 (en) * 2000-12-06 2002-11-28 Fairchild Semiconductor Corporation MOS-gated power device with doped polysilicon body and process for forming same
CN102130000A (zh) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 沟槽型双层栅mos器件的制备方法
CN102646709A (zh) * 2012-04-06 2012-08-22 东南大学 一种快速超结纵向双扩散金属氧化物半导体管
CN104952928A (zh) * 2015-04-30 2015-09-30 苏州东微半导体有限公司 一种栅漏电容缓变的超结功率器件及其制造方法
CN105161540A (zh) * 2015-09-15 2015-12-16 电子科技大学 一种具有低米勒电容的vdmos器件结构及其制备方法
CN106229343A (zh) * 2016-08-12 2016-12-14 上海鼎阳通半导体科技有限公司 超结器件

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5297706B2 (ja) * 2008-07-07 2013-09-25 ルネサスエレクトロニクス株式会社 半導体装置
JP2012204636A (ja) * 2011-03-25 2012-10-22 Toshiba Corp 半導体装置およびその製造方法
CN203659877U (zh) * 2013-10-30 2014-06-18 英飞凌科技奥地利有限公司 超结器件和包括所述超结器件的半导体结构
CN108258027A (zh) * 2016-12-28 2018-07-06 苏州东微半导体有限公司 一种超级结功率晶体管及其制备方法
CN207183281U (zh) * 2017-09-01 2018-04-03 无锡紫光微电子有限公司 一种可调节开关速度的沟槽栅超结半导体器件
CN109755310B (zh) * 2017-11-01 2021-01-01 苏州东微半导体有限公司 一种分栅结构的功率晶体管
CN109037312B (zh) * 2018-08-23 2024-04-09 无锡市乾野微纳科技有限公司 一种带有屏蔽栅的超结igbt及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020175383A1 (en) * 2000-12-06 2002-11-28 Fairchild Semiconductor Corporation MOS-gated power device with doped polysilicon body and process for forming same
CN102130000A (zh) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 沟槽型双层栅mos器件的制备方法
CN102646709A (zh) * 2012-04-06 2012-08-22 东南大学 一种快速超结纵向双扩散金属氧化物半导体管
CN104952928A (zh) * 2015-04-30 2015-09-30 苏州东微半导体有限公司 一种栅漏电容缓变的超结功率器件及其制造方法
CN105161540A (zh) * 2015-09-15 2015-12-16 电子科技大学 一种具有低米勒电容的vdmos器件结构及其制备方法
CN106229343A (zh) * 2016-08-12 2016-12-14 上海鼎阳通半导体科技有限公司 超结器件

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